CN114706449B

CN114706449B - Frequency control method, circuit and chip based on self-adaptive clock

Info

Publication number: CN114706449B
Application number: CN202210316765.0A
Authority: CN
Inventors: 寇博华; 王彤; 江鹏; 陆启乐; 蒲宇; 石欢
Original assignee: Hangzhou C Sky Microsystems Co Ltd
Current assignee: Hangzhou C Sky Microsystems Co Ltd
Priority date: 2022-03-28
Filing date: 2022-03-28
Publication date: 2024-04-26
Anticipated expiration: 2042-03-28
Also published as: CN114706449A

Abstract

The specification discloses a frequency control method, a circuit and a chip based on an adaptive clock, which are particularly suitable for various chips which are widely applied and comprise an artificial intelligence Internet of things chip and are based on RISC-V architecture instruction sets (or ARM architecture and X86 architecture); when the voltage drop monitoring module monitors that the target processing unit has voltage transient drop and the voltage drop generated in the effective monitoring period reaches at least one threshold value in the set threshold value set, triggering to generate at least one threshold value signal, the clock control module selects the threshold value signal meeting the frequency drop constraint condition as a target threshold value signal, determines a target frequency drop strategy according to the target threshold value signal and the performance signal acquired from the target processing unit, sends the target frequency drop strategy to the clock output module, and the clock output module selects a frequency drop clock signal conforming to the target frequency drop strategy from the frequency drop clock signal set and outputs the frequency drop clock signal to the target processing unit for accurate frequency drop so as to reduce the performance loss of the target processing unit caused by the voltage drop.

Description

Frequency control method, circuit and chip based on self-adaptive clock

Technical Field

The present document relates to the field of integrated circuit technologies, and in particular, to a frequency control method, a circuit, and a chip based on an adaptive clock.

Background

The chip is used as a core component of various electronic devices, and the demand and application of the chip are continuously expanding. Particularly for various chip applications including artificial intelligence internet of things chips based on RISC-V architecture instruction sets (including ARM architecture, X86 architecture as well), for example.

With the continuous shrinking of chip manufacturing process, the density of chip integration is increasing, and the performance of chips is also increasing. Meanwhile, the high-performance module in the chip can more easily cause the problem that the chip generates voltage transient drop in the fast switching of frequency and load, so that the circuit time sequence in the high-performance module can not be ensured, and abnormal work is caused.

At present, a high-performance module is protected by adopting a self-adaptive clock circuit frequency-reducing mode, but the existing frequency-reducing scheme is too rough and can increase power consumption and integrated area, and performance loss is brought to the high-performance module.

Disclosure of Invention

An object of one or more embodiments of the present disclosure is to provide a frequency control method, a circuit and a chip based on an adaptive clock, so as to accurately down-convert different voltage drops of a target processing unit, and reduce or avoid performance loss of the target processing unit due to the voltage drops.

To solve the above technical problems, one or more embodiments of the present specification are implemented as follows:

In a first aspect, a frequency control method based on an adaptive clock is provided, and the frequency control method is applied to an adaptive clock control circuit, where the adaptive clock control circuit includes: the device comprises a voltage drop monitoring module, a clock control module, a clock generation module and a clock output module; the frequency control method comprises the following steps:

The voltage drop monitoring module monitors the voltage of the target processing unit, and triggers a threshold signal corresponding to each threshold value in at least one threshold value set when the voltage drop is monitored to be instantaneously dropped and the voltage drop generated in the effective monitoring period reaches the at least one threshold value in the set threshold value set;

The clock control module receives at least one threshold signal, selects one threshold signal from the threshold signals as a target threshold signal based on a down-conversion constraint condition, and acquires a performance signal from the target processing unit; determining a target frequency-reducing strategy based on the performance signal and the target threshold signal, and sending the target frequency-reducing strategy to the clock output module; the performance signal is used for representing the current load change and/or load state of the target processing unit, and the target frequency-reducing strategy at least comprises frequency-reducing amplitude;

The clock output module selects a down-conversion clock signal corresponding to the target down-conversion strategy from the clock signal set generated by the clock generation module and outputs the down-conversion clock signal to the target processing unit.

In a second aspect, a frequency control circuit based on an adaptive clock is provided, comprising: the device comprises a voltage drop monitoring module, a clock control module, a clock output module and a clock generation module; a plurality of pressure drop thresholds are preset in the pressure drop monitoring module, and each pressure drop threshold corresponds to a threshold signal;

The voltage drop monitoring module monitors the voltage of the target processing unit, and triggers a threshold signal corresponding to each threshold value in at least one threshold value set when the voltage drop generated in the effective monitoring period reaches at least one threshold value in the set threshold value set after the voltage drop is monitored to be instantaneously dropped;

The clock control module receives at least one threshold signal, selects one threshold signal from the at least one threshold signal as a target threshold signal based on a frequency-reducing constraint condition, and acquires a performance signal from the target processing unit; determining a target frequency-reducing strategy based on the performance signal and the target threshold signal, and sending the target frequency-reducing strategy to the clock output module; the performance signal is used for representing the current load change and/or load state of the target processing unit, and the target frequency-reducing strategy at least comprises frequency-reducing amplitude;

In a third aspect, a system on a chip is presented, comprising:

A target processing unit that performs a high-performance processing operation;

And the frequency control circuit of the adaptive clock of the second aspect is in signal connection with the target processing unit, monitors the voltage drop of the target processing unit, and feeds back the adaptively adjusted clock signal to the target processing unit.

In a fourth aspect, a chip is provided, including:

the system-on-chip of the third aspect;

an off-chip bus;

and the memory and the power management circuit are connected with the system on chip through an off-chip bus.

As can be seen from the technical solutions provided in one or more embodiments of the present disclosure, a plurality of pressure drop thresholds are deployed in the pressure drop monitoring module, each pressure drop threshold corresponding to a threshold signal; when the voltage drop monitoring module monitors that the target processing unit has a voltage transient drop and the voltage drop generated in the effective monitoring period reaches at least one threshold value in the set threshold value set, the voltage drop monitoring module can trigger to generate one or more threshold value signals, so that different threshold value signals can be triggered according to different voltage drops. And then, the clock control module selects a threshold signal meeting the down-conversion constraint condition as a target threshold signal, and comprehensively determines a target down-conversion strategy matched with the current voltage transient drop event by using the target threshold signal and a performance signal acquired from a target processing unit. And then the clock signal is sent to a clock output module, and the clock output module selects the down-conversion clock signal conforming to the target down-conversion strategy from the down-conversion clock signal set sent by the clock generation module. And finally, outputting the power to the target processing unit for accurate frequency reduction so as to reduce or avoid the performance loss of the target processing unit caused by pressure drop.

Drawings

For a clearer description of one or more embodiments of the present description or of the solutions of the prior art, reference will be made below to the accompanying drawings which are used in the description of one or more embodiments or of the prior art, it being apparent that the drawings in the description below are only some of the embodiments described in the description, from which, without inventive faculty, other drawings can also be obtained for a person skilled in the art.

Fig. 1 is a schematic circuit configuration diagram of a frequency control scheme based on an adaptive clock according to an embodiment of the present disclosure.

Fig. 2 is a schematic diagram of steps of a frequency control method based on an adaptive clock according to an embodiment of the present disclosure.

FIG. 3 is a schematic diagram of the predictive logic built in the form of state pointers provided by embodiments of the present description.

Fig. 4 is a schematic logic diagram of a target frequency down strategy for determining a frequency down amplitude in combination with a load status signal configuration according to an embodiment of the present disclosure.

Fig. 5 is a schematic diagram of determining and adjusting a down-conversion duration according to an embodiment of the present disclosure.

Fig. 6 is a schematic flow chart of the adaptive clock-based down-conversion control according to the embodiment of the present disclosure.

FIG. 7 is a schematic diagram of a computer system according to one embodiment of the present disclosure.

Detailed Description

In order that those skilled in the art will better understand the technical solutions in this specification, a clear and complete description of the technical solutions in one or more embodiments of this specification will be provided below with reference to the accompanying drawings in one or more embodiments of this specification, and it is apparent that the one or more embodiments described are only a part of embodiments of this specification, not all embodiments. All other embodiments, which can be made by one or more embodiments of the present disclosure without inventive faculty, are intended to be within the scope of the present disclosure.

Considering the complex manufacturing process and the continuous reduction of the volume of the chip, the integrated density of the chip is increased, and the performance of the chip is improved. Under the fast switching of frequency and load, the problem that the power supply network of the chip cannot provide enough current to the area where the high-performance module is located in time easily occurs, so that the voltage of the voltage domain drops instantaneously, the circuit time sequence in the high-performance module cannot be guaranteed, and the chip may enter an unpredictable out-of-control state, so that the work is abnormal. Many commercial high-performance processors currently select a circuit scheme of an adaptive clock to timely down-convert and guarantee internal timing of the high-performance module, for example, down-convert by a divide-by-two or multi-channel phase-locked loop (Phase Locked Loop, PLL), but the existing down-converting modes cannot down-convert the voltage drop in a targeted manner, and although the multi-channel PLL can realize multi-channel clock output, the implementation needs to sacrifice larger power consumption and area, and does not meet the current trend of large integration density.

In order to solve the above technical problems, the embodiment of the present specification proposes an improved down-conversion control scheme of an adaptive clock, which mainly includes: deploying a set of thresholds comprising a plurality of thresholds in the pressure drop monitoring module, each threshold corresponding to a threshold signal; when the voltage drop monitoring module monitors that the target processing unit has a voltage transient drop and the voltage drop generated in the effective monitoring period reaches at least one threshold value in the set threshold value set, the voltage drop monitoring module can trigger to generate one or more threshold value signals, so that different threshold value signals can be triggered according to different voltage drops. And then, the clock control module selects a threshold signal meeting the down-conversion constraint condition as a target threshold signal, and comprehensively determines a target down-conversion strategy matched with the current voltage transient drop event by using the target threshold signal and a performance signal acquired from a target processing unit. And then the clock signal is sent to a clock output module, and the clock output module selects the down-conversion clock signal conforming to the target down-conversion strategy from the down-conversion clock signal set sent by the clock generation module. And finally, outputting the power to the target processing unit for accurate frequency reduction so as to reduce or avoid the performance loss of the target processing unit caused by pressure drop.

The technical scheme of the present specification is described in detail below through specific examples.

Referring to fig. 1, a schematic circuit structure of a frequency control scheme based on an adaptive clock according to an embodiment of the present disclosure is shown.

The circuit is divided into two main components: an adaptive clock unit 102 and a target processing unit 104; the target processing unit 104 is a high performance module, such as a CPU, GPU, etc., which may have a voltage drop problem and needs to be subjected to the frequency down process; the adaptive clock unit 102 is a core circuit part of the scheme of the present specification, and provides a targeted accurate frequency-reducing strategy for different voltage drops through adaptive clock matching, so as to ensure the normal operation of the high-performance module. The adaptive clock unit 102 and the target processing unit 104 may be in the same voltage domain, and are powered by the power supply voltage DVDD.

In fig. 1, the adaptive clock unit 102 further includes: the voltage drop monitoring module 1022, the clock control module 1024, the clock generation module 1026 and the clock output module 1028. One end of the voltage drop monitoring module 1022 is in signal connection with the target processing unit 104, so as to monitor the voltage condition of the target processing unit 104. At the same time, the other end of the voltage drop monitoring module 1022 is in signal connection with the clock control module 1024 to transmit the triggered threshold signal to the clock control module 1024. Meanwhile, the clock control module 1024 is further connected to the target processing unit 104, so as to obtain the performance signal generated by the target processing unit 104. The clock control module 1024 is further coupled to the clock output module 1028 to send its determined target frequency down strategy to the clock output module 1028, facilitating the clock output module 1028 to match the corresponding down clock signal aclk_out.

In fact, the circuit also comprises: a phase-locked loop PLL is used to send the full-frequency clock signal required by the target processing unit 104 when no voltage drop occurs to the adaptive clock unit 102. The full frequency clock signal is directly connected to the clock output module 1028 via one pll_out and the other pll_out to the clock generation module 1026. When a voltage drop occurs and a threshold signal is triggered, the pll_out path of clock signal is turned off, and the path of clock generation module 1026 is turned on to perform the frequency down conversion process. Otherwise, when no voltage drop occurs or the voltage drop occurs but is insufficient to trigger the threshold signal, the pll_out clock signal is turned on and the clock generation module 1026 is turned off.

It should be appreciated that in order to coordinate with different voltage drops for targeted down-conversion processing, the range of voltage drops that may occur in the target processing unit 104 may be analyzed by test data of pre-silicon pre-slice simulation and post-silicon post-slice simulation, for example, may be reduced by 5% -18%, according to the voltage and/or frequency shift of the current target processing unit 104. Then the pressure drop range is divided into different pressure drop thresholds based on the pressure drop range. A plurality of pressure drop thresholds are configured in the pressure drop monitoring module 1022, and a threshold signal is allocated to each pressure drop threshold, and when a pressure drop is detected and reaches a certain threshold in a set of threshold values, the threshold reached by the pressure drop and the threshold signals of other threshold values smaller than the threshold are triggered. It should be noted that, the threshold signals corresponding to different voltage drop thresholds are different, alternatively, when a plurality of threshold signals are triggered, the threshold signals may be read in a one-hot one-bit valid code format under the condition that valid signals are identified as accurately as possible.

Meanwhile, according to the configuration of the threshold value in the voltage drop monitoring module 1022 and the distribution of the threshold value signal for each threshold value, correspondingly, a plurality of down-conversion clocks corresponding to different down-conversion amplitudes are deployed in advance in the clock generating module, and the down-conversion amplitude of each down-conversion clock is adjustable.

In the embodiment of the present disclosure, the clock control module 1024 may comprehensively consider determining the target frequency-reducing strategy for the voltage drop generated currently according to the determined target threshold signal and the performance signal obtained from the target processing unit 104, so as to avoid inaccuracy in determining the frequency-reducing strategy caused by separately considering the target threshold signal, and improve the control integrity and stability from multidimensional analysis. In fact, other configurable signals may be generated during actual circuit control, and may also be included as reference factors, i.e., the clock control module 1024 may determine a target frequency down-conversion strategy for the currently generated voltage drop based on the determined target threshold signal, the performance signal obtained from the target processing unit 104, and other configurable signals.

An alternative implementation may deploy a preset threshold signal and down-conversion policy mapping relationship in advance in the clock control module 1024. The mapping relation may be in the form of a lookup table, and is not limited in its concrete form. Each threshold signal corresponds to a down-conversion strategy, and each down-conversion strategy comprises at least a down-conversion amplitude, for example, the down-conversion amplitude is 10%. Depending on the performance signal, each of the downconversion strategies may in turn comprise a different downconversion sub-strategy. For example, each down-conversion strategy may further comprise: an unmodified first frequency-reducing sub-strategy, a second frequency-reducing sub-strategy based on forward modification of the first signal, and a third frequency-reducing sub-strategy based on reverse modification of the first signal. In addition, may further comprise: a fourth frequency-reducing sub-strategy based on forward correction of the second signal and a fifth frequency-reducing sub-strategy based on reverse correction of the second signal.

The first frequency-reducing sub-strategy may be a frequency-reducing amplitude determined according to a voltage drop of the trigger threshold signal, and the frequency-reducing amplitude determined in the first frequency-reducing sub-strategy is only related to the threshold signal, so that no correction is needed for the frequency-reducing amplitude.

The second frequency-reducing sub-strategy can be frequency-reducing amplitude of frequency-reducing correction determined based on the voltage drop of the trigger threshold signal, the frequency-reducing amplitude in the second frequency-reducing sub-strategy is related to the threshold signal and the first signal, so that on the basis of the frequency-reducing amplitude determined based on the threshold signal, the frequency-reducing amplitude determined by the threshold signal is positively corrected based on the frequency-reducing trend determined by the prediction logic by using the first signal, the frequency-reducing amplitude in the second frequency-reducing sub-strategy is smaller than the frequency-reducing amplitude in the first frequency-reducing sub-strategy, and the specific frequency-reducing frequency can be flexibly adjusted according to the designed prediction logic.

The third frequency-reducing sub-strategy can be frequency-reducing amplitude which is determined based on the voltage drop of the trigger threshold signal and is corrected by increasing the frequency-reducing amplitude, and the frequency-reducing amplitude in the third frequency-reducing sub-strategy is also related to the threshold signal and the first signal, so that on the basis of the frequency-reducing amplitude determined based on the threshold signal, the frequency-reducing amplitude determined by the first signal based on the frequency-reducing strategy determined by the prediction logic is used for carrying out reverse correction on the frequency-reducing amplitude determined by the threshold signal, and the frequency-reducing amplitude in the third frequency-reducing sub-strategy is larger than the frequency-reducing amplitude in the first frequency-reducing sub-strategy, and the frequency-reducing amplitude can be flexibly adjusted according to the designed prediction logic.

The fourth frequency-reducing sub-strategy can be frequency-reducing amplitude of frequency-reducing correction determined based on the voltage drop of the trigger threshold signal, the frequency-reducing amplitude in the fourth frequency-reducing sub-strategy is related to the threshold signal and the second signal, so that on the basis of the frequency-reducing amplitude determined based on the threshold signal, the frequency-reducing amplitude determined by the threshold signal is subjected to forward correction by using the frequency-reducing strategy preconfigured by the second signal through the control register, and the frequency-reducing amplitude in the fourth frequency-reducing sub-strategy is smaller than the frequency-reducing amplitude in the first frequency-reducing sub-strategy, and the specific frequency of the frequency-reducing amplitude can be flexibly adjusted according to the designed control register.

The fifth frequency-reducing sub-strategy can be frequency-reducing amplitude which is determined based on the voltage drop of the trigger threshold signal and is corrected by increasing the frequency-reducing amplitude, and the frequency-reducing amplitude in the fifth frequency-reducing sub-strategy is also related to the threshold signal and the second signal, so that on the basis of the frequency-reducing amplitude which is determined based on the threshold signal, the frequency-reducing amplitude which is determined by the threshold signal is reversely corrected by using the frequency-reducing strategy which is preconfigured by the second signal through the control register, and the frequency-reducing amplitude in the fifth frequency-reducing sub-strategy is larger than the frequency-reducing amplitude in the first frequency-reducing sub-strategy, and the specific magnitude can be flexibly adjusted according to the designed control register.

Thus, the target threshold signal and the performance signal may be comprehensively considered when determining the down-conversion strategy for triggering the voltage drop of the threshold signal; if the analysis performance signal is insufficient to induce pressure drop, a matched first frequency-reducing sub-strategy can be selected according to the target threshold signal, namely, the frequency-reducing processing is carried out by adopting uncorrected frequency-reducing amplitude; if analyzing the performance signal may induce a voltage drop, then in selecting a frequency-reducing sub-strategy that matches the target threshold signal, the effect of the size of the performance signal on the current voltage drop is also considered, and a forward-corrected frequency-reducing sub-strategy is selected, for example: a second frequency-reducing sub-strategy or a fourth frequency-reducing sub-strategy; or select a reverse modified down sub-strategy, such as: a third down-conversion sub-strategy or a fifth down-conversion sub-strategy.

It should be understood that, in the embodiment of the present disclosure, the design of the above frequency-reducing sub-strategy is only one possible embodiment, and is not limited to the implementation range of the scheme, and in particular, multiple experimental verification may be performed by using frequency-reducing requirements generated when different threshold signals and performance signals are comprehensively considered, so as to design different frequency-reducing sub-strategies to achieve more accurate matching.

Accordingly, in the clock generation module 1026, according to different frequency-reducing sub-strategies, frequency-reducing clocks with different frequency-reducing amplitudes are deployed respectively. For example, the clock generation module 1026 generates several frequencies from full frequency to half frequency, which may be implemented by delay locked loop DLL or digital gating. The present specification is not limited thereto. In fact, the frequency down range in the embodiments of the present disclosure may be anywhere between the full frequency to the lowest frequency, which may be a viable frequency greater than 0 and less than the full frequency.

Through the circuit structure shown in fig. 1, accurate frequency reduction of different voltage drops can be realized, and compared with the prior multipath frequency reduction scheme which can be adopted at present, the power consumption and the occupied area of the digital control logic added in the frequency reduction control scheme are smaller, and the response time for triggering frequency reduction is not changed.

A frequency control method based on an adaptive clock according to an embodiment of the present disclosure will be described in detail with reference to fig. 2. The frequency control method of the adaptive clock may include the steps of:

step 202: the voltage drop monitoring module monitors the voltage of the target processing unit, and triggers a threshold signal corresponding to each threshold value in at least one threshold value set when the voltage drop is monitored to be instantaneously dropped and the voltage drop generated in the effective monitoring period reaches the at least one threshold value in the set threshold value set.

Depending on the drop monitoring mechanism, the threshold signal may be metastable and require some more time to wait, and may be a few nanoseconds from the start of the drop to the lowest point, so an active monitoring period is provided here to ensure that the trigger threshold signal is a valid drop. The effective monitoring period can be manually deployed according to simulation or test results or calculated and automatically set by a processor.

In the embodiment of the present disclosure, if the voltage drop monitoring module detects that the voltage drops instantaneously and the voltage drop generated in the effective monitoring period reaches a minimum threshold value in the set threshold value set, triggering a threshold value signal corresponding to the minimum threshold value; and if the voltage drop monitoring module detects that the voltage drops instantaneously and the voltage drops generated in the effective monitoring period sequentially reach a plurality of thresholds in the set threshold set, sequentially triggering threshold signals corresponding to each threshold in the plurality of thresholds according to the sequence from small to large.

Referring to table 1, the number of thresholds in the pressure drop monitoring module may be flexibly configured according to requirements, and the number is defined as three for convenience of description. Threshold 1 is the minimum pressure drop threshold and threshold 3 is the maximum pressure drop threshold. The threshold itself may also be adjusted according to the current voltage and frequency range. For example, at high pressure and high frequency, the amplitude of the pressure drop is more likely to become large, so that the three thresholds can be set more widely, for example, 5%,10%,15%. If the amplitude of the voltage drop is not very large at low voltage and low frequency, the three thresholds can be set more closely, e.g. 5%,7%,10%. A typical digital implementation of pressure drop monitoring is: simulating the critical path, or selecting and copying the real critical path. Because of the digital implementation, the corresponding threshold number can be increased by copying the critical path under the condition of controllable power consumption area.

Optionally, a plurality of voltage drop thresholds may be adjusted in this specification according to the current voltage and/or frequency of the target processing circuit. The number of voltage drop thresholds in the voltage drop monitoring module may be increased by replicating the critical path.

Threshold 3	Threshold 2	Threshold 1	Description of the invention
				Without any means for	Without any means for	Without any means for	No pressure drop
Without any means for	Without any means for	Triggering	Triggering a minimum pressure drop threshold
				Without any means for	Triggering	X	Triggering a medium pressure drop threshold
Triggering	X	X	Triggering a maximum pressure drop threshold

TABLE 1

As can be seen from an analysis of table 1, when the pressure drop is detected to reach the threshold value 1, since the threshold value 1 is the minimum value, only the threshold signal corresponding to the threshold value 1 is triggered. When the voltage drop is detected to reach the threshold 2, the voltage drop reaches the threshold 1 at the same time, so that the threshold signal corresponding to the threshold 2 is triggered, meanwhile, the threshold signal corresponding to the threshold 1 can be triggered, the triggering process is sequential, the threshold signal corresponding to the threshold 1 is triggered first, and then the threshold signal corresponding to the threshold 1 is triggered while the threshold signal corresponding to the threshold 2 is kept. Similarly, when the detected voltage drop reaches the threshold 3, the threshold signal corresponding to the threshold 1, the threshold signal corresponding to the threshold 2 and the threshold signal corresponding to the threshold 3 are triggered in sequence.

It should be appreciated that in the present embodiments, the pressure drop monitoring module only monitors and triggers the threshold signal, and does not involve a determination of the target threshold signal, which is processed by the clock control module. In fact, the determining operation of the target threshold signal can also be transferred to the voltage drop monitoring module for execution, namely, the corresponding function of the clock control module is transferred to the voltage drop monitoring module for implementation. The present embodiments are not limited thereto, and the above are merely examples.

It should be noted that, although the threshold signal may be increasing, the clock control module turns off the original clock of the pll_out path as long as one path of the threshold signal is triggered. Moreover, the trigger signal and the threshold signal of the clock gating mechanism are the same, so the scheme does not influence the voltage drop processing response time of the adaptive clock.

Step 204: the clock control module receives at least one threshold signal, selects one threshold signal from the threshold signals as a target threshold signal based on a down-conversion constraint condition, and acquires a performance signal from the target processing unit; determining a target frequency-reducing strategy based on the performance signal and the target threshold signal, and sending the target frequency-reducing strategy to the clock output module; the performance signal is used for representing the current load change and/or load state of the target processing unit, and the target frequency-reducing strategy at least comprises frequency-reducing amplitude.

In the embodiment of the present disclosure, the down-conversion constraint condition may be selectively set according to a current scene requirement. For example, for a scenario requiring rapid frequency-down reaction, the clock control module may select, from the at least one threshold signal, a threshold signal corresponding to a threshold with a maximum value as the target threshold signal. For the scene requiring accurate and stable frequency reduction, the clock control module can select a threshold signal corresponding to the threshold with the maximum value of continuous stable triggering from the at least one threshold signal as a target threshold signal.

According to an implementation scheme, a clock control module can select a target frequency-reducing strategy matched with the target threshold signal from a preset mapping relation between the threshold signal and the frequency-reducing strategy based on an analysis result of the performance signal. Here, the performance signal may be used as an auxiliary reference to jointly determine the frequency-down amplitude, i.e. the target frequency-down strategy.

Wherein the performance signal may be a first signal that the high performance processing unit is ready to switch loads. The clock control module can analyze whether the load change will cause a voltage drop through simple prediction logic, and referring to fig. 3, if the prediction bias is caused, when the load switching signal is set high, the clock control can select to actively reduce the clock frequency for a few time lengths. It is understood here that a voltage drop may be induced when the first signal is set high; in fact, it may also be provided that a voltage drop is induced when the first signal is set low. The effect of the first signal on the downscaling amplitude may be detailed in a subsequent active downscaling control scheme.

The performance signal may also be a status signal of the high performance processing unit under a certain high load, i.e. a second signal, which may in fact also comprise a physical status signal under a high load state, such as a status signal reflected by a temperature state. If the second signal is set high, the clock control module may select a corresponding down-conversion strategy in a manner that the control register is configured in advance when the voltage drop is below the threshold but insufficient to trigger the target threshold signal. Conversely, if the second signal is set low and the target threshold signal is triggered, if the voltage drop is smaller, the disturbance on the power supply network is more likely, and the adaptive clock does not need to be greatly reduced in frequency; if the voltage drop is large, the load unknown to the high-performance processing unit or the work abnormality of the self-adaptive clock is more likely to be caused, and then the frequency is required to be reduced by a larger extent. Thus, the magnitude of the second signal and the voltage drop that triggers the generation of the target threshold signal determine the magnitude of the down-conversion in the target down-conversion strategy.

When the target frequency-reducing strategy is determined together with the threshold signal and the performance signal, the following two implementations can be classified according to the type of the performance signal:

Mode one: the mapping relation between the preset threshold signal and the frequency-reducing strategy comprises the following steps: the frequency-reducing strategy corresponding to each threshold signal at least comprises the following steps: an unmodified first frequency-reducing sub-strategy, a second frequency-reducing sub-strategy based on forward modification of the first signal, and a third frequency-reducing sub-strategy based on reverse modification of the first signal; the clock control module identifies that the performance signal is a first signal for preparing a switching load for the target processing unit, and judges whether the first signal can cause voltage drop or not based on prediction logic; if the first signal is judged to be capable of inducing pressure drop, selecting a second frequency-reduction sub-strategy or a third frequency-reduction sub-strategy corresponding to the threshold signal as a target frequency-reduction strategy based on the magnitude of the first signal from a preset mapping relation between the threshold signal and the frequency-reduction strategy; and if the first signal is judged to be insufficient to cause pressure drop, selecting a first frequency-reducing sub-strategy corresponding to the threshold signal from the mapping relation of the threshold signal and the frequency-reducing strategy as a target frequency-reducing strategy.

Mode two: the mapping relation between the preset threshold signal and the frequency-reducing strategy comprises the following steps: the frequency-reducing strategy corresponding to each threshold signal comprises the following steps: an unmodified first frequency-reducing sub-strategy, a fourth frequency-reducing sub-strategy based on forward modification of the second signal, and a fifth frequency-reducing sub-strategy based on reverse modification of the second signal; the clock control module identifies the performance signal as a second signal of the target processing unit under a specific load, and judges whether the second signal can cause voltage drop or not based on the magnitude of the second signal; if the second signal is judged to be capable of inducing the voltage drop, a fourth frequency-reduction sub-strategy or a fifth frequency-reduction sub-strategy corresponding to the threshold signal is selected as a target frequency-reduction strategy from a preset mapping relation between the threshold signal and the frequency-reduction strategy based on the magnitude of the second signal and the voltage drop of triggering to generate the target threshold signal; and if the second signal is judged to be insufficient to cause pressure drop, selecting a first frequency-reducing sub-strategy corresponding to the threshold signal from the mapping relation of the threshold signal and the frequency-reducing strategy as a target frequency-reducing strategy.

The above first and second modes are merely two examples of the present scheme, and the embodiment of the present specification is not limited as a necessary scheme. Besides the first mode and the second mode, a mapping relation between the threshold signal and the frequency-reducing strategy can be established in advance by using the threshold signal and the frequency-reducing strategy alone, wherein only one frequency-reducing strategy corresponding to the threshold signal in the mapping relation can exist, and a plurality of different sub frequency-reducing strategies do not exist; when the target frequency-reducing strategy is determined according to the threshold signal and the performance signal, the frequency-reducing strategy corresponding to the threshold signal can be selected from the mapping relation between the threshold signal and the frequency-reducing strategy according to the threshold signal, and then the frequency-reducing amplitude in the frequency-reducing strategy is subjected to forward correction or reverse correction or not correction based on the performance signal, so that the target frequency-reducing strategy is obtained. For example, according to the combination analysis of the threshold signal and the performance signal, the corresponding down-conversion amplitude under each combination condition is determined, and different down-conversion clocks are deployed in the clock generation module. Thus, when the threshold signal is transmitted, the clock control module can combine the threshold signal and the performance signal to determine the matched target frequency-reducing strategy.

Referring to fig. 4, taking a performance signal as a load state signal as an example, after triggering a threshold signal 1 corresponding to a threshold 1, selecting a default down-conversion strategy 1 if the load state signal is low, and selecting a down-conversion strategy 3 configured according to the load state signal if the load state signal is high; after triggering the threshold signal 2 corresponding to the threshold 2, if the load state signal is set low, selecting a default frequency-reducing strategy 2, and if the load state signal is set high, selecting a frequency-reducing strategy 4 configured according to the load state signal. Only two branches are taken as an example here, and there may be branches with a threshold value of 3 to a threshold value of N, which are not listed here one by one.

Therefore, in the embodiment of the present disclosure, the frequency-reducing amplitude in the target frequency-reducing strategy may be directly selected and matched based on a preset mapping relationship, or the frequency-reducing strategy may be determined based on the preset mapping relationship, and then the frequency-reducing amplitude in the frequency-reducing strategy is corrected according to the performance signal, so as to obtain the target frequency-reducing strategy. In a word, no matter what specific determination mode is adopted, a more accurate and proper target frequency-reducing strategy can be matched for the voltage drop generated currently according to the target threshold signal performance signal.

Step 206: and the clock output module selects a down-conversion clock signal corresponding to the target down-conversion strategy from the clock signal set generated by the clock generation module and outputs the down-conversion clock signal to the target processing unit.

As described above, the clock generation module is configured with a plurality of down-conversion clocks in advance and generates a plurality of down-conversion clock signals; after the clock output module receives the target frequency-reducing strategy, a corresponding frequency-reducing clock signal can be selected according to the frequency-reducing amplitude in the target frequency-reducing strategy and output to the target processing unit.

The frequency control scheme is a passive frequency-reducing operation implemented under the condition that voltage drop is generated, a target threshold signal is determined based on a frequency-reducing constraint condition from threshold signals triggered by the voltage drop, a target frequency-reducing strategy is determined based on the target threshold signal and a performance signal, and a corresponding frequency-reducing clock signal is selected from frequency-reducing clock signals generated by a clock generation module based on the frequency-reducing amplitude in the target frequency-reducing strategy and is input into a target processing unit for frequency-reducing processing. Therefore, different target frequency-reducing strategies are matched for different pressure drops based on the threshold signals and the performance signals, accurate and flexible frequency reduction is realized, and performance loss of the target processing unit caused by the pressure drops is reduced or avoided.

In addition to the above-described down-conversion processing in the passive mode, the embodiments of the present disclosure also provide an active down-conversion control scheme based on an adaptive clock. Upon voltage monitoring of a target processing unit based on step 202 of a passive down-conversion scheme, the clock control module obtains a performance signal from the target processing unit if the voltage drop monitoring module monitors that the voltage change of the target processing unit does not trigger any threshold signal. Based on the analysis result of the performance signal, selecting a target frequency-reducing strategy matched with the performance signal from a preset mapping relation between the performance signal and the frequency-reducing strategy, and sending the target frequency-reducing strategy to the clock output module; wherein the performance signal is used to characterize the current load change and/or load status of the target processing unit.

Optionally, if the clock control module determines that the performance signal can cause pressure drop according to the analysis result of the performance signal, selecting a frequency-reducing strategy matched with the value of the performance signal as a target frequency-reducing strategy from the preset mapping relation between the performance signal and the frequency-reducing strategy according to the size of the performance signal; if the clock control module determines that the performance signal is insufficient to induce a voltage drop, no processing is done.

When the clock control module selects a frequency-reducing strategy matched with the value of the performance signal from the preset mapping relation between the performance signal and the frequency-reducing strategy according to the size of the performance signal as a target frequency-reducing strategy, one specific implementation mode is as follows: and the clock control module selects the frequency-reducing amplitude matched with the signal pointer or the frequency-reducing amplitude and the frequency-reducing duration from the preset mapping relation of the performance signal and the frequency-reducing strategy according to the state pointer corresponding to the size of the performance signal, and the frequency-reducing amplitude and the frequency-reducing duration are used as target frequency-reducing strategies.

Referring to fig. 3, the performance signal is taken as a switching signal when the load changes, and if the switching signal is high to cause a voltage drop, different state pointers can be set according to different values of the switching signal, for example, the state pointer is 00, and the corresponding frequency-reducing strategy is: not actively reducing frequency; the state pointer is 01, and the corresponding down-conversion strategy is: small frequency reduction, wherein the frequency reduction duration is a; the state pointer is 10, and the corresponding down-conversion strategy is: small frequency reduction, wherein the frequency reduction duration is b; the state pointer is 11, and the corresponding down-conversion strategy is: and (3) greatly reducing the frequency, wherein the frequency reducing duration is c. It should be appreciated that this fig. 3 is presented by way of example only and is not limiting as to the scope of implementation of the scheme. Wherein the down-conversion amplitude and down-conversion duration can be determined from historical simulation and test data.

It is contemplated that in actual frequency control schemes, some voltage drops are not caused by load or frequency changes and these voltage drops are not stable in duration or magnitude. For example, voltage drop fluctuations caused by non-load and non-frequency variations may result from unreasonable threshold settings, or from very short failures or periodic fluctuations caused by other noise on the power network or chip.

If the voltage drop is fluctuating due to unreasonable threshold setting, the voltage drop monitoring module may trigger the threshold more easily, so that the clock output module outputs the down-conversion clock signal for a long time. Thus, for this case, the threshold setting rationality can be tested repeatedly at the beginning of the design to avoid such pressure drop fluctuations as much as possible.

If the voltage drop caused by the power network or other noise on the chip fluctuates, the duration and the occurrence frequency of the voltage drop cannot be long, and the voltage drop may disappear when the clock output module is ready to output the down-conversion clock signal. At this time, normal processing may be directly restored to the full frequency, but if the full frequency clock is restored, the full frequency clock must be re-synchronized, and obviously, the synchronization process during clock switching may reduce the output clock. Especially for the situations of unstable duration and occurrence frequency, the clocks may be switched repeatedly, and more output clocks are reduced. In order to cope with these special cases, after the clock output module outputs the down-converted clock signal to the target processing unit, when the voltage drop disappears, the down-converted clock signal is still output to the target processing unit, and the set duration is continued, so that the possibility of output clock reduction caused by clock switching is reduced. The set time length is determined according to the fluctuation frequency of the historical voltage drop, for example, according to whether the voltage drop threshold is repeatedly triggered in a short time after the clock control signal is restored to the full frequency.

It should be understood that in the embodiment of the present disclosure, the target frequency-reducing strategy may include only a frequency-reducing amplitude, and the frequency-reducing clock signal to be output is matched based on the frequency-reducing amplitude, and the output of the frequency-reducing clock signal may be stopped when the voltage drop disappears or when the threshold signal triggered by the voltage drop disappears. In the process of outputting the down-conversion clock signal, the voltage drop monitoring module also monitors the voltage drop change at all times so as to inform the clock control module to stop down-conversion output and restore to output the full-frequency clock signal when the voltage drop disappears or the threshold signal disappears.

In fact, the target frequency-reducing strategy may further include a frequency-reducing duration in addition to the frequency-reducing amplitude. Referring to fig. 5, the initial value of the down-conversion time period may be determined based on historical simulation or test data and continuously cyclically corrected in a subsequent frequency control scheme. For example, after a frequency-down strategy is initiated based on the target threshold signal, a frequency-down clock signal is output, and the output frequency-down time period is adjustable, and specifically, the adjustment can be performed with reference to the following rules: triggering a threshold signal in a short time, and increasing the time length of next output frequency reduction; the threshold signal is not triggered in a short time, and the next time of outputting the down-conversion time is unchanged. After the voltage drop disappears, the full frequency clock signal is recovered.

It should be noted that the set duration may be regarded as a down-conversion duration in the target down-conversion policy. Therefore, the determination scheme of the set time length can also be obtained by processing in the manner of referring to fig. 5.

In summary, embodiments of the present disclosure control the selection of the final output down-converted clock signal based on the threshold signal, the performance signal, and other configurable signals by the core module clock control module. The mode triggered by the frequency reduction can be divided into active protection and passive protection. Referring to fig. 6, during the process of outputting the full-frequency clock signal, whether the target processing unit generates a voltage drop or not is monitored in real time, and a threshold signal is triggered, if the threshold signal is triggered, a passive protection mode is selected to determine the target frequency-reducing strategy, otherwise, an active protection mode is selected to pre-determine that there may be a voltage drop in a short time, and then the target frequency-reducing strategy is actively determined. The active protection can increase the stability of a power supply network, the passive protection is the core of a self-adaptive clock frequency-reducing control scheme, the accurate frequency reduction of different voltage drops can be realized, and the performance loss of a target processing unit caused by the voltage drops is reduced or avoided.

It should be understood that the down-conversion amplitude and down-conversion duration in the target down-conversion strategy are mainly implemented through configuration in the active protection mode, for example, predicting a mapping relationship of state pointers or configuration in logic. In the passive protection mode, the specific implementation manner may be described with reference to the relevant contexts of the first and second modes, which are not described herein.

Embodiments of the present specification also provide a system on a chip, including: a target processing unit that performs a high-performance processing operation; the frequency control circuit of the adaptive clock according to the above embodiment is connected with the target processing unit in a signal manner, monitors the voltage drop of the target processing unit, and feeds back the adaptively adjusted clock signal to the target processing unit.

Meanwhile, the embodiment of the specification also provides a chip, which comprises: the system-on-chip in the above embodiment; an off-chip bus; and the memory and the power management circuit are connected with the system on chip through an off-chip bus.

With the rise of the artificial intelligence internet of things AIoT, the RISC-V instruction set architecture is receiving more and more attention and support due to its unique openness and flexibility, and is expected to become a CPU architecture for the next generation of wide application. The architecture can be adopted to design corresponding CPUs which cover various application scenes from low power consumption to high performance. When the designed chip focuses on performance, the down-conversion control system using the adaptive clock in the embodiment of the specification can enable the CPU to work at higher voltage in an over-frequency mode. When more attention is paid to power consumption, the down-conversion control system using the adaptive clock can effectively reduce the extra reserved voltage, thereby reducing the power consumption of the CPU.

For example, to reduce power consumption, we might have the CPU at a low frequency and low voltage gear under low load, but due to the complexity of the process, it is often impossible to fully verify that all the voltage-frequency combinations are converged before streaming, so to ensure that the CPU can be at that frequency, more margin is added to the voltage. If the adaptive clock frequency-reducing control scheme in the embodiment of the specification is matched, even if the margin is not added, the normal operation of the CPU can be ensured through frequency reduction.

For another example, if we want to push the limit performance of the chip, such as trying to run the chip at 2.5GHz at 1.1V, this is not guaranteed before the chip is streamed, only part of the chip can run, and a sieve is needed. However, if a down control scheme for the adaptive clock is used, more chips can be used, since although some CPUs are still not able to run to 2.5GHz in all cases, if due to transient voltage drops, the adaptive clock can be used to solve so that the CPU can try higher frequencies.

Thus, the adaptive clock frequency-reducing control scheme can realize low power consumption and high frequency try of the CPU on the chip.

FIG. 7 illustrates a general computer architecture to which embodiments of the present description may be applied. As shown in fig. 7, a computer system 700 may include one or more processors 702, and memory 704. In some embodiments, the frequency control circuit of the adaptive clock described above may be used in the computer architecture to provide the clock signal, in other embodiments, a system-on-chip may be used directly as the processor 702 in this embodiment. The memory 704 in the computer system 700 may be a main memory (referred to as main memory or internal memory for short). For storing instruction information and/or data information represented by data signals, such as data provided by the processor 702 (e.g., as a result of an operation), may also be used to effect data exchange between the processor 702 and the external storage device 706 (otherwise known as secondary or external memory). In some cases, the processor 702 may need to access the memory 704 to obtain data in the memory 704 or to modify data in the memory 704. Based on this, the processor 702 may include an instruction execution unit 7022, a memory management unit 7024, and the like. In addition, computer system 700 may also include input/output devices such as a memory display device 708, an audio device 710, a mouse/keyboard 712, and the like. A display device 708 is coupled to the bus, for example via a corresponding graphics card, for displaying according to a display signal provided by the bus. Computer system 700 also typically includes a communication device 714, and thus can communicate with a network or other device in a variety of ways. Different computer systems may also vary in architecture depending on the motherboard, operating system, and instruction set architecture. For example, many computer systems are currently provided with an input/output control center connected between the bus and the various input/output devices, and the input/output control center may be integrated within the processor 702 or independent of the processor 702.

In some embodiments, the adaptive clock-based frequency control circuit described above may be used in the present embedded system to provide a clock signal, and in other embodiments, the system-on-chip may be used directly as the processor in the present embodiment. With the rapid development of ultra-large-scale integrated circuits (VERY LARGE SCALE Integration) and semiconductor processes, part or all of the above-mentioned embedded systems can be implemented on a single silicon wafer, i.e., the embedded system-on-chip.

It should be appreciated that the frequency control circuit of the adaptive clock referred to in the embodiments of the present specification may be applied to any electronic device including a system on a chip, a chip. The electronic device may be, for example, a cloud server with a huge number of data centers, and may also be various electronic devices used in daily life.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.

Claims

1. The frequency control method based on the adaptive clock is applied to the adaptive clock control circuit, and the adaptive clock control circuit comprises the following steps: the device comprises a voltage drop monitoring module, a clock control module, a clock generation module and a clock output module; the frequency control method comprises the following steps:

The clock control module receives at least one threshold signal, selects one threshold signal from the threshold signals as a target threshold signal based on a down-conversion constraint condition, and acquires a performance signal from the target processing unit; based on the analysis result of the performance signal, selecting a target frequency-reducing strategy matched with the target threshold signal from a preset mapping relation between the threshold signal and the frequency-reducing strategy, and sending the target frequency-reducing strategy to the clock output module; the performance signal is used for representing the current load change and/or load state of the target processing unit, the target frequency-reducing strategy at least comprises frequency-reducing amplitude, each threshold signal corresponds to one frequency-reducing strategy, and each frequency-reducing strategy at least comprises frequency-reducing amplitude;

The clock output module selects a down-conversion clock signal corresponding to the target down-conversion strategy from the clock signal set generated by the clock generation module and outputs the down-conversion clock signal to the target processing unit, and the clock signal set comprises a plurality of down-conversion clock signals with different down-conversion amplitudes.

2. The adaptive clock-based frequency control method of claim 1, wherein the voltage drop monitoring module triggers a threshold signal corresponding to each of at least one threshold when a voltage drop is detected that is instantaneously dropped and a voltage drop generated during an active monitoring period reaches at least one threshold of a set of thresholds, comprising:

If the voltage drop monitoring module detects that the voltage drops instantaneously and the voltage drop generated in the effective monitoring period reaches the minimum threshold value in the set threshold value set, triggering a threshold value signal corresponding to the minimum threshold value;

and if the voltage drop monitoring module detects that the voltage drops instantaneously and the voltage drops generated in the effective monitoring period sequentially reach a plurality of thresholds in the set threshold set, sequentially triggering threshold signals corresponding to each threshold in the plurality of thresholds according to the sequence from small to large.

3. The adaptive clock-based frequency control method of claim 2, wherein the clock control module selects one of the threshold signals as the target threshold signal based on a down-conversion constraint condition, comprising:

the clock control module selects a threshold signal corresponding to a threshold with the largest value from the at least one threshold signal as a target threshold signal;

Or alternatively

And the clock control module selects a threshold signal corresponding to a threshold with the maximum value of continuous stable triggering from the at least one threshold signal as a target threshold signal.

4. The frequency control method based on an adaptive clock as claimed in claim 1, wherein the preset mapping relationship between the threshold signal and the frequency-down strategy is as follows: the frequency-reducing strategy corresponding to each threshold signal at least comprises the following steps: an unmodified first frequency-reducing sub-strategy, a second frequency-reducing sub-strategy based on forward modification of the first signal, and a third frequency-reducing sub-strategy based on reverse modification of the first signal;

The clock control module selects a target frequency-reducing strategy matched with the target threshold signal from a preset mapping relation between the threshold signal and the frequency-reducing strategy based on the analysis result of the performance signal, and the clock control module comprises the following steps:

the clock control module identifies that the performance signal is a first signal for preparing a switching load for the target processing unit, and judges whether the first signal can cause voltage drop or not based on prediction logic;

If the first signal is judged to be capable of inducing pressure drop, selecting a second frequency-reduction sub-strategy or a third frequency-reduction sub-strategy corresponding to the threshold signal as a target frequency-reduction strategy based on the magnitude of the first signal from a preset mapping relation between the threshold signal and the frequency-reduction strategy;

And if the first signal is judged to be insufficient to cause pressure drop, selecting a first frequency-reducing sub-strategy corresponding to the threshold signal from the mapping relation of the threshold signal and the frequency-reducing strategy as a target frequency-reducing strategy.

5. The frequency control method based on an adaptive clock as claimed in claim 1, wherein the preset mapping relationship between the threshold signal and the frequency-down strategy is as follows: the frequency-reducing strategy corresponding to each threshold signal further comprises: a fourth frequency-reducing sub-strategy based on forward correction of the second signal and a fifth frequency-reducing sub-strategy based on reverse correction of the second signal;

the clock control module identifies the performance signal as a second signal of the target processing unit under a specific load, and judges whether the second signal can cause voltage drop or not based on the magnitude of the second signal;

if the second signal is judged to be capable of inducing the voltage drop, a fourth frequency-reduction sub-strategy or a fifth frequency-reduction sub-strategy corresponding to the threshold signal is selected as a target frequency-reduction strategy from a preset mapping relation between the threshold signal and the frequency-reduction strategy based on the magnitude of the second signal and the voltage drop of triggering to generate the target threshold signal;

And if the second signal is judged to be insufficient to cause pressure drop, selecting a first frequency-reducing sub-strategy corresponding to the threshold signal from the mapping relation of the threshold signal and the frequency-reducing strategy as a target frequency-reducing strategy.

6. The adaptive clock-based frequency control method of claim 1, further comprising, if the voltage drop monitoring module monitors that a voltage change of a target processing unit does not trigger any threshold signal:

The clock control module acquires a performance signal from the target processing unit; based on the analysis result of the performance signal, selecting a target frequency-reducing strategy matched with the performance signal from a preset mapping relation between the performance signal and the frequency-reducing strategy, and sending the target frequency-reducing strategy to the clock output module; wherein the performance signal is used to characterize the current load change and/or load status of the target processing unit.

7. The adaptive clock-based frequency control method according to claim 6, wherein the clock control module selects a target frequency-down strategy matched with the performance signal from a preset mapping relationship between the performance signal and the frequency-down strategy based on an analysis result of the performance signal, and the method comprises:

if the performance signal is determined to be capable of inducing pressure drop according to the analysis result of the performance signal, selecting a frequency-reducing strategy matched with the value of the performance signal from the preset mapping relation between the performance signal and the frequency-reducing strategy according to the size of the performance signal as a target frequency-reducing strategy;

if the performance signal is insufficient to induce a pressure drop, no treatment is done.

8. The adaptive clock-based frequency control method as claimed in claim 7, wherein the clock control module selects a down-conversion strategy matched with the value of the performance signal as the target down-conversion strategy from the preset mapping relationship between the performance signal and the down-conversion strategy according to the size of the performance signal, and the method comprises the following steps:

And the clock control module selects the frequency-reducing amplitude matched with the signal pointer or the frequency-reducing amplitude and the frequency-reducing duration from the preset mapping relation of the performance signal and the frequency-reducing strategy according to the signal pointer corresponding to the size of the performance signal.

9. The method for controlling a frequency based on an adaptive clock according to claim 1 to 3 or 6 to 8,

If the current or expected generated pressure drop is determined to be the fluctuating pressure drop caused by non-load or non-frequency change in the target processing unit according to the analysis result of the performance signal; then after the clock output module outputs the down-converted clock signal to the target processing unit, the method further comprises:

when the voltage drop disappears, the clock output module still outputs the down-conversion clock signal to the target processing unit, and the time duration is set continuously; the set time length is determined according to the fluctuation frequency of the historical pressure drop.

10. A frequency control circuit based on an adaptive clock, comprising: the device comprises a voltage drop monitoring module, a clock control module, a clock output module and a clock generation module; a plurality of pressure drop thresholds are preset in the pressure drop monitoring module, and each pressure drop threshold corresponds to a threshold signal;

The clock control module is used for selecting one threshold signal from at least one threshold signal based on a frequency-reducing constraint condition as a target threshold signal and acquiring a performance signal from the target processing unit; selecting a target frequency-reducing strategy matched with the target threshold signal from a preset mapping relation between the threshold signal and the frequency-reducing strategy based on an analysis result of the performance signal; the performance signal is used for representing the current load change and/or load state of the target processing unit, the target frequency-reducing strategy at least comprises frequency-reducing amplitude, each threshold signal corresponds to one frequency-reducing strategy, and each frequency-reducing strategy at least comprises frequency-reducing amplitude;

11. The frequency control circuit of an adaptive clock of claim 10, the clock control module further to obtain a performance signal from a target processing unit if the voltage drop monitoring module monitors that a voltage change of the target processing unit does not trigger any threshold signal; based on the analysis result of the performance signal, selecting a target frequency-reducing strategy matched with the performance signal from a preset mapping relation between the performance signal and the frequency-reducing strategy, and sending the target frequency-reducing strategy to the clock output module; wherein the performance signal is used to characterize the current load change and/or load status of the target processing unit.

12. A system on a chip, comprising:

A target processing unit that performs a high-performance processing operation;

And the frequency control circuit of the adaptive clock of any one of claims 10 or 11, in signal connection with the target processing unit, monitoring the voltage drop of the target processing unit, and feeding back an adaptively adjusted clock signal to the target processing unit.

13. A chip, comprising:

the system-on-chip of claim 12;

an off-chip bus;

And the memory and the power management circuit are connected with the system on chip through the off-chip bus.