DE102012112363A1 - Method for controlling power of chip system of multi-core system, involves comparing time interval between receipt of former and latter wake-up request signals and controlling output of wake-up request signal based on the comparison - Google Patents

Abstract

The method involves controlling (S160) an output of a wake-up request signal and another wake-up request signal in such a way that a time interval between the outputs of the wake-up request signals is same or larger than a time interval threshold value. The time interval between the receipt of the former and latter wake-up request signals is compared with the time interval threshold value. The output of one among wake-up request signals is controlled based on the comparison between the time interval and the time interval threshold value. Independent claims are included for the following: (1) a chip system for use with a wake up-request signal distribution circuit; and (2) a multi-core system for use with multiple wake up-sources.

Description

CROSS REFERENCE TO RELATED APPLICATION (S)

This application claims under 35 USC § 119 the Priority of Korean Patent Application No. 10-2012-0008822 filed on Jan. 30, 2012 with the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety.

BACKGROUND

Technical area

Exemplary embodiments relate generally to, for example, multiprocessor and / or multi-core systems, methods for distributing a plurality of interrupts, interrupt request signal propagation circuits, and system-on-chip (SOC) systems. which have the same.

Description of the Prior Art

A conventional electrical device has an interrupt controller for interrupt handling operations. When a plurality of interrupt sources generate a plurality of interrupts, the interrupt controller may prioritize the interrupts and provide interrupt request signals to processors. The interrupt request signals are generated based on the interrupts.

Recently, a system-on-chip (SOC) system has been more widely used in electrical devices because the electrical devices have become smaller and lighter. Here, SOCs may include a plurality of intellectual property (IP) blocks or IP blocks and a plurality of processors (or a processor having a plurality of cores).

In an SOC, processors often enter a low-power mode to reduce power consumption. The processors wake up from the low power mode in response to the receipt of respective interrupt request signals. As described above, interrupt request signals are generated based on the interrupts generated by a plurality of interrupt sources. However, if the processors wake up substantially from the low power state at the same or substantially the same time (eg, sometimes referred to as a sudden wake up), then inrush currents in the processors may result.

SHORT VERSION

One or more exemplary embodiments provide methods for propagating a plurality of interrupt request signals that are capable of suppressing and / or preventing modes of a plurality of processors (or a plurality of cores in a multi-core processor or multi-core processor) continuously from an inactive state (for example a power-down state, a power-off state, etc.) into an active state (for example, a switch-on state ( power-on-state), etc.) are changed within a relatively small amount of time, even if a plurality of interrupts are continuously generated by a plurality of interrupt sources within a relatively small amount of time.

One or more exemplary embodiments provide interrupt request signal distribution circuits that are capable of suppressing and / or preventing modes of a plurality of processors (or a plurality of cores in a multi-core processor) from continuously occurring inactive state (for example, a power-down state, a power-off state, etc.) into an active state (eg, a power-on state, etc.) within one even if a plurality of interrupts are continuously generated by a plurality of interrupt sources within a relatively short period of time.

Exemplary embodiments also provide system-on-chips having interrupt request signal propagation circuits.

By controlling time intervals between the issuance of interrupt request signals (eg, time intervals between the issuance of adjacent interrupt request signals) to be greater than or equal to a time interval limit, the interrupt request signals being based on a plurality of interrupts In accordance with exemplary embodiments, methods for distributing a plurality of interrupt request signals may suppress and / or prevent modes of a plurality of processors (or a plurality of cores in a multi-core processor) from being continuously inactive (e.g. Abschaltvorgangs- Also, power-down state, power-off state, etc.) are changed to an active state (eg, a power-on state, etc.) within a relatively small period of time when a plurality of interrupts are continuously generated by a plurality of interrupt sources within a relatively small amount of time. As a result, inrush currents in the processors can be suppressed and / or prevented.

Additionally, by controlling time intervals between a plurality of interrupt request signals (eg, time intervals between the output of adjacent interrupt request signals) to be greater than or equal to a time interval limit value, the interrupt request signals may be based on a plurality of interrupts may suppress an interrupt request signal propagation circuit according to one or more example embodiments and / or prevent modes of a plurality of processors (or a plurality of cores in a multi-core processor) from being continuously inactive (e.g., a power down operation) Power-down state, a power-off state, etc.) are changed to an active state (for example, a power-on state, etc.) within a relatively small period of time, even if a plurality of interrupts are continuous is generated by a plurality of interrupt sources within a relatively short period of time. As a result, inrush currents in the processors can be suppressed and / or prevented.

One-chip systems according to example embodiments may include an interrupt request signal propagation circuit. Thus, single-chip systems can achieve relatively high operational reliability by suppressing and / or preventing modes of a plurality of processors (or a plurality of cores in a multi-core processor) from being continuously inactive (e.g., shutdown). State (power-down state), a power-off state, etc.) are changed to an active state (for example, a power-on state, etc.) within a relatively small period of time.

At least one exemplary embodiment provides a method of power control for a single-chip system. In accordance with at least this exemplary embodiment, the method comprises: controlling a delivery of at least one of a first wakeup request signal and a second wakeup request signal such that a time interval between the output of the first wakeup request signal and the first wakeup request signal Output of the second wake-up request signal is greater than or equal to a time interval limit, wherein the first wake-up request signal and the second wake-up request signal are one of simultaneous and consecutive wake-up request signals.

At least one other exemplary embodiment provides a method of power control for a single-chip system. In accordance with at least this example embodiment, the method comprises: comparing a first priority of a first wakeup request signal with a second priority of a second wakeup request signal; and controlling an output of at least one of the first wakeup request signal and the second wakeup request signal based on the comparison between the first priority and the second priority such that a time difference between the output of the first wakeup request signal and the output of the first wakeup request signal second wakeup request signal is greater than or equal to a time interval limit.

At least one other exemplary embodiment provides a method of power control for a single-chip system. In accordance with at least this example embodiment, the method comprises: controlling an output of at least one of a first wakeup request signal to a first processor in an inactive state and a second wakeup request signal to a second processor in the inactive state such that a time interval between the output of the first wakeup request signal to the first processor and the output of the second wakeup request signal to the second processor is greater than or equal to a time interval limit, wherein the first wakeup request signal and the second wakeup request signal are one of simultaneous and consecutive wake-up request signals.

At least one other exemplary embodiment provides a method of power control for a single-chip system. In accordance with at least this exemplary embodiment, the method comprises: comparing a first priority of a first wakeup request signal with a second priority of a second wakeup request signal, each of the first wakeup request signal Request signal and the second wake-up request signal is connected to a functional block in an inactive state; and controlling an output of at least one of the first wakeup request signal and the second wakeup request signal based on the comparison between the first priority and the second priority such that a time difference between the output of the first wakeup request signal and an output of the first wakeup request signal second wakeup request signal is greater than or equal to a time interval limit.

At least one other exemplary embodiment provides a single chip system, comprising: a wakeup request signal propagation circuit configured to provide an output of at least one of a first wakeup request signal to a first functional block and a second wakeup request signal a second function block such that a time interval between the output of the first wakeup request signal to the first function block and the output of the second wakeup request signal to the second function block is greater than or equal to a time interval limit value, wherein the first Wakeup request signal and the second wakeup request signal are one of simultaneous and consecutive wakeup request signals.

At least one other exemplary embodiment provides a one-chip system comprising: a wakeup request signal propagation circuit configured to compare a first priority of a first wakeup request signal with a second priority of a second wakeup request signal; wherein the wakeup request signal propagation circuit is further configured to control an output of at least one of the first wakeup request signal and the second wakeup request signal based on the comparison between the first priority and the second priority such that a time difference between the output of the first wakeup request signal and an output of the second wakeup request signal is greater than or equal to a time interval limit value.

At least one other exemplary embodiment provides a single chip system comprising: a wakeup request signal propagation circuit configured to output at least one of a first wakeup request signal to a first functional block in an inactive state and a second one Wakeup request signal to a second functional block in an inactive state such that a time interval between the output of the first wakeup request signal and the output of the second wakeup request signal is greater than or equal to a time interval limit value, the first one Wakeup request signal and the second wakeup request signal are one of simultaneous and consecutive wakeup request signals.

At least one other exemplary embodiment provides a one-chip system comprising: a wakeup request signal propagation circuit configured to compare a first priority of a first wakeup request signal with a second priority of a second wakeup request signal; wherein each of the first wakeup request signal and the second wakeup request signal is connected to a functional block in an inactive state, wherein the wakeup request signal propagation circuit is further configured to output at least one of the first wakeup request signal and the second wakeup request signal based on the comparison between the first priority and the second priority, to control such that a time difference between the output of the first wakeup request signal and an output of the second wakeup request signal is greater than or equal to a time interval limit.

At least one other exemplary embodiment provides a one-chip system comprising: a plurality of wake-up request signal sources configured to generate at least first and second wake-up signals; a wakeup signal controller configured to generate at least a first and a second wakeup request signal based on the first and second wakeup signals; a plurality of processors configured to transition from an inactive state to an active state based on the first and second wakeup request signals; and a wakeup request signal propagation circuit configured to control an output of at least one of the first wakeup request signal to a first one of the plurality of processors and the second wakeup request signal to a second one of the plurality of processors, in that a time interval between the output of the first wakeup request signal and the output of the second wakeup request signal is greater than or equal to a time interval limit, wherein the first wakeup request signal and the second wakeup request signal are one of simultaneous and consecutive wakeup request signals.

At least one other exemplary embodiment provides a multi-core system comprising: a plurality of wake-up signal sources configured to be at least first and second generate second wake-up signal; a wakeup signal controller configured to generate at least first and second wakeup request signals based on the first and second wakeup signals; a multi-core processor having at least a first and a second core, wherein the first core is configured to receive the first wakeup request signal, and the second core is configured to receive the second wakeup Receive request signal; a wakeup request signal propagation circuit configured to control an output of at least one of the first wakeup request signal to the first core and the second wakeup request signal to the second core such that a time interval between the output of the second core first wake-up request signal and the output of the second wake-up request signal is greater than or equal to a time interval limit, the first wake-up request signal and the second wake-up request signal being one of simultaneous and consecutive wake-up request signals; and at least one memory device configured to couple with the plurality of wake-up signal sources and the multi-core processor via a system bus.

BRIEF DESCRIPTION OF THE DRAWINGS

Illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

1 FIG. 10 is a block diagram illustrating a system-on-chip system according to an example embodiment. FIG.

2 FIG. 10 is a flowchart illustrating a method of propagating a plurality of interrupt request signals according to an example embodiment.

The 3A and 3B 10 are diagrams illustrating an example in which a plurality of interrupt request signals are executed according to the method of FIG 2 is disseminated.

The 4A and 4B FIG. 15 are diagrams illustrating another example in which a plurality of interrupt request signals are executed according to the method of FIG 2 is disseminated.

The 5A and 5B 15 are diagrams illustrating still another example in which a plurality of interrupt request signals are executed according to the method of FIG 2 is disseminated.

6 FIG. 10 is a flow chart illustrating a method of propagating a plurality of interrupt request signals, according to another example embodiment.

The 7A and 7B 10 are diagrams illustrating an example in which a plurality of interrupt request signals are executed according to the method of FIG 6 is disseminated.

8th FIG. 10 is a flow chart illustrating a method of propagating a plurality of interrupt request signals, according to another example embodiment.

The 9A and 9B 10 are diagrams illustrating an example in which a plurality of interrupt request signals are executed according to the method of FIG 8th is disseminated.

10 FIG. 10 is a flow chart illustrating a method of propagating a plurality of interrupt request signals, according to another example embodiment.

11 FIG. 13 is a diagram illustrating a plurality of processors in an active state and a plurality of processors in an inactive state. FIG.

12 FIG. 10 is a block diagram illustrating an interrupt request signal propagation circuit according to an example embodiment. FIG.

13 FIG. 12 is a diagram illustrating a state machine implementation of the interrupt request signal holder, which is shown in FIG 12 is illustrated.

14 FIG. 15 is a diagram illustrating a state machine implementation of the interrupt request signal arbiter which is shown in FIG 12 shown is illustrated.

15 FIG. 13 is a timing chart showing an exemplary operation of the interrupt request signal propagating circuit of FIG 12 illustrates

16 FIG. 10 is a block diagram illustrating an interrupt request signal propagation circuit according to another exemplary embodiment.

17 FIG. 15 is a diagram illustrating an exemplary operation of the interrupt request signal propagation circuit incorporated in FIG 1 shown is illustrated.

18 FIG. 15 is a diagram illustrating another exemplary operation of the interrupt request signal propagation circuit incorporated in FIG 1 shown is illustrated.

19 FIG. 15 is a diagram showing still another exemplary operation of the interrupt request signal propagation circuit incorporated in FIG 1 shown is illustrated.

20 FIG. 10 is a block diagram illustrating a multi-core system according to an example embodiment. FIG.

21 FIG. 15 is a diagram illustrating an example in which a multi-core system of FIG 20 implemented as a smartphone.

DETAILED DESCRIPTION

Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. However, inventive concepts may be embodied in many different forms and should not be considered as limited to the exemplary embodiments described herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that although the first / first / first, second / second / second, third / third / third etc. words may be used herein to describe various elements, these elements should not be limited by these terms. These words are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the inventive concept. As used herein, the wording "and / or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a like manner (eg, "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

The terminology used herein is merely for describing particular example embodiments and is not intended to be limiting of inventive concepts. As used herein, the singular forms "one" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will further be understood that the words "pointing to" and / or "having" when used in this specification, do not, however, specify the presence of said features, integers, steps, operations, elements, and / or components exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

Unless defined otherwise, all wording (including technical and scientific terms) used herein has the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. It will further be understood that words, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the particular field and not being interpreted in an idealized or overly formal sense Unless expressly defined herein.

1 FIG. 10 is a block diagram illustrating a system-on-chip system according to an example embodiment. FIG.

Referring to 1 has the one-chip system 500 a first bis (n) -th interrupt source 520_1 to 520_n , an interrupt controller 540 , an interrupt request signal propagation circuit 560 and a first to a (m) th processor 580_1 to 580_m on. As discussed herein, the interrupt request signal propagation circuit may be referred to 560 as a growth Request signal propagation circuit and / or interrupt request signal propagation circuit are referred. An interrupt request signal may be referred to as a wakeup request signal. Similarly, on the interrupt controller 540 Reference may be made to a wake-up signal controller and an interrupt may be referred to as a wake-up signal.

In at least some example embodiments, the number of interrupt sources 520_1 to 520_n greater than the number of processors 580_1 to 580_m , However, in other example embodiments, the number of interrupt sources 520_1 to 520_n less than or equal to the number of processors 580_1 to 580_m , In addition, the first to (m) -th process 580_1 to 580_m separate processors or a plurality of cores of a multi-processor or multiple processor correspond. In one example, the multi-processor may be referred to as a dual-core processor if m is 2, it may be referred to as a quad-core processor if m is 4, etc.

The first to the (n) th interrupt source 520_1 to 520_n each generate a first to a (n) th interrupt INT_R1 to INT_Rn. In this example, the first to nth interrupt source is 520_1 to 520_n Intellectual property blocks (IP blocks) that perform certain operations in the multi-processor (or multi-core) system. The first to the (n) th interrupt source 520_1 to 520_n may correspond to components of a system-on-chip (SOC) system such as a video module, a sound module, a display module, a memory module, a communication module, a camera module, etc.

Still referring to 1 generates the interrupt controller 540 each a first to (m) -th interrupt request signal nIRQ_I1 to nIRQ_Im based on the first to (n) -th interrupt INT_R1 to INT_Rn from the first to the (n) -th interrupt source 520_1 to 520_n ,

The interrupt request signal propagation circuit 560 outputs first through m (m) -th interrupt request signals nIRQ_O1 to nIRQ_Om to the first to (m) th processors, respectively 580_1 to 580_m based on the first to (m) -th interrupt request signal nIRQ_I1 to nIRQ_Im and at time intervals which are greater than or equal to a time interval threshold. According to at least some example embodiments, the time interval threshold may be a given, a desired, or a predetermined time interval determined according to empirical data or selected by a user or design engineer. In at least one example embodiment, the time interval threshold may be a time interval in a range in which the inrush currents in the processors are not generated when modes of the processors are changed from an inactive state to an active state (eg, continuously changed).

Still referring to 1 lead the first to (m) -th processor 580_1 to 580_m Interrupt handling operations for the first to (n) th interrupt source 520_1 to 520_n respectively in response to the first to (m) -th interrupt request signal nIRQ_O1 to nIRQ_Om.

As mentioned above, the interrupt controller generates 540 the first to (m) -th interrupt request signal nIRQ_I1 to nIRQ_Im based on the first to nth interrupt TNT_R1 to TNT_Rn, which are triggered by the first to n-th interrupt source 520_1 to 520_n be generated. In at least one example embodiment, the interrupt controller receives 540 the first to nth interrupt TNT_R1 to TNT_Rn from the first to the (n) th interrupt source 520_1 to 520_n and assigns the first through nth interrupt TNT_R1 to TNT_Rn to the first to (m) th processors 580_1 to 580_m to. If the number of the first to (m) -th processor 580_1 to 580_m is less than the number of the first to the (n) th interrupt source 520_1 to 520_m , then the interrupt controller 540 the first to nth interrupt TNT_R1 to TNT_Rn to the first to (m) th processor 580_1 to 580_m by assigning the first to (n) th interrupts temporally and / or spatially to TNT_R1 to TNT_Rn.

The interrupt request signal propagation circuit 560 controls the time intervals between the output of the first to (m) -th interrupt request signal nIRQ_I1 to nIRQ_Im (for example, a time interval between the output of adjacent interrupt request signals) transmitted from the interrupt controller 540 be supplied so that it is greater than or equal to the time interval limit. In one example, the time interval threshold may be within a range in which inrush surges in the first to (m) th processors 580_1 to 580_m are not generated when modes of the first to (m) -th processor 580_1 to 580_m be changed from an inactive state to an active state (for example, to be changed continuously).

As more detailed below with respect to 12 will be discussed, in at least one example embodiment, the interrupt request signal propagation circuit 560 a first to (m) -th interrupt request signal holder and an interrupt request signal arbiter. In this example, the first to m-th interrupt request signal holders receive the first to m-th interrupt request signals nIRQ_I1 to nIRQ_Im, and give the first to the m-th interrupt request signals nIRQ_O1 to nIRQ_Om to the first to the (m) -th processor 580_1 to 580_m at time intervals which are greater than or equal to the time interval limit.

If necessary, the interrupt request signal arbiter controls the time interval between the output of each of the first through (m) th interrupt request signals nIRQ_I1 to nIRQ_Im to be greater than or equal to the time interval threshold. For example, if a time interval between adjacent ones of the first to (m) th interrupt request signal nIRQ_I1 to nIRQ_Im is smaller than the time interval threshold, then the interrupt request signal arbiter controls the time interval between the output of the adjacent interrupt request signals such that the time interval is greater than or equal to the time interval limit.

As discussed herein, time intervals between (eg, adjacent) interrupt request signals relate to time intervals between the receipt of (eg, adjacent) interrupt request signals at, for example, the interrupt request signal propagation circuit.

In one example, the first to m-th interrupt request signals nIRQ_I1 to nIRQ_Im may be supplied to the first to m-th interrupt request signal holders, respectively, and the first to m-th interrupt request signal holders may be respectively connected to the first to (m) -th processor 580_1 to 580_m be coupled. In an exemplary embodiment, the first to m-th interrupt request signal holder and the interrupt request signal arbiter may operate in approximately one clock domain. A request / acknowledge handshake operation may be performed between the first through m-th interrupt request signal holders and the interrupt request signal arbiter.

The interrupt request signal propagation circuit 560 may control the time intervals between the output of the first to m-th interrupt request signals nIRQ_I1 to nIRQ_Im to be greater than or equal to the time interval threshold value by delaying the output of a (k + 1) th interrupt request signal which follows a k-th interrupt request signal (in this example k is an integer greater than or equal to 1) until a (k) th time interval between the (k) th interrupt request signal and the (k + 1 ) -th interrupt request signal is at least the same or substantially the same as the time interval limit (for example, when the (k) -th interval is greater than zero). In addition, the interrupt request signal propagation circuit 560 delays the output of the (k) th interrupt request signal or the output of the (k + 1) th interrupt request signal by the time interval limit (for example, when the (k) th time interval between the (k) th interrupt request signal and the (k + 1) th interrupt request signal is equal to or substantially equal to zero).

According to at least some example embodiments, the interrupt request signal propagation circuit 560 change an output order for the first to (m) -th interrupt request signal nIRQ_O1 to nIRQ_Om based on given, desired or predetermined priorities associated with the interrupts and / or the interrupt request signals, so that an output order for the first to (m) -th interrupt request signal nIRQ_O1 to nIRQ_Om is different from a feed order for the first to (m) -th interrupt request signal nIRQ_I1 to nIRQ_Im.

In at least some example embodiments, the interrupt request signal propagation circuit may 560 the first to (m) th processor 580_1 to 580_m into a first group having processors in an active state and a second group having processors in an inactive state, subdividing or grouping. Then, the interrupt request signal propagation circuit 560 under the first to (m) -th interrupt request signal nIRQ_I1 to nIRQ_It does not control time intervals between the output of the interrupt request signal assigned to the first group to be at least the time interval threshold, but it may determine the time intervals between the output of the interrupt request signals assigned to the second group, so that they are at least the time interval threshold. By controlling the time intervals between the first to the (m) -th interrupt request signal nIRQ_I1 to nIRQ_Im, which are generated based on the first to nth interrupt INT_R1 to INT_Rn to be greater than or equal to Time interval limit, can be the one-chip system 500 suppress and / or prevent modes of the first to (m) th processor 580_1 to 580_m from an inactive state to an active state within a relatively small time window (sometimes referred to as a sudden wake up) will be changed (eg, continuously changed) even if the interrupts are due to the interrupt sources 520_1 to 520_n be generated continuously within a relatively small time window. As a result, the one-chip system 500 achieve relatively high operational reliability by suppressing and / or preventing inrush surges due to a sudden wakeup of a plurality of processors (or a plurality of cores in a multi-core processor).

2 FIG. 10 is a flowchart illustrating a method of propagating a plurality of interrupt request signals according to an example embodiment. For clarity, the method which is in 2 with respect to the SOC which is shown in 1 is shown. It should be understood, however, that exemplary embodiments should not be limited to this implementation.

Referring to 2 receives at S120 the interrupt request signal propagation circuit 560 a plurality of interrupt request signals. At S140, the interrupt request signal propagation circuit checks 560 whether the time intervals between (for example, receipt of) the interrupt request signals (eg, time intervals between adjacent interrupt request signals) is less than a time interval limit.

If a time interval between interrupt request signals is less than the time interval limit, then the interrupt request signal propagation circuit controls 560 the time interval between the output of the interrupt request signals at S160 to be greater than or equal to the time interval threshold. The interrupt request signal propagation circuit 560 then outputs the interrupt request signals to a plurality of processors at S180, respectively.

Returning to S140, when a time interval between the interrupt request signals is greater than or equal to the time interval threshold, the interrupt request signal propagation circuit is obtained 560 for example, the time interval between the output of the interrupt request signals at S165 (for example, does not match). The interrupt request signal propagation circuit 560 then outputs the interrupt request signals to the plurality of processors at S180, respectively.

According to at least some example embodiments, the processors may correspond to separate processors or to a plurality of cores in a multi-core processor (eg, a dual-core processor, a quad-core processor, etc.). For simplicity, the processors are described as being in an active state or an inactive state. However, it should be understood that the active state corresponds to a normal operation mode such as an on state, etc., and that the inactive state corresponds to a low power mode such as a power down state, a power down state, etc. Hereinafter, the method which is described in 2 is shown in more detail with reference to the SOC which is shown in FIG 1 is shown.

Referring to the 1 and 2 receives, as mentioned above, the interrupt request signal propagation circuit 560 sequentially following the interrupt request signals at S120. The interrupt request signals may be generated based on a plurality of interrupts output from a plurality of interrupt sources, and may be assigned to respective processors. In this example, the interrupt sources are blocks of intellectual property blocks (IP blocks) that perform certain operations in the multi-core system (or multi-processor system). The interrupt sources may correspond to components of a system-on-chip (SOC) system, such as a video module, a sound module, a display module, a memory module, a communication module, a camera module, etc When the interrupts are generated by the interrupt sources, the interrupt request signals may be generated based on the interrupts and then provided for respective processors. The processors may then perform interrupt handling operations in response to the interrupt request signals, respectively. Recently, SOCs have been more widely used for electric devices because electrical devices become smaller and lighter. As described above, an SOC may include a plurality of IP blocks and a plurality of processors or a processor having a plurality of cores. In this example, the processors may more often enter a low power mode to reduce power consumption and may wake up from the low power mode in response to receipt of respective interrupt request signals. When processors from the low-power mode substantially wake up at the same time or substantially at the same time (sometimes referred to as a sudden wake-up), inrush surges may occur. Inrush currents are caused in the processors. The inrush surges can cause devices having SOCs to malfunction. As sizes of SOCs become smaller, it is relatively difficult for the SOCs to achieve relatively high operational reliability because inrush surges are also caused by dynamic current changes in the SOC.

Returning to 2 in response to the receipt of the interrupt request signals, checks the interrupt request signal propagation circuit 560 at S140, if the time intervals between the interrupt request signals are smaller than the time interval threshold. As mentioned above, in at least one example embodiment, the time interval limit may be determined to be within a range in which the inrush currents are not generated in the processors when modes of the processors are continuously changed from an inactive state to an active state ,

When a time interval between interrupt request signals is smaller than the time interval threshold, the interrupt request signal propagation circuit controls 560 the time interval between the output of the interrupt request signals to be at least equal to the time interval limit at S160.

In more detail, at S160, the interrupt request signal propagation circuit is controlled 560 the time interval being at least equal to the time interval limit by delaying the output of a (k + 1) th interrupt request signal following a (k) th interrupt request signal (where k is an integer greater than or is equal to 1) until a (k) -th time interval between the (k) -th interrupt request signal and the (k + 1) -th interrupt request signal becomes at least equal to or substantially the same as the time-interval limit value when the (k ) -th time interval is greater than zero (not zero). In this example, the (k) -th interrupt request signal and the (k + 1) th interrupt request signal are adjacent (e.g., consecutive or sequential inputs).

For example, two processors can wake up consecutively within a relatively small window of time (sometimes referred to as a sudden awakening) and, as a result, inrush surges can be caused in two processors when the (k) interrupt request signal and the (k + 1) -th interrupt request signal will be output to the two processors without controlling the (k) th time interval when the (k) th time interval is smaller than the time interval threshold. Thus, the interrupt request signal propagation circuit controls 560 the (k) -th time interval between the (k) -th interrupt request signal and the (k + 1) -th interrupt request signal to be the time interval limit value by delaying the output of the (k + 1) -th Interrupt request signal following the (k) interrupt request signal.

In addition, the interrupt request signal propagation circuit delays 560 the output of the (k) th interrupt request signal or the (k + 1) th interrupt request signal to at least the time interval limit when the (k) th time interval between the (k) th interrupt request signal and the (k) th interrupt request signal k + 1) -th interrupt request signal is equal to or substantially zero (the interrupt request signals are concurrently or simultaneously inputted.) As a result, inrush surges in two processors can be suppressed and / or prevented since the (k) th time interval passes through using the method of 2 is controlled so that it is at least the time interval limit when the (k) -th interrupt request signal and the (k + 1) -th interrupt request signal are input at the same time or substantially at the same time.

According to at least some example embodiments, the interrupt request signal propagation circuit 506 An output order of the interrupt request signals based on given, desired or predetermined priorities associated with the interrupts and / or interrupt request signals change when a time interval between the interrupt request signals is controlled to be greater than or equal to the time interval limit.

For example, assume that a (k) -th interrupt request signal, a (k + 1) -th interrupt request signal, and a (k + 2) -th interrupt request signal are successively input in this order. When a (k) -th time interval between the (k) -th interrupt request signal and the (k + 1) -th interrupt request signal and a (k + 1) -th time interval between the (k + 1) -th interrupt Request signal and the (k + 2) th interrupt request signal are smaller than the time interval limit, then controls the interrupt request signal propagation circuit 560 the (k) th time interval being greater than or equal to the time interval limit, by delaying the output of the (k + 1) th interrupt request signal following the (k) th interrupt request signal, and it then controls the (k + 1) th time interval to be greater than or equal to the time interval threshold by delaying the output of the (k + 2) th interrupt request signal corresponding to the (k + 1) - th Interrup request signal follows. However, in at least some embodiments, the interrupt request signal propagation circuit may 560 change an output order of the (k) th interrupt request signal, the (k + 1) th interrupt request signal and the (k + 2) th interrupt request signal based on given, desired or predetermined priorities of the interrupts.

For example, assume that the (k) -th interrupt request signal, the (k + 1) -th interrupt request signal, and the (k + 2) -th interrupt request signal are successively input, and that the (K) -th interrupt request signal has the highest priority and the (k + 1) -th interrupt request signal has the lowest priority. In this case, when a (k) -th time interval between the (k) -th interrupt request signal and the (k + 1) -th interrupt request signal and a (k + 1) th time interval between the (k + 1) -th interrupt request signal and the (k + 2) th interrupt request signal is smaller than the time interval limit, the interrupt request signal propagation circuit 560 then sequentially following the (k) th interrupt request signal, the (k + 2) th interrupt request signal and the (k + 1) th interrupt request signal in this order based on given, desired or predetermined priorities of the interrupts and or interrupt request signals.

Generally, when a processor receives an interrupt request signal, a mode of the processor changes from an inactive state to an active state. Then, the processor performs interrupt handling operations (or interrupt services) in response to the interrupt request signal corresponding to an interrupt generated by an interrupt source. Here, inrush surges can result because a plurality of transistors included in the processor suddenly operate. In particular, a low power processor may have a plurality of clock gating circuits to reduce power consumption in an active state. Thus, most clocks do not switch to an inactive state. When a mode of the processor is changed from an inactive state to an active state, inrush surges can result since most clocks switch concurrently or simultaneously. Furthermore, in the case where a one-chip system has a plurality of processors, when the processors are waking up from the low-power mode at the same or substantially the same time (sometimes referred to as a sudden wake-up), all of the inrush currents occurring in the processors are added, so that the inrush currents may cause an electrical device having the SOC to malfunction.

By controlling time intervals between an output of a plurality of interrupt request signals to be greater than or equal to the time interval threshold, the method of FIG 2 suppress and / or prevent modes of a plurality of processors (or a plurality of cores in a multi-core processor) from continuously changing from an inactive state to an active state within a relatively small amount of time, even if the interrupts are continuously interrupted by a Plurality of interrupt sources within a relatively small time window. As a result, an SOC performing the method of 2 to achieve a relatively high operational reliability by suppressing and / or preventing inrush currents due to the sudden waking up of a plurality of processors (or a plurality of cores in a multi-core processor). According to at least some example embodiments, the method of the 2 for a plurality of interrupt request signals which are supplied to a plurality of processors in an inactive state.

Returning to 2 gives the interrupt request signal propagation circuit 560 then the interrupt request signals at S180 to a plurality of processors, respectively.

Returning to S140 in 2 receives if one Time interval between the interrupt request signals is greater than the time interval limit, then the interrupt request signal propagation circuit 560 maintains (does not adjust) the time interval between the output of the interrupt request signals at S165. The interrupt request signal propagation circuit 560 then outputs the interrupt request signals to a plurality of processors at S180, respectively.

According to at least the exemplary embodiment, which in 2 is shown, gives the interrupt request signal propagation circuit 560 each of the interrupt request signals to the processors is controlled by controlling a time interval between the output of the interrupt request signals to be at least equal to the time interval limit value when the time interval between the interrupt request signals is less than the time interval limit value. The interrupt request signal propagation circuit 560 respectively, outputs the interrupt request signals to the processors without controlling (or adjusting) the time intervals when the time interval between the interrupt request signals is greater than or equal to the time interval threshold. As a result, the interrupt request signals for the processors may each be provided at a time interval which is greater than or equal to the time interval threshold.

The 3A and 3B 10 are diagrams illustrating an example in which a plurality of interrupt request signals are executed according to the method of FIG 2 is disseminated. 3A shows an example in which a first to a fourth interrupt request signal nIRQ_1 to nIRQ_4 are successively supplied, and 3B FIG. 15 shows an example in which the first through fourth interrupt request signals nIRQ_1 to nIRQ_4 successively follow first through fourth processors, respectively, according to the method of FIG 2 is issued.

As in 3A is illustrated, a first time interval S1 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 is smaller than a time interval threshold PS, a second time interval S2 between the second interrupt request signal nIRQ_2 and the third interrupt request signal nIRQ_3 is smaller than that Time interval threshold PS, and a third time interval S3 between the third interrupt request signal nIRQ_3 and the fourth interrupt request signal nIRQ_4 is also smaller than the second interval threshold PS.

As in 3B is illustrated, the output of the second interrupt request signal nIRQ_2 is delayed such that the first time interval 51 is at least equal to or substantially equal to the time interval threshold PS. In addition, the output of the third interrupt request signal nIRQ_3 is delayed such that the second time interval S2 is at least equal to or substantially equal to the time interval threshold PS. Furthermore, the output of the fourth interrupt request signal nIRQ_4 is delayed such that the third time interval S3 is at least equal to or substantially equal to the time interval threshold PS. As described above, the first to fourth interrupt request signals nIRQ_1 to nIRQ_4 may be successively output to the first to fourth processors at time intervals corresponding to the time interval threshold PS, respectively.

The 4A and 4B FIG. 15 are diagrams illustrating another example in which a plurality of interrupt request signals are executed according to the method of FIG 2 to be spread. 4A shows an example in which a first to fourth interrupt request signal nIRQ_1 to nIRQ_4 are successively supplied, and 4B FIG. 15 shows an example in which the first through fourth interrupt request signals nIRQ_1 to nIRQ_4 successively follow first through fourth processors, respectively, according to the method of FIG 2 is issued.

More detailed is how in 4A 1, a first time interval S1 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 is greater than a time interval limit PS, a second time interval S2 between the second interrupt request signal nIRQ_2 and the third interrupt request signal nIRQ_3 is less than the time interval limit PS, and a third time interval S3 between the third interrupt request signal nIRQ_3 and the fourth interrupt request signal nIRQ_4 is also smaller than the time interval threshold PS.

As in 4B is illustrated in accordance with the methods of 2 the first time interval S1 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 is maintained and not adjusted, whereas the output of the third interrupt request signal nIRQ_3 is delayed such that the second time interval S2 is greater than or equal to the time interval threshold PS and the output of the fourth interrupt request signal nIRQ_4 is delayed such that the third time interval S3 is greater than or equal to the time interval threshold PS. The first to fourth interrupt request signals nIRQ_1 to nIRQ_4 are sequentially output to the first to fourth processors respectively at time intervals greater than or equal to the time interval threshold PS.

The 5A and 5B 15 are diagrams illustrating still another example in which a plurality of interrupt request signals are executed according to the method of FIG 2 to be spread. 5A shows an example in which a first to fourth interrupt request signal nIRQ_1 to nIRQ_4 are successively supplied, and 5B FIG. 15 shows an example in which the first through the fourth interrupt request signals nIRQ_1 to nIRQ_4 are sequentially sent to first to fourth processors according to the method of FIG 2 be issued.

As in 5A is a first time interval 51 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 is smaller than a time interval threshold PS, a second time interval S2 between the second interrupt request signal nIRQ_2 and the third interrupt request signal nIRQ_3 is smaller than the time interval threshold PS, and a third time interval S3 between the third interrupt request signal nIRQ_3 and the fourth interrupt request signal nIRQ_4 is also smaller than the time interval threshold PS.

According to performance of an SOC in an electrical device, inrush surges in two processors may not be caused even if two processors simultaneously or concurrently or sequentially wake up within a relatively small time window, inrush surges can be caused in three processors if three processors wake up simultaneously or concurrently or sequentially within a relatively small window of time.

As in the 5A and 5B is illustrated, it may according to the methods of 2 two processors may be allowed to wake up sequentially within a relatively small time window, but more than two processors may not. For example, as in the 5A and 5B 2, the first time interval S1 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 is maintained (not adjusted), although the first time interval S1 is smaller than the time interval threshold PS. In this example, a given, desired, or predetermined number of processors (eg, two processors) are allowed to wake up sequentially within a relatively small time window. However, the output of the third interrupt request signal nIRQ_3 is delayed such that the second time interval S2 is greater than or equal to the time interval threshold PS. Accordingly, according to the method of 2 suppresses and / or prevents three processors from waking up consecutively within a relatively small time window. Then, as in 5B is shown, the third time interval S3 between the third interrupt request signal nIRQ_3 and the fourth interrupt request signal nIRQ_4 maintained and not adjusted, even if the third time interval S3 is smaller than the time interval threshold PS.

6 FIG. 10 is a flow chart illustrating a method of propagating a plurality of interrupt request signals, according to another example embodiment. As in 2 For clarity, the method is described in 6 with reference to the SOC which is shown in FIG 1 is shown. It should be understood, however, that exemplary embodiments should not be limited to this implementation.

Referring to 6 receives the interrupt request signal propagation circuit 560 a (k) -th interrupt request signal at S210 and then receives a (k + 1) -th interrupt request signal at S220.

At S230, the interrupt request signal propagation circuit checks 560 whether a time interval between the (k) th interrupt request signal and the (k + 1) th interrupt request signal is greater than zero.

If the time interval between the (k) th interrupt request signal and the (k + 1) th interrupt request signal is greater than zero, then the interrupt request signal propagation circuit delays 560 the output of the (k) th interrupt request signal at S240 until the time interval becomes at least the same or substantially the same as the time interval limit.

Returning to S230, when a time interval between the (k) interrupt request signal and the (k + 1) th interrupt request signal is equal to zero, at S250, the interrupt request signal distribution circuit delays 560 the output of the (k) th interrupt request signal and the output of the (k + 1) th interrupt request signal by at least the time interval limit based on given, desired or predetermined priorities associated with the interrupts and / or interrupt request signals ,

Generally, the (k) -th interrupt request signal and the (k + 1) -th interrupt request signal are successively supplied, so that a time interval between the (k) -th interrupt request signal and the (k + 1) - th interrupt request signal is greater than zero. However, according to at least some example embodiments, the (k) -th interrupt request signal and the (k + 1) -th interrupt request signal may be supplied at the same or substantially the same time (e.g., concurrent or concurrent). In this example, the interrupt request signal propagation circuit checks 560 whether a time interval between the (k) th interrupt request signal and the (k + 1) th interrupt request signal is greater than zero.

If a time interval between the (k) -th interrupt Request signal and the (k + 1) th interrupt request signal is greater than zero, but less than the time interval limit, then delays the interrupt request signal propagation circuit 560 the output of the (k) th interrupt request signal until the time interval becomes at least the same or substantially the same as the time interval limit.

On the other hand, when a time interval between the (k) th interrupt request signal and the (k + 1) th interrupt request signal is equal to zero, the interrupt request signal propagation circuit is delayed 560 the output of the (k) th interrupt request signal or the output of the (k + 1) th interrupt request signal by at least the time interval limit based on the given, desired or predetermined priorities associated with the interrupts and / or interrupt request signals are. As a result, the (k) -th interrupt request signal and the (k + 1) -th interrupt request signal to a (k) -th processor and a (k + 1) -th processor at a time interval corresponding to at least the Time interval limit output, even if the (k) -th interrupt request signal and the (k + 1) -th interrupt request signal at the same or substantially the same time (for example, concurrent or concurrent) are supplied. Accordingly, the method of the 6 suppress and / or prevent modes of a plurality of processors included in an SOC from being continuously changed from an inactive state to an active state within a relatively small time window (sometimes referred to as a sudden awakening).

The 7A and 7B 10 are diagrams illustrating an example in which a plurality of interrupt request signals are executed according to the method of FIG 6 to be spread. 7A shows an example in which a first to a fourth interrupt request signal nIRQ_1 to nIRQ_4 are successively supplied, and 7B FIG. 15 shows an example in which the first through the fourth interrupt request signals nIRQ_1 to nIRQ_4 are sequentially sent to first to fourth processors according to the method of FIG 6 be issued.

In the example which is in 7A 4, adjacent interrupt request signals nIRQ_3 and nIRQ_4 are supplied at the same or substantially the same time (for example, concurrently or concurrently), whereas the interrupt request signals nIRQ_1 and nIRQ_2 are successively supplied. A first time interval S1 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 is smaller than a time interval threshold PS, a second time interval S2 between the second interrupt request signal nIRQ_2 and the third interrupt request signal nIRQ_3 (or the fourth interrupt request signal nIRQ_4) is smaller than the time interval threshold PS, and a time interval between the third interrupt request signal nIRQ_3 and the fourth interrupt request signal nIRQ_4 is equal to or substantially equal to zero.

As in 7B 1, it is assumed that a priority of the fourth interrupt request signal nIRQ_4 is higher than a priority of the third interrupt request signal nIRQ_3. The output of the second interrupt request signal nIRQ_2 is delayed such that the first time interval 51 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 is greater than or equal to the time interval threshold PS. In addition, the output of the fourth interrupt request signal nIRQ_4 is delayed such that the second time interval S2 between the second interrupt request signal nIRQ_2 and the fourth interrupt request signal nIRQ_4 is greater than or equal to the time interval threshold PS. Furthermore, the output of the third interrupt request signal nIRQ_3 is delayed by the time interval threshold PS after the output of the fourth interrupt request signal nIRQ_4.

In the example, which in the 7A and 7B 4, the fourth interrupt request signal nIRQ_4 is output before the third interrupt request signal nIRQ_3 because a priority of the fourth interrupt request signal nIRQ_4 is higher than a priority of the third interrupt request signal nIRQ_3. The first to fourth interrupt request signals nIRQ_1 to nIRQ_4 are respectively output to the first to fourth processors at time intervals corresponding to the time interval threshold PS based on given, desired or predetermined priorities when adjacent interrupt request signals (eg, the third interrupt request signal nIRQ_3 and the fourth interrupt request signal nIRQ_4) are supplied at the same or substantially the same time (for example, simultaneously or concurrently).

8th FIG. 10 is a flow chart illustrating a method of propagating a plurality of interrupt request signals, according to another example embodiment. As for 2 For the sake of clarity, the method which is used in 8th with reference to the SOC which is shown in 1 is shown. It should be understood, however, that exemplary embodiments should not be limited to this implementation.

Referring to 8th receives the interrupt request signal propagation circuit 560 a (k) -th interrupt request signal at S310, and then receives a (k + 1) -th interrupt request signal at S320. Although this exemplary embodiment is described with reference to the (k) -th interrupt request signal and the (k + 1) -th interrupt request signal, which are successively received, For example, exemplary embodiments may be equally applicable to interrupt request signals received concurrently or concurrently.

The interrupt request signal propagation circuit 560 then checks at S330 whether a priority of the (k) th interrupt request signal is higher than a priority of the (k + 1) th interrupt request signal.

If the priority of the (k) -th interrupt request signal is higher than the priority of the (k + 1) th interrupt request signal, then the interrupt request signal propagation circuit delays 560 at S340, the output of the (k + 1) th interrupt request signal.

Returning to S330, when a priority of the (k) -th interrupt request signal is less than the priority of the (k + 1) -th interrupt request signal, the interrupt request signal propagation circuit delays 560 the output of the (k) th interrupt request signal at S350.

In the exemplary embodiment, which is in 8th 2, it is assumed that a time interval between the (k) th interrupt request signal and the (k + 1) th interrupt request signal is smaller than the time interval threshold.

In accordance with the procedure of 8th may be the interrupt request signal propagation circuit 560 sequentially receive the (k) th interrupt request signal and the (k + 1) th interrupt request signal and check whether a time interval between the (k) th interrupt request signal and the (k + 1) th interrupt Request signal is less than the time interval limit. The interrupt request signal propagation circuit 560 Also checks whether a priority of the (k) -th interrupt request signal is higher than a priority of the (k + 1) th interrupt request signal. Then, the interrupt request signal propagation circuit determines 560 an output order for the (k) th interrupt request signal and the (k + 1) th interrupt request signal based on given, desired, or predetermined priorities associated with the interrupt request signals, regardless of or independent of an input order for the interrupt request signal (k) th interrupt request signal and the (k + 1) th interrupt request signal.

For example, in more detail, the interrupt request signal propagation circuit delays 560 the output of the (k + 1) th interrupt request signal when a priority of the (k) th interrupt request signal is higher than a priority of the (k + 1) th interrupt request signal. On the other hand, the interrupt request signal propagation circuit delays 560 the output of the (k) th interrupt request signal when a priority of the (k) th interrupt request signal is less than a priority of the (k + 1) th interrupt request signal. As a result, the (k) -th interrupt request signal and the (k + 1) -th interrupt request signal to a (k) -th processor and a (k + 1) -th processor at a time interval which is at least corresponding to the time interval threshold based on given, desired or predetermined priorities. Accordingly, the method of the 8th suppress and / or prevent modes of a plurality of processors included in an SOC from being continuously changed from an inactive state to an active state within a relatively small period of time (sometimes referred to as a sudden awakening).

The 9A and 9B 10 are diagrams illustrating an example in which a plurality of interrupt request signals are executed according to the methods of FIG 8th to be spread. The 9A shows an example in which a first to fourth interrupt request signal nIRQ_1 to nIRQ_4 are successively supplied, and 9B FIG. 12 shows an example in which the first through fourth interrupt request signals nIRQ_1 through nIRQ_4 are each sent to first through fourth processors based on given, desired or predetermined priorities according to the methods of FIGS 8th be issued.

As in 9A is illustrated, a first time interval S1 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 is smaller than a time interval threshold PS, a second time interval S2 between the second interrupt request signal nIRQ_2 and the third interrupt request signal nIRQ_3 is smaller than that Time interval threshold PS and a third time interval S3 between the third interrupt request signal nIRQ_3 and the fourth interrupt request signal nIRQ_4 is smaller than the time interval threshold PS. In at least one example embodiment, according to the required conditions for an SOC in an electrical device, it may be necessary for an output order for the first to fourth interrupt request signals nIRQ_1 to nIRQ_4 to be different from a supply order for the first to fourth interrupt request signals nIRQ_1 to nIRQ_4 is. Thus, an output order for the first to fourth interrupt request signals nIRQ_1 to nIRQ_4 may be changed based on given, desired or predetermined priorities associated with the interrupt request signals nIRQ_1 to nIRQ_4.

By using the method of 8th For example, a wake-up order for first through fourth processors that perform interrupt handling operations in response to the first through fourth interrupt request signals nIRQ_1 through nIRQ_4 can be changed by changing an output order for the first through fourth interrupt request signals nIRQ_1 through nIRQ_4 based on the given one, adjusted to desired or predetermined priorities.

As in 9B 1, the interrupt request signal propagation circuit gives the first interrupt request signal nIRQ_1, the third interrupt request signal nIRQ_3, the fourth interrupt request signal nIRQ_4 and the second interrupt request signal nIRQ_2 based on the given, desired or predetermined priorities regardless or independent of the supply order of the first to fourth interrupt request signal nIRQ_1 to nIRQ_4. Meanwhile, the time intervals between the first interrupt request signal nIRQ_1, the third interrupt request signal nIRQ_3, the fourth interrupt request signal nIRQ_4 and the second interrupt request signal nIRQ_2 are controlled to be greater than or equal to the time interval threshold PS. As a result, the first to fourth interrupt request signals nIRQ_1 to nIRQ_4 are respectively output to a first to fourth processors at a time interval corresponding to at least the time interval threshold PS, based on the given, desired or predetermined priorities.

10 FIG. 10 is a flowchart illustrating a method of propagating a plurality of interrupts according to another exemplary embodiment; and FIG 11 FIG. 13 is a diagram illustrating a plurality of processors in an active state and a plurality of processors in an inactive state. FIG. The method, which in 10 is shown with reference to the SOC, which in 1 is shown, and the processors, which in 11 are shown are described.

Referring to the 1 . 10 and 11 receives at S410 the interrupt request signal propagation circuit 560 successively a plurality of interrupt request signals. At S420, the interrupt request signal propagation circuit divides or groups 560 the interrupt request signals in target interrupt request signals and non-target interrupt request signals.

According to at least this exemplary embodiment, the target interrupt request signals are interrupt request signals which are allocated (eg, scheduled to be outputted) to processors TP_1 to TP_4 in an inactive state, whereas the non-target interrupt request signals are interrupt request signals. which processors NTP_1 and NTP_2 are assigned in an active state.

Returning to 10 gives the interrupt request signal propagation circuit 560 at S430, the non-target interrupt request signals to the processors NTP_1 and NTP_2 immediately in an active state. Meanwhile, the interrupt request signal propagation circuit checks 560 at S440, if the time intervals between target interrupt request signals (eg, time intervals between adjacent target interrupt request signals) are less than a time interval threshold.

If a time interval between target interrupt request signals is less than the time interval threshold, then the interrupt request signal propagation circuit controls 560 at S450, a time interval between the output of the target interrupt request signals to be greater than or equal to the time interval threshold. The interrupt request signal propagation circuit 560 Then, at S480, outputs the target interrupt request signals to the processors TP_1 to TP_4 in an inactive state, respectively.

Returning to S440, if a time interval between target interrupt request signals is greater than or equal to the time interval threshold, then the interrupt request signal propagation circuit is obtained 560 the time interval between the output of the target interrupt request signals at S460 upright (does not match this). The interrupt request signal propagation circuit 560 then outputs the target interrupt request signals to the processors TP_1 to TP_4 in an active state at S480, respectively.

According to the method of 10 For example, time intervals between the non-target interrupt request signals are not controlled because the processors NTP_1 and NTP_1 are in an active state and do not require wake-up. However, the time intervals between target interrupt request signals assigned to the processor in TP_1 to TP_4 in the inactive state are controlled to be greater than or equal to the time interval threshold. As a result, an SOC performing the method of 10 operate at higher speeds because the number of interrupt request signals (e.g., loads) being handled is reduced.

12 FIG. 10 is a block diagram illustrating an interrupt request signal propagation circuit according to an example embodiment. FIG. The interrupt request signal propagation circuit, which in 12 can be shown as the interrupt request signal propagation circuit 560 , what a 1 shown serve.

Referring to 12 indicates the interrupt request signal propagation circuit 100 an interrupt request signal arbiter 140 and a first to (m) -th interrupt request signal holder 120_1 to 120_m on. In this example, m is an integer greater than or equal to 2.

The first to (m) th interrupt request signal holder 120_1 to 120_m is configured to receive respectively a first to (m) -th interrupt request signal nIRQ_I1 to nIRQ_Im, and a first to (m) -th interrupt request signal nIRQ_O1 to nIRQ_Om to a first to (m) -th processor (not in 12 illustrated) at respective time intervals greater than or equal to a time interval threshold.

The first to m-th interrupt request signals nIRQ_I1 to nIRQ_Im are generated based on a plurality of interrupts which are received from a plurality of interrupt sources (not in FIG 12 illustrated). In addition, the first to (m) th interrupt request signals nIRQ_I1 to nIRQ_Im become respectively the first to (m) th interrupt request signal holders 120_1 to 120_m fed. Meanwhile, the first to the (m) th interrupt request signal holder 120_1 to 120_m each coupled to the first to (m) th processor. In addition, the first to the (m) -th interrupt request signal holder 120_1 to 120_m the first to (m) th interrupt request signal nIRQ_O1 to nIRQ_Om to the first to (m) th processor each at time intervals greater than or equal to the time interval threshold.

Send in detail by referring to 12 if the first to (m) -th interrupt request signal holder 120_1 to 120_m receiving the first to (m) th interrupt request signal nIRQ_I1 to nIRQ_Im, respectively, the first to (m) th interrupt request signal holder 120_1 to 120_m respective output request signals RS1 to RSm to the interrupt request signal arbiter 140 , If the first to (m) -th interrupt request signal holder 120_1 to 120_m respective output acknowledge signals AS1 to ASm from the interrupt request signal arbiter 140 receive the first (m) -th interrupt request signal holder 120_1 to 120_m the first to (m) -th interrupt request signal nIRQ_O1 to nIRQ_Om each to the first to (m) -th processor.

For this operation, each of the first to (m) -th interrupt request signal holders 120_1 to 120_m by a state machine having an idle state, a wait state, and an assert state. An example state machine implementation will become more detailed below with reference to FIG 13 to be discribed.

The interrupt request signal arbiter 140 is configured to control time intervals between the output of the first to m-th interrupt request signal (eg, a time interval between the output of adjacent interrupt request signals) to be greater than or equal to a time interval threshold when the time intervals between the first to (m) th interrupt request signal is less than the time interval limit. In this example, the time interval threshold may be a given, desired, or predetermined time interval value within a range. in which inrush surges are not caused in the first to (m) th processor when modes of the processors are continuously changed from an inactive state to an active state.

Still referring to 12 receives the interrupt request signal arbiter 140 respectively the output request signals RS1 to RSm from the first to the (m) th interrupt request signal holder 120_1 to 120_m , Then, the interrupt request signal arbiter controls 140 the first to (m) -th interrupt request signal holder 120_1 to 120_m to obtain the first to m-th interrupt request signals nIRQ_O1 to nIRQ_Om respectively to the first to m-th processor at time intervals which are greater than or equal to the time-interval threshold value by outputting the output confirmation signals AS1 to ASm each to the first to (m) -th interrupt request signal holder 120_1 to 120_m to output at time intervals which are greater than or equal to the time interval limit. For this operation, the interrupt request signal arbiter 140 be implemented by a state machine having an idle state and a wait state. An example state machine implementation will become more detailed below with reference to FIG 14 to be discribed.

In at least one example embodiment, the interrupt request signal arbiter 140 change an output order of the first to (m) th interrupt request signal nIRQ_O1 to nIRQ_Om based on given, desired or predetermined priorities associated with the interrupt request signals nIRQ_O1 to nIRQ_Om. As a result, a Feed order of the first to (m) -th interrupt request signal nIRQ_I1 to nIRQ_Im corresponding to the first to (m) -th interrupt request signal holder 120_1 to 120_m be different from an output order of the first to (m) -th interrupt request signal nIRQ_O1 to nIRQ_Om, which are from the first to (m) -th interrupt request signal holder 120_1 to 120_m be issued.

In at least one example embodiment, the interrupt request signal arbiter 140 the first to (m) th processor into a first group having processors in an active state and a second group having processors in an inactive state, subdivide or group. Among the first to (m) -th interrupt request signals nIRQ_I1 to nIRQ_Im, the interrupt request signal arbiter may 140 but do not control the time intervals between interrupt request signals associated with the first group to be the time interval limit, but may control each time interval among interrupt request signals associated with the second group to be greater than or equal to to the time interval limit.

As described above, by controlling the time intervals between an output of a plurality of interrupt request signals, which are generated based on a plurality of interrupts to be greater than or equal to the time interval threshold, the interrupt request signal propagation circuit 100 suppress and / or prevent modes of a plurality of processors (or a plurality of cores in a multi-core processor) from being continuously changed from an inactive state to an active state within a relatively small amount of time (sometimes referred to as abrupt Wake up) even though the interrupts are continuously generated by a plurality of interrupt sources within a relatively small time window. As a result, an SOC representing the interrupt request signal propagation circuit 100 to achieve a relatively high operational reliability by suppressing and / or preventing inrush surges due to a sudden wakeup of a plurality of processors (or a plurality of cores in a multi-core processor).

13 FIG. 12 is a diagram illustrating an example state machine implementation of the interrupt request signal holder incorporated in FIG 12 shown is illustrated. One or more of the first to (m) -th interrupt request signal holder 120_1 to 120_m can be controlled by a state machine like the one in 13 is shown to be implemented. However, example embodiments are not limited to this implementation. For the sake of clarity, will 13 with reference to the (n) th interrupt request signal holder 120_n and the n-th interrupt request signal nIRQ_In. It should be understood, however, that each of the first to (m) -th interrupt request signal holder 120_1 to 120_m can work in the same or substantially the same way.

Referring to 13 indicates the state machine 200 an idle state 220 , a wait state 240 and an assert state 260 on. The idle state 220 indicates that the interrupt request signal holder 120_n has not received the interrupt request signal nIRQ_In. The wait state 240 indicates that the interrupt request signal holder 120_n for the output confirmation signal ASn from the interrupt request signal arbiter 104 waiting. The assert state 260 indicates that the interrupt request signal holder 120_n the interrupt request signal nIRQ_On to the (n) th processor 580_n has spent or is spending. In this example, the idle state is the same 220 a default state for the interrupt request signal holder 120_n ,

Details remain with reference to 13 the first to (m) th interrupt request signal holder 120_1 to 120_m in the idle state 220 until they respectively receive the first to (m) th interrupt request signals nIRQ_I1 to nIRQ_Im. In response to the receipt of the first to (m) th interrupt request signals nIRQ_I1 to nIRQ_Im, the first to (m) th interrupt request signal holders occur 120_1 to 120_m in the wait state 240 or the assert state 260 one.

For example, if the interrupt request signal holder is transmitting 120_n receives an interrupt request signal nIRQ_In, the interrupt request signal holder 120_n an output request signal RSn to the interrupt request signal arbiter 140 , When the interrupt request signal arbiter 140 an output confirmation signal ASn to the interrupt request signal holder 120_n immediately outputs, then the interrupt request signal holder occurs 120_n in the assert state 260 (RA). However, if the interrupt request signal arbiter 140 no output confirmation signal ASn to the interrupt request signal holder 120_n immediately outputs, then the interrupt request signal holder occurs 120_n in the wait state 240 (RNA). In this case, the interrupt request signal arbiter delays 140 the output of the output confirmation signal ASn to control a time interval between the output of the interrupt request signals (for example, a time interval) between the output of adjacent interrupt request signals).

Subsequently, the interrupt request signal holder receives 120_n the output confirmation signal ASn from the interrupt request signal arbiter 140 while he is in the wait state 240 is. In response to the output confirmation signal ASn, the interrupt request signal holder enters 120_n in the assert state 260 (AR).

After the interrupt request signal holder 120_n the interrupt request signal nIRQ_On to the (n) -th processor while in the assert state 260 is, returns the interrupt request signal holder 120_n in the idle state 220 (AL) back. As described above, each of the first to (m) -th interrupt request signal holder may 120_1 to 120_m by a state machine having a relatively simple structure.

14 FIG. 12 is a diagram illustrating an example state machine implementation of the interrupt request signal arbiter which is shown in FIG 12 shown is illustrated.

Referring to 14 indicates the state machine 300 an idle state 320 and a wait state 340 on. The idle state 320 indicates that none of the first to (m) -th interrupt request signal nIRQ_O1 to nIRQ_Om is output to the first to (m) th processor. The wait state 340 indicates that at least one of the first to (m) -th interrupt request signal nIRQ_O1 to nIRQ_Om is output to the first to (m) th processor. In this example, the idle state is the same 320 a default state for the interrupt request signal arbiter 140 ,

The interrupt request signal arbiter 140 can in the idle state 320 until it receives any of the output request signals RS1 to RSm from the first to the (m) th interrupt request signal holder 120_1 to 120_m receives. In response to receipt of an output request signal (eg, RSn from the interrupt request signal holder 120_n ) enters the interrupt request signal arbiter 140 in the wait state 340 (REQ) and immediately gives an output confirmation signal ASn to the interrupt request signal holder 120_n out. The interrupt request signal arbiter 140 remains in the wait state 340 during a given, desired, or predetermined time interval (eg, the time interval threshold). Then the interrupt request signal arbiter returns 140 in the idle state 320 (EXP) back. According to at least this exemplary embodiment, while the interrupt request signal arbiter 140 in the wait state 340 is the interrupt request signal arbiter 140 no other output acknowledge signals to other interrupt request signal holders, even if other interrupt request signal holders their output request signal to the interrupt request signal arbiter 140 send. As a result, the first to m-th interrupt request signals nIRQ_O1 to nIRQ_Om are output to the first to m-th processor at time intervals that are greater than or equal to the time-interval threshold, respectively. As described above, the interrupt request signal arbiter 140 by a state machine having a relatively simple structure.

15 FIG. 13 is a timing chart showing an exemplary operation of the interrupt request signal propagating circuit of FIG 12 illustrated.

Referring to 15 when an (i) th interrupt request signal nIRQ_Ii is given to the (i) th interrupt request signal holder 120_i in the interrupt request signal propagation circuit 100 is supplied to the (i) th interrupt request signal holder 120_i an output request signal RSiREQ to the interrupt request signal arbiter 140 out. As the interrupt request signal arbiter 140 in an idle state IDLE (no previous interrupt request signal exists), the interrupt request signal arbiter 140 immediately output an assertion signal ASi ACK to the (i) th interrupt request signal holder 120_i out.

In response to the output confirmation signal ASi ACK, the (i) th interrupt request signal holder goes 120_i from the idle state IDLE to an assert state ASSERT via and the interrupt request signal arbiter 140 goes from the idle state IDLE to a wait state WAIT. Thus, the (i) th interrupt request signal nIRQ_Oi is output to the (i) th processor.

While the interrupt request signal propagation circuit 140 is WAIT in the wait state, if the (j) -th interrupt request signal holder is 120_j an output request signal RSj REQ to the interrupt request signal arbiter 140 in response to receiving a (j) -th interrupt request signal nIRQ_Ij, the interrupt request signal arbiter 140 no output confirmation signal ASj ACK to the (j) -th interrupt request signal holder 120_j out. The amount of time during which the interrupt request signal arbiter 140 in the wait state WAIT can be determined by considering various conditions such as physical Characteristics, etc., and can be adjusted by a circuit such as a counter, etc.

According to at least some example embodiments, the (j) -th interrupt request signal holder 120_j from idle state IDLE to a WAIT wait state rather than an assert ASSERT state. After the interrupt request signal arbiter 140 enters idle state IDLE from a wait state WAIT, when a time interval between the (i) th interrupt request signal nIRQ_Oi and the (j) th interrupt request signal nIRQ_Oj becomes at least the same or substantially the same as the time interval limit, the interrupt request signal arbiter 140 an output confirmation signal ASj ACK to the (j) -th interrupt request signal holder 120_j out. In response to the output confirmation signal ASj ACK, the (j) th interrupt request signal holder goes 120_j from the wait state WAIT to the assert state ASSERT and outputs the (j) -th interrupt request signal nIRQ_Oj to the (j) th processor.

As in 15 1, the (i) -th interrupt request signal nIRQ_Oi and the (j) -th interrupt request signal nIRQ_Oj may be applied to the (i) th processor and the (j) th processor, respectively, at a time interval greater than or is equal to the time interval limit.

As described above, by controlling the time intervals between a plurality of interrupt request signals (for example, a time interval between adjacent interrupt request signals) to be greater than or equal to the time interval threshold value, the interrupt request signal propagation circuit can 100 suppress and / or prevent modes of a plurality of processors (or a plurality of cores in a multi-core processor) from being continuously changed from an inactive state to an active state within a relatively small amount of time (sometimes referred to as abrupt Wake up) even though the interrupts are continually generated by a plurality of interrupt sources within a relatively short period of time.

16 FIG. 4 is a block diagram illustrating an exemplary software implementation of an interrupt request signal propagation circuit according to an example embodiment. The interrupt request signal propagation circuit, which in 16 can be shown as the interrupt request signal propagation circuit 560 , what a 1 shown serve.

Referring to 16 The interrupt request signal propagation circuit comprises a plurality of level detectors LD1, LD2, LD3, ..., LDm. In this example, m is an integer greater than or equal to 2. The plurality of level detectors LD1 through LDm detect changes in respective ones of the plurality of interrupt request signals nIRQ_I1 through nIRQ_Im to provide new interrupts (and / or interrupt requests). for the main processor to identify / capture. When new interrupts and / or interrupt requests are detected for the main processor, the microcontroller interrupt controller notifies 1302 the microcontroller 1308 over a bus 1306 ,

The microcontroller 1308 controls the output of the new interrupt requests (eg, new interrupt requests from the interrupt request signals nIRQ_I1 to nIRQ_Im) such that the time intervals between the issuance of the interrupt request signals (eg, one from nIRQ_O1 to nIRQ_Om corresponding to the new interrupt requests) increases is equal to or equal to the time interval limit. For example, the microcontroller 1308 the new interrupt request for a given or desired period of time (for example, by storing the interrupt request in a random access memory (RAM)) 1310 ) and then delay the interrupt request signal by the general-purpose I / O circuit 1304 (general purpose I / O circuit).

The RAM 1310 and / or the read-only memory (ROM) 1312 , what a 16 are configured to store interrupt requests during the delay discussed above, and / or to store an indication of the action to be taken in response to the detected interrupt signal.

The microcontroller 1308 updates the physical signals in the interrupt output lines nIRQ_O1 to nIRQ_Om via the general purpose input / output circuit 1304 , The microcontroller 1308 communicates with the general purpose input / output circuit 1304 over the bus 1306 , Because multi-purpose input / output circuits, such as the one in 16 is well known, a detailed discussion is omitted.

The signals are sent to processors, for example 580_1 to 580_m in the same or substantially the same manner as discussed above with respect to at least some other exemplary embodiments.

In accordance with at least this exemplary embodiment, the microcontroller interrupt controller is 1302 which is in 16 shown by the interrupt controller 540 which is in 1 is shown, separated. 17 FIG. 15 is a diagram illustrating an exemplary operation of an interrupt request signal propagation circuit for the SOC of FIG 1 illustrated.

17 shows an example in which the first to (m) -th interrupt request signal holder 562_1 to 562_m the interrupt request signal propagation circuit 560 by an interrupt request signal arbiter (not shown) of the interrupt request signal propagation circuit 560 in the SOC 500 to be controlled. Thus, the first to (m) -th interrupt request signal nIRQ_I1 to nIRQ_Im to the first to (m) -th processor 580_1 to 580_m as the first to (m) -th interrupt request signal nIRQ_O1 to nIRQ_Om are respectively output at time intervals corresponding to the time interval threshold PS. As in 17 For the sake of simplicity, it is assumed that m is 4.

Detailed generated when the first to (n) th interrupt source 520_1 to 520_n output the first to the (n) th interrupt INT_R1 to INT_Rn, the interrupt controller 540 the first to fourth interrupt request signals nIRQ_I1 to nIRQ_I4 based on the first to (n) th interrupt INT_RI to INT_Rn. As in 17 1, the first interrupt request signal nIRQ_I1, the third interrupt request signal nIRQ_I3, the second interrupt request signal nIRQ_I2, and the fourth interrupt request signal nIRQ_I4 are respectively sequenced by the first interrupt request signal holder 562_1 , the third interrupt request signal holder 562_3 , the second interrupt request signal holder 562_2 and the fourth interrupt request signal holder 562_4 receive.

The first interrupt request signal holder 562_1 immediately gives the first interrupt request signal nIRQ_O1 to the first processor 580_1 because no previous interrupt request signal exists before the first interrupt request signal nIRQ_i1. The third interrupt request signal holder 562_3 delays the output of the third interrupt request signal nIRQ_I3 by a period DL1 since a time interval between the first interrupt request signal nIRQ_I1 and the third interrupt request signal nIRQ_I3 is smaller than the time interval threshold PS. The third interrupt request signal holder 562_3 then gives the third interrupt request signal nIRQ_O3 to the third processor 580_3 out.

The second interrupt request signal holder 562_2 delays the output of the second interrupt request signal nIRQ_I2 by a period DL2 and then outputs the second interrupt request signal nIRQ_O2 to the second processor 580_2 out.

The fourth interrupt request signal holder 562_4 delays the output of the fourth interrupt request signal nIRQ_I4 by a period DL3, and then outputs the fourth interrupt request signal nIRQ_O4 to the fourth processor 5804 out.

In accordance with at least this exemplary embodiment, inrush surges may occur due to a sudden waking up of the first to fourth processors 580_1 to 580_4 suppressed and / or prevented since the first to fourth processor 580_1 to 580_4 receive the first to fourth interrupt request signals nIRQ_O1 to nIRQ_O4 each at a time interval corresponding to at least the time interval threshold PS.

18 FIG. 15 is a diagram illustrating another exemplary operation of an interrupt request signal propagation circuit for the SOC of FIG 1 illustrated.

18 shows an example in which the first to (m) -th interrupt request signal holder 562_1 to 562_m the interrupt request signal propagation circuit 560 by an interrupt request signal arbiter (in 18 not shown) of the interrupt request signal propagation circuit 560 in the one-chip system (system-on-chip) 500 to be controlled. In this example, the first to (m) th interrupt request signals nIRQ_I1 to nIRQ_Im become the first to (m) th processors, respectively 580_1 to 580_m is output as the first to m-th interrupt request signal nIRQ_O1 to nIRQ_Om at time intervals which are greater than or equal to the time interval threshold PS. As in 18 For the sake of simplicity, it is assumed that m is 4.

Detailed generated when the first to (n) th interrupt source 520_1 to 520_n output the first to the (n) th interrupt INT_R1 to INT_Rn, the interrupt controller 540 the first to fourth interrupt request signals nIRQ_I1 to nIRQ_I4 based on the first to (n) th interrupts INT_R1 to INT_Rn. As in 18 1, the first interrupt request signal nIRQ_I1, the second interrupt request signal nIRQ_I2, the fourth interrupt request signal nIRQ_I4, and the third interrupt request signal nIRQ_I3 are sequentially respectively passed through the first interrupt request signal holder 562_1 , the second interrupt request signal holder 562_2 , the fourth interrupt request signal holder 562_4 and the third interrupt request signal holder 562_3 receive.

The first interrupt request signal holder 562_1 gives the first interrupt request signal nIRQ_O1 to the first processor 580_1 immediately because no previous interrupt request signal exists before the first interrupt request signal nIRQ_I1.

The second interrupt request signal holder 562_2 also issues the second interrupt request signal nIRQ_O2 to the second processor 580_2 Immediately because a time interval S1 between the first interrupt request signal nIRQ_I1 and the second interrupt request signal nIRQ_I2 is greater than the time interval limit PS.

The fourth interrupt request signal holder 562_4 Delay the output for the fourth interrupt request signal nIRQ_O4 by a period DL1, since a time interval between the second interrupt request signal nIRQ_I2 and the fourth interrupt request signal nIRQ_I4 is smaller than the time interval threshold PS. The fourth interrupt request signal holder 562_4 then gives the fourth interrupt request signal nIRQ_O4 to the fourth processor 580_4 out.

The third interrupt request signal holder 562_3 delays the output of the third interrupt request signal nIRQ_O3 by a period DL2 after the second interrupt request signal nIRQ_O3 is output, and then outputs the third interrupt request signal nIRQ_O3 to the third processor 580_3 out.

In accordance with at least this exemplary embodiment, inrush surges may occur due to a sudden waking up of the first to fourth processors 580_1 to 580_4 suppressed and / or prevented since the first to fourth processor 580_1 to 580_4 receives the first to fourth interrupt request signals nIRQ_O1 to nIRQ_O4 each at a time interval which is greater than or equal to the time interval threshold PS.

19 FIG. 15 is a diagram illustrating still another exemplary operation of an interrupt request signal propagation circuit for the SOC of FIG 1 illustrated.

19 shows an example in which the first to (m) -th interrupt request signal holder 562_1 to 562_m the interrupt request signal propagation circuit 560 by an interrupt request signal arbiter (in 19 not illustrated) of the interrupt request signal propagation circuit 560 in the SOC 500 is controlled. Thus, the first to (m) th interrupt request signals nIRQ_I1 to nIRQ_Im become the first to (m) th processors 580_1 to 580_m is output as the first to m-th interrupt request signal nIRQ_O1 to nIRQ_Om at time intervals corresponding to the time interval threshold PS, respectively. As in 19 For the sake of simplicity, it is assumed that m is 4.

If the first to (n) th interrupt source 520_1 to 520_n output the first to the (n) -th interrupt INT_R1 to INT_Rn, generates the interrupt controller 540 the first to fourth interrupt request signals nIRQ_I1 to nIRQ_I4 based on the first to (n) th interrupts INT_R1 to INT_Rn. As in 19 1, the first interrupt request signal nIRQ_I1 and the second interrupt request signal nIRQ_I2 are respectively concurrently or concurrently by the first interrupt request signal holder 562_1 and the second interrupt request signal holder 562_2 receive. Then, the fourth interrupt request signal nIRQ_I4 and the third interrupt request signal nIRQ_I3 are respectively sequentially passed through the fourth interrupt request signal holder 562_4 and the third interrupt request signal holder 562_3 receive. Here, it is assumed that a priority of the first interrupt request signal nIRQ_I1 is higher than a priority of the second interrupt request signal nIRQ_I2. Thus, in this example, the first interrupt request signal holder 562_1 the first interrupt request signal nIRQ_O1 to the first processor 580_1 immediately out.

The second interrupt request signal holder 562_2 delays the output of the second interrupt request signal nIRQ_I2 by a period DL1 (for example, by the time interval threshold PS), and then outputs the second interrupt request signal nIRQ_O2 to the second processor 580_2 out.

The fourth interrupt request signal nIRQ_O4 and the third interrupt request signal nIRQ_O3 are applied to the fourth processor 580_4 and the third processor 580_3 each unobserved or output independently of the feed order of the fourth interrupt request signal nIRQ_I4 and the third interrupt request signal nIRQ_I3. Here, it is assumed that a priority of the third interrupt request signal nIRQ_I3 is higher than a priority of the fourth interrupt request signal nIRQ_I4. The third interrupt request signal holder 562_3 delays the output of the third interrupt request signal nIRQ_O3 by a period DL2, and then outputs the third interrupt request signal nIRQ_O3 to the third processor 580_3 out. The fourth interrupt request signal holder 562_4 delays the output of the fourth interrupt request signal nIRQ_O4 by a period DL3, and then outputs the interrupt request signal nIRQ_O4 to the fourth processor 580_4 out.

In accordance with at least this exemplary embodiment, inrush surges may occur due to a sudden waking up of the first to fourth processors 580_1 to 580_4 suppressed and / or prevented since the first to fourth processor 580_1 to 580_4 receive the first to fourth interrupt request signals nIRQ_O1 to nIRQ_O4 at time intervals corresponding to the time interval threshold PS, respectively.

20 FIG. 4 is a block diagram illustrating a multi-core system according to example embodiments; and FIG 21 FIG. 15 is a diagram illustrating an example in which a multi-core system of FIG 20 implemented as a smartphone.

Referring to the 20 and 21 has the multi-core system 600 a first bis (n) -th interrupt source 610_1 to 610_N , an interrupt controller 620 , an interrupt request signal propagation circuit 630 , a multi-core processor 640 , a bus interface or a bus interface 645 , a random access memory (RAM) device 650 , a read only memory (ROM) device 660 , a storage device 670 , a system bus 680 etc. on. Here's the multi-core processor 640 a first to a (m) -th core P1 to Pm. In one example, the multi-processor may be referred to as a dual-core processor if m is 2, it may be referred to as a quad-core processor if m is 4, etc.

As in 21 Illustrated is the multi-core system 600 as a smartphone 700 be implemented. The multi-core system 600 but is not limited to this. For example, the multi-core system may be implemented as an electric device such as a smart TV, a smartpad, a mobile phone, etc. Furthermore, it should be understood that the multi-core system 600 a system having a multi-core processor having a plurality of cores or a system having a plurality of processors each having one or more cores.

The first to the (n) th interrupt source 610_1 to 610_N may each generate and output a first to the (n) th interrupt INT_R1 to TNT_Rn. The first to the (n) th interrupt source 610_1 to 610_N may correspond to components of a system-on chip (SOC) such as a video module, a sound module, a display module, a memory module, a communication module, a camera module, etc. That is, for example, that the first to (n) -th interrupt source 610_1 to 610_N Blocks of intellectual property (IP blocks) can be specific operations for the multi-core system 600 carry out.

The interrupt controller 620 generates a first to (m) -th interrupt request signal nIRQ_I1 to nIRQ_Im based on the first (n) -th interrupt INT_R1 to INT_Rn, which is from the first to the (n) -th interrupt source 610_1 to 610_N be issued. The interrupt request signal propagation circuit 630 controls time intervals between the first to (m) -th interrupt request signal nIRQ_I1 to nIRQ_Im (for example, a time interval between adjacent interrupt request signals) supplied from the interrupt controller 620 so that they are greater than or equal to the time interval limit.

As in 20 3, the first to (m) -th interrupt request signals nIRQ_O1 to nIRQ_Om are respectively applied to the first to (m) th core P1 to Pm of the multi-core processor 640 output. For this operation, this operation indicates the interrupt request signal propagation circuit 630 a first to (m) -th interrupt request signal holder and an interrupt request signal arbiter for controlling the first to (m) -th interrupt request signal holder. Since the interrupt request signal propagation circuit 630 is described in detail above, a double description is omitted below.

The multi-core processor 640 is with other components through a system bus 680 using a bus interface or a bus interface 645 coupled. The multi-core processor 640 is configured to work with the intellectual property blocks (IP blocks) 610_1 to 610_N , the RAM device 650 , the ROM device 660 , the storage device 670 , etc. via a system bus 680 such as an address bus, a control bus, a data bus, etc. to communicate. The storage device 670 For example, a hard disk drive (HDD), a solid state drive (SSD), a redundant array of redundant array disks (RAID), and so on. According to at least some example embodiments, the multi-core processor 640 be coupled to an extended bus or an extended bus such as an aspherical component interconnect bus (aspheric component bus).

Although in 20 not shown, the multi-core system 600 continue at least a non-volatile memory device and / or at least one volatile memory device. For example, the nonvolatile memory device may be an erasable programmable read only memory (EPROM) device, an electrically erasable programmable read only memory (EEPROM) device, a flash memory device. A device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano-floating gate memory ( NFGM = nano floating gate memory) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric write Read-only memory (FRAM = ferroelectric random access memory) device, etc. In addition, the volatile memory device may correspond to a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a DRAM mobile device, etc. *** " ,

As in 20 illustrates the multi-core system 600 a system bus path for transmitting (receiving and transmitting) data and an interrupt path for handling interrupt outputs from the intellectual property blocks (IP) 610_N on. The multi-core processor 640 can perform certain operations on intellectual property blocks (IP) 610_1 to 610_N based on the system bus path. In addition, the multi-core processor 640 Intellectual Property Block (IP) Interrupt Handling Operations 610_1 to 610_N based on the interrupt path. The multi-core system 600 can be implemented through various packages such as Package-on-Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP) ), In Waffle Pack, Die In Wafer Shape, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flat-Pack (TQFP), System In Package (SIP), Multi-Chip Package (MCP), Wafer-Level Fabricated Package ( WFP), Wafer Level Processed Stack Package (WSPO).

Exemplary embodiments may be applied to electrical devices including a plurality of processors (or a multi-core processor). For example, at least some example embodiments may be applied to electrical devices such as mobile phones, smart phones, computers, laptops, workstations, smartpads, security systems, etc.

The foregoing is illustrative of exemplary embodiments and should not be considered as limiting thereto. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept defined in the claims. Accordingly, it should be understood that the foregoing is illustrative of various exemplary embodiments and is not to be considered as limiting the particular example embodiments disclosed herein, and that it is intended that modifications to the disclosed example embodiments and other example embodiments within the the scope of the appended claims are included.

QUOTES INCLUDE IN THE DESCRIPTION

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Cited patent literature

• KR 10-2012-0008822 [0001]

Claims (26)

Method for power control for a one-chip system ( 500 ), the method comprising: controlling an output of at least a first wakeup request signal (nIRQ_1) and a second wakeup request signal (nIRQ_2) such that a time interval (S1) between the output of the first wakeup request signal (nIRQ_1) and the output of the second wakeup request signal (nIRQ_2) is greater than or equal to a time interval threshold (PS), the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) of one of simultaneous and consecutive wakeup request signals (nIRQ_1 , nIRQ_2). The method of claim 1, wherein the first and second wakeup request signals are interrupt request signals (nIRQ_1, nIRQ_2). The method of claim 1, further comprising: comparing a first time difference (S1) between receipt of the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) with the time interval limit value (PS); and where the output of at least one of the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) is controlled based on the comparison between the first time difference (S1) and the time interval limit value (PS). The method of claim 3, wherein the controlling comprises: delaying the output of at least one of the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) if the first time difference (S1) is less than the time interval limit value (PS). The method of claim 3, wherein the controlling comprises: outputting the first and second wakeup request signals (nIRQ_1, nIRQ_2) without additional or intended delay if the first time difference (S1) is greater than or equal to the time interval limit value (PS). Method for power control for a one-chip system ( 500 ), the method comprising: comparing a first priority of a first wakeup request signal (nIRQ_1) with a second priority of a second wakeup request signal (nIRQ_2); and controlling an output of at least one of the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) based on the comparison between the first priority and the second priority such that a time difference (S1) between the output of the first Wakeup request signal (nIRQ_1) and the output of the second wakeup request signal (nIRQ_2) is greater than or equal to a time interval limit value (PS). The method of claim 6, wherein the first and second wakeup request signals are interrupt request signals (nIRQ_1, nIRQ_2). The method of claim 6, wherein the controlling comprises: delaying the output of at least one of the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) based on the comparison. The method of claim 8, wherein the first priority is greater than the second priority and wherein the delaying comprises: delaying the output of the second wakeup request signal (nIRQ_2). The method of claim 8, wherein the first wakeup request signal (nIRQ_1) is received prior to the second wakeup request signal (nIRQ_2), and wherein delaying comprises delaying the output of the first wakeup request signal (nIRQ_1). The method of claim 6, wherein the first and second wakeup request signals (nIRQ_1, nIRQ_2) are one of consecutive and concurrent wakeup request signals (nIRQ_1, nIRQ_2). The method of claim 6, wherein the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) are connected to functional blocks in an inactive state, and wherein the controlling comprises: outputting wake-up request signals connected to function blocks in an active state without delay. Method for power control for a one-chip system ( 500 ), the method comprising: controlling an output of at least one of a first wake-up request signal (nIRQ_1) to a first processor ( 580_1 ) in an inactive state and a second wake-up request signal (nIRQ_2) to a second processor ( 580_2 ) in the inactive state such that a time interval between the output of the first wake-up request signal (nIRQ_1) to the first processor ( 580_1 ) and the output of the second Wake-up request signal (nIRQ_2) to the second processor ( 580_2 ) is greater than or equal to a time interval threshold (PS), wherein the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) are one of simultaneous and consecutive wakeup request signals (nIRQ_1, nIRQ_2). The method of claim 13, wherein the first and second wakeup request signals are interrupt request signals (nIRQ_1, nIRQ_2). The method of claim 13, further comprising: comparing a first time difference (S1) between receipt of the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) with a time interval limit value (PS); and wherein the output of at least one of the first wakeup request signal (nIRQ_1) to the first processor ( 580_1 ) and the second wakeup request signal (nIRQ_2) to the second processor ( 580_2 ) is controlled based on the comparison between the first time difference (S1) and the time interval threshold (PS). The method of claim 15, wherein the controlling comprises: delaying the output of at least one of the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) if the first time difference (S1) is less than the time interval limit value (PS). The method of claim 15, wherein the controlling comprises: outputting the first and second wakeup request signals (nIRQ_1, nIRQ_2) without delay when the first time difference (S1) is greater than or equal to the time interval limit value (PS). The method of claim 13, further comprising: controlling an output of a third wakeup request signal (nIRQ_3) to a third processor ( 580_3 ) in an inactive state such that a time interval between the output of the second wake-up request signal (nIRQ_2) to the second processor ( 580_2 ) and the output of the third wake-up request signal (nIRQ_3) to the third processor ( 580_3 ) is greater than or equal to the time interval threshold (PS), the second wakeup request signal (nIRQ_2) and the third wakeup request signal (nIRQ_3) being one of simultaneous and consecutive wakeup signals (nIRQ_2, nIRQ_3). The method of claim 13, wherein the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) are simultaneous wakeup request signals (nIRQ_1, nIRQ_2), and wherein the controlling comprises: delaying the output of at least one of the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) based on priorities associated with each of the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2). One-chip system ( 500 ), comprising: a wake-up request signal propagation circuit ( 100 . 560 ) configured to control an output of at least one of a first wakeup request signal (nIRQ_1) to a first function block and a second wakeup request signal (nIRQ_2) to a second function block such that a time interval between the output of the first wakeup request signal Request signal (nIRQ_1) to the first function block and the output of the second wakeup request signal (nIRQ_2) to the second function block is greater than or equal to a time interval limit (PS), the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) are one of simultaneous and consecutive wake-up request signals (nIRQ_1, nIRQ_2). One-chip system ( 500 ) according to claim 20, wherein said first and second wake-up request signals are interrupt request signals (nIRQ_1, nIRQ_2). One-chip system ( 500 ) according to claim 20, wherein the wake-up request signal propagation circuit ( 100 . 560 ) Comprises: an arbiter ( 140 ) configured to compare a first time difference (S1) between the reception of the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) with the time interval limit value (PS), wherein the arbiter ( 140 ) is further configured to generate a plurality of output acknowledge signals (ASi ACK) based on the comparison; and wherein the wake-up request signal propagation circuit ( 100 . 560 ) is configured to control the output of at least one of the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) based on the plurality of output acknowledge signals (ASi ACK). One-chip system ( 500 ) according to claim 22, wherein the wake-up request signal propagation circuit ( 100 . 560 ) further comprises: a first interrupt request signal holding circuit ( 120_1 ) configured to store the first wakeup request signal (nIRQ_1), the first interrupt request signal hold circuit (12) 120_1 ) is further configured to output the first wake-up request signal (nIRQ_1) in response to a first one of the plurality of output acknowledge signals (ASi ACK); and a second interrupt request signal holding circuit ( 120_2 ) configured to store the second wakeup request signal (nIRQ_2), the second interrupt request signal hold circuit (12) 1202 ) is further configured to output the second wake-up request signal (nIRQ_2) in response to a second one of the plurality of output acknowledge signals (ASi ACK). One-chip system ( 500 ) according to claim 22, wherein the wake-up request signal propagation circuit ( 100 . 560 ) is configured to delay the output of at least one of the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) when the first time difference (S1) is less than the time interval limit value (PS). One-chip system ( 500 ) according to claim 20, wherein the wake-up request signal propagation circuit ( 100 . 560 ) Comprises: a first level detector (LD1) configured to detect the first wakeup request signal (nIRQ_1); a second level detector (LD2) configured to detect the second wakeup request signal (nIRQ_2); and a microcontroller configured to control the output of at least one of the first wakeup request signal (nIRQ_1) to the first functional block and the second wakeup request signal (nIRQ_2) to the second functional block. A multi-core system comprising: a plurality of wake-up signal sources configured to generate at least a first and a second wake-up signal; a wake-up signal controller configured to generate at least first and second wake-up request signals (nIRQ_1, nIRQ_2) based on the first and second wake-up signals; a multi-core processor having at least a first core and a second core, wherein the first core is configured to receive the first wakeup request signal (nIRQ_1), and wherein the second core is configured to generate the second wakeup request signal (nIRQ_1); Request signal (nIRQ_2) to receive; a wake-up request signal propagation circuit ( 100 . 560 ) configured to control the output of at least one of the first wakeup request signal (nIRQ_1) to the first core and the second wakeup request signal (nIRQ_2) to the second core such that a time interval between the output of the first wakeup request signal Request signal (nIRQ_1) and the output of the second wakeup request signal (nIRQ_2) is greater than or equal to a time interval limit value (PS), the first wakeup request signal (nIRQ_1) and the second wakeup request signal (nIRQ_2) being one of simultaneous and consecutive Wake-up request signals (nIRQ_1, nIRQ_2); and at least one memory device configured to couple with the plurality of wake-up signal sources and the multi-core processor via a system bus.

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