CN101673221B

CN101673221B - Interrupt processing method of embedded on-chip multiprocessor

Info

Publication number: CN101673221B
Application number: CN 200910197529
Authority: CN
Inventors: 凌毅; 陈芸
Original assignee: Tongji University
Current assignee: Tongji University
Priority date: 2009-10-22
Filing date: 2009-10-22
Publication date: 2013-02-13
Anticipated expiration: 2029-10-22
Also published as: CN101673221A

Abstract

The invention belongs to the technical field of on-chip multiprocessors, in particular relating to an interrupt processing method of an embedded on-chip multiprocessor. On the basis of keeping the original structure of each processor, by designing a multiprocessor interrupt dispatcher IP kernel meeting the on-chip bus standard, the invention completes the dispatching for the external interrupt and simultaneously realizes the interrupt generated by the on-chip multiprocessor, thereby achieving the internuclear interrupt communication effect. The invention realizes the centralized dispatching for multiple interrupts inside and outside the chip, comprehensively allocates the interrupts according to the usage rate detection for each CPU while considering the real-time performance, and achieves the effect of balancing system loads.

Description

A kind of interruption processing method of embedded on-chip multiprocessor

Technical field

The invention belongs to the on-chip multi-processor technical field, be specifically related to a kind of interruption processing method of embedded on-chip multiprocessor.

Background technology

In uniprocessor; interruption is that CPU is in operation present procedure process; when some anomalous event or certain external request in house software interrupt request occurring; so that CPU temporarily stops the program to carry out; forward to carry out and process handling procedure unusual or that external unit service in house software interrupts; move complete rear CPU and return again the program place that temporarily stops, continuing to carry out original program.When the CPU peripheral hardware was more, a certain moment may produce a large amount of interruptions, so that CPU is in interruption status for a long time, so that some interrupt events can not get processing, had reduced real-time and the overall performance of system.

The development of multiprocessor technology can address the above problem, and this has just required a rational multiprocessor interruptable controller.If all interruptions are placed on the same processor core process, the problems referred to above can occur equally.

Programmable interrupt controller (APIC) by the advanced person who is used for multi-purpose computer of INTEL Corp. exploitation, cooperate outside 8259A collaborative work, can reach and process the external interrupt that is received on the disconnected input pin therein by processor and the interruption that is produced by software, in multicomputer system, it communicates with the I/O APIC chip of outside, and these interrupt distribution are processed to the processor on the system bus, revise dynamically simultaneously the priority arbitration of each local APIC by bus arbitration, to keep its harmony.

Be in the patent " polycaryon processor interruption load balancing method and apparatus " of CN200810135521 at application number, processor core is divided into two groups of respectively special disposal process and interruptions dynamically, the algorithm of its dynamic assignment processor core has solved interruption load balancing to a certain extent, but take the processor core that marks off specially some as cost, when the processor core number is few, very calculate.

Multiprocessor not only is used for multi-purpose computer, server, and embedded on-chip multiprocessor also fast development gets up, and develops to fields such as telecommunications, multimedia, Industry Control, robotization, smart machines gradually.Yet be applied to the interruption processing method blank out almost also of the on-chip multi-processor of built-in field, if as general multiprocessor computer, realize interrupting original architecture that processing requirements is revised each processor core, greatly increase time and the cost of embedded on-chip multiprocessor system development.

Summary of the invention

The object of the invention is to propose a kind of interruption processing method of embedded on-chip multiprocessor.

The interruption processing method of the embedded on-chip multiprocessor that the present invention proposes comprises the multiprocessor interrupt moderation device based on on-chip bus, the processing of external interrupt, internuclear interruption processing, and is specific as follows:

(1) based on the multiprocessor interrupt schedule device of on-chip bus

Meet multiprocessor interrupt schedule device (Multi-Processor InterruptScheduler, the MPIS) IP kernel of on-chip bus interface standard to the implement of interruption function centralized scheduling by design.This multiprocessor interrupt schedule device links to each other with on-chip bus, realize the interrupt communication information of communicating by letter and accepting to send from processor core with each processor core, multiprocessor interrupt schedule device input end connects exterior I/O device interrupt source interface, accept the external interrupt signal source, the N of multiprocessor interrupt schedule device (for the number of processor core) output terminal look-at-me is connected to respectively not maskable (or having enabled) look-at-me source port of the original outside of each processor CPU.Realize processing and the internuclear interrupt communication of external interrupt are processed by this multiprocessor interrupt schedule device;

(2) processing of external interrupt

Record respectively outside maskable and not the maskable interrupt source signal in the corresponding registers of multiprocessor interrupt schedule device, program give each interrupt source priority (on the whole internuclear interrupt communication priority be higher than the outside not maskable interrupt being higher than maskable interrupts), the situation that enables in programming maskable interrupts source, judged to dispatch in have no progeny, the operation conditions of checking each CPU (comprises the program information that moving and the utilization rate of CPU, be sent to the MPIS corresponding registers by each CPU, operating system is finished), the priority ratio that interrupts first moving hangs down the CPU of task, the lower CPU of interrupts of CPU utilization rate when task priority is identical, i.e. taking into account system load balancing when having considered system real time;

(3) internuclear interrupt communication is processed

Internuclear interrupt communication sends interrupting information to multiprocessor interrupt schedule device and record by each CPU by on-chip bus, then multiprocessor interrupt schedule device sends interrupting information according to log file to being interrupted CPU, this CPU in have no progeny and read the corresponding CPU interrupt schedule register of MPIS, do corresponding interrupt service routine or obtaining communication data.

The beneficial effect that the present invention has is: the present invention is a kind of interruption processing method of embedded on-chip multiprocessor, the processing of by rationally effective realization of MPIS external interrupt being communicated by letter with internal interrupt on the basis that does not change the former architecture of processor core, accelerate the speed of embedded on-chip multiprocessor system development, taking into account system load balancing when having considered system real time.

Description of drawings

Fig. 1 is the annexation schematic diagram of MPIS in the on-chip multi-processor system.

Fig. 2 is the inner structure block diagram of MPIS.

Fig. 3 is the implementation process schematic diagram that the present invention solves external interrupt.

Fig. 4 is the implementation process schematic diagram that the present invention solves internuclear interrupt communication.

Embodiment

Below in conjunction with description of drawings method of the present invention.

Embodiment 1:

The interruption processing method of a kind of embedded on-chip multiprocessor that the present invention proposes comprises following process:

1) annexation of MPIS in the on-chip multi-processor system.

Here take 4 core processors as example, as shown in Figure 1, MPIS adds this on-chip multi-processor system to the form of an IP kernel, MPIS is to be connected to from port on the on-chip bus unified the system, the input end of this MPIS is that the I/O equipment interface produces the external interrupt signal source, comprises maskable and maskable interrupt source signal not.MPIS also produces interrupt signal output: INT0, INT1, INT2, INT3 in addition, connects respectively not maskable external interrupt (or the having enabled) interface that CPU0, CPU1, CPU2, CPU3 carry originally.By this MPIS outside interrupt source signal and the centralized management of internal interrupt communication signal source are dispatched.

2) MPIS internal truss frame structure.

Here case of external maskable interrupts signal is 64 road INTM[63:0], outside not maskable look-at-me is 32 road INTUM[31:0], internal interrupt signal of communication number is 8, the on-chip bus signal comprises: clk, chipselect, address, read, readdata, write, writedata etc., as shown in Figure 2.Register file among the MPIS comprises: internuclear interrupt communication register, outside be maskable interrupt register, outside maskable interrupts register, maskable interrupts enable register, CPU interrupt schedule register group, CPU running status register group, CPU OIER etc. not.

Internuclear interrupt communication register is used for storage from the internuclear interrupt communication signal of CPU, 8 internal interrupt signals are arranged here, be defined as 32 bit register variable CIR, i.e. 84 register, wherein each 4 represent an internuclear interruption, its 0-1 position represent interrupted 4 CPUID number: 00 represents CPU0,01 represents CPU1,10 and represents CPU2,11 and represent CPU3, and 2 keep zero clearings, and 3 is 1 or 0 to represent this look-at-me and whether produce.

Outside not maskable interrupt register is defined as 32 bit register variable OUMR, and its each is 1 or 0 to represent this look-at-me and whether produce, and in like manner defining outside maskable interrupts register is 64 bit register variable OMR.

The maskable interrupts enable register is used for identifying the situation that enables of 64 outside maskable interrupts signal sources, is defined as 64 bit register variable MER, each be the corresponding outside maskable interrupts signal source of 1 or 0 representative shielding whether.

CPU interrupt schedule register group has 4 CPU interrupt schedule registers here, and the interrupt schedule of depositing respectively each CPU is situation as a result.Here define 48 register variable: PISR0, PISR1, PISR2, PISR3 deposit respectively the interrupt schedule result of CPU0, CPU1, CPU2, CPU3.Table 1 is listed the field description of PISR0:

Table 1PISR0 field description

The position

Describe

0-5	Interrupt schedule result's interruption ID number (priority)
		6-7	Judge this register 0-5 position record interruption ID number representative be which kind of interrupt type 00: internal interrupt communication 01: outside not maskable interrupts 10: outside maskable interrupts 11: without interrupting

CPU running status register group has 4 CPU running status registers, the current running status of depositing respectively each CPU here.Here define 4 16 register variable: PRSR0, PRSR1, PRSR2, PRSR3 deposit respectively the current running status of CPU0, CPU1, CPU2, CPU3.Table 2 is listed the field description of PRSR0.

Table 2PRSR0 field description

The position	Describe
		0-5	The priority of the ID of the interruption that CPU0 is moving number (priority) or task
6-7	Judge that the 0-5 of this register is interrupt type or the task 00 of record: internal interrupt communication 01: outside not maskable interrupts 10: outside maskable interrupts 11: task
		8-14	The current C PU utilization rate (0-100) of CPU0
15	Keep zero clearing

The interruption that the CPU OIER is used for identifying each CPU enables all interrupt sources shielding situations of situation and outside maskable interrupts.Utilize this register can allow each CPU realize random interrupt switch under the control of program, close CPU operation task program of interruption, the CPU that opens interruption is operation task program and accept interruption simultaneously.Here define the 16 register variable PIER that are, its 0-3 position is 1 or 0 to represent respectively CPU0, CPU1, CPU2, CPU3 and interrupt whether enabling.4-14 is for keeping zero clearing.15 be 1 or 0 representative whole outside maskable interrupts source shielding whether.

The interrupt logic of MPIS is made corresponding processing according to the situation of register file, and revises register file, jointly finishes the interruption of on-chip multi-processor system in conjunction with CPU and processes.

3) external interrupt is processed.

MPIS to the processing procedure of outside interrupt source signal as shown in Figure 3, when outside maskable with when the maskable look-at-me produces, MPIS is deposited with OMR with signal, corresponding positions among the OUMR, interrupt logic is found out according to MER and is needed interrupt source to be processed, check PRSR0, PRSR1, PRSR2, the corresponding positions of PRSR3 is found out the CPU of operation lowest priority task, if move more than one of the CPU of minimum equal priority task, find out the minimum CPU of current C PU utilization rate of each CPU, PISR corresponding to this CPU that finds out is revised as needs interrupt source information to be processed at first in the need interrupt source to be processed that correspondence finds out.If outage service routine all on the CPU, rule is the same.When MPIS has determined to be interrupted CPU, send INT0, INT1, INT2, INT3 look-at-me to each CPU, have no progeny during each CPU produces and read each self-corresponding PISR register value by on-chip bus, according to this register value interrupt service routine is carried out in the entry address that CPU jumps to corresponding registered service routine.

4) internuclear interrupt communication is processed.

MPIS to the processing procedure of internuclear communication disruption signal source as shown in Figure 4, produce internuclear interrupting information by CPU, the ID that comprises interrupted CPU and internuclear communication disruption, revise the corresponding field of CIR by on-chip bus, MPIS checks and will be interrupted PRSR corresponding to CPU, judge priority and CPU usage determine whether revise the PISR register of wanting interrupted CPU, produce look-at-me INTn, have no progeny among the CPU and read the PISR of this CPU by on-chip bus, according to this register value internuclear interrupt service routine or obtaining communication data are carried out in the entry address that CPU jumps to corresponding registered service routine.

Claims

1. the interruption processing method of an embedded on-chip multiprocessor is characterized in that comprising based on the processing of the multiprocessor interrupt schedule device of on-chip bus, the processing of external interrupt, internuclear interruption and processes, and concrete steps are as follows:

(1) based on the processing of the multiprocessor interrupt schedule device of on-chip bus

Meet the multiprocessor interrupt schedule device IP kernel of on-chip bus interface standard to the implement of interruption function centralized scheduling by design; This multiprocessor interrupt schedule device links to each other with on-chip bus, realize the interrupt communication information of communicating by letter and accepting to send from processor core with each processor core, multiprocessor interrupt schedule device input end connects exterior I/O device interrupt source interface, accept the external interrupt signal source, N output terminal look-at-me of multiprocessor interrupt schedule device is connected to respectively not maskable interrupt source signal port of the original outside of each processor CPU; Realize processing and the internuclear interrupt communication of external interrupt are processed by this multiprocessor interrupt schedule device;

(2) processing of external interrupt

Record respectively outside maskable and not the maskable interrupt source signal in the corresponding registers of multiprocessor interrupt schedule device, program is given each interrupt source priority, namely on the whole internuclear interrupt communication priority be higher than the outside not maskable interrupt being higher than maskable interrupts, the situation that enables in programming maskable interrupts source, judged to dispatch in have no progeny, check the operation conditions of each CPU, comprise the program information that moving and the utilization rate of CPU, be sent to multiprocessor interrupt schedule device corresponding registers by each CPU, operating system is finished, the priority ratio that interrupts first moving hangs down the CPU of task, the lower CPU of interrupts of CPU utilization rate when task priority is identical, i.e. taking into account system load balancing when having considered system real time;

(3) internuclear interrupt communication is processed

Internuclear interrupt communication sends interrupting information to multiprocessor interrupt schedule device and record by each CPU by on-chip bus, then multiprocessor interrupt schedule device sends interrupting information according to log file to being interrupted CPU, this CPU in have no progeny and read the corresponding CPU interrupt schedule of multiprocessor interrupt schedule device register, do corresponding interrupt service routine or obtaining communication data.