CN103019848B - Method for realizing peripheral component interconnect (PCI) bus non-vector interrupt - Google Patents
Method for realizing peripheral component interconnect (PCI) bus non-vector interrupt Download PDFInfo
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- CN103019848B CN103019848B CN201210572407.2A CN201210572407A CN103019848B CN 103019848 B CN103019848 B CN 103019848B CN 201210572407 A CN201210572407 A CN 201210572407A CN 103019848 B CN103019848 B CN 103019848B
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Abstract
The invention discloses a method for realizing peripheral component interconnect (PCI) bus non-vector interrupt, which belongs to the technical field of PCI buses. The method comprises the following steps: 1, an interrupt enable register, an interrupt status register and an interrupt clear register are set up in a control platform; 2, the control platform sets designated locations in the interrupt enable register according to enable signals; 3, the control platform detects interrupt events which are generated by an interrupt source No. i and detects an ith set location of the interrupt enable register at the same time, so that the ith location of the interrupt enable register is set; after one or more than one bits of the interrupt enable register are set, interrupt request signals can be generated; 4, a PCI system has an interrupt request zone bit and receives the interrupt request signal, if the interrupt request zone bit is hollow, the interrupt request zone bit is set, the interrupt is responded, and an interrupt program is operated; and an interrupt service routine calls different processing programs according to different interrupt sources. The method is used for the interrupt control of the PCI system.
Description
Technical field
The invention belongs to pci bus technical field.
Background technology
Along with the complicacy of tested system day by day improves, system also constantly improves for the requirement of pci bus board function, and pci bus is now to the development of cpci bus and PXI bus, and the function of single PXI board also gets more and more, becomes increasingly complex.
Single PCI board is when facing complicated tested system, because the interrupt event of system increases, require that board should have the ability processed more multiple interrupt event, but existing PCI board can only provide 4 interrupt request ends such as INTA#, INTB#, INTC#, INTD# for each system, for the tested system of function complexity, this can not meet the application being responsible for functional cards at present far away.
Summary of the invention
In view of this, the invention provides a kind of pci bus non vector interrupt implementation method, adopt the method can break through existing pci bus to each board device interrupt source number quantitative limitation, several times improve the quantity of the interrupt source of existing PCI board equipment, meet multifunction board card apparatus based on pci bus to the demand of interrupt source quantitative aspects.
Based on above-mentioned purpose technical scheme of the present invention be:
A kind of pci bus non vector interrupt implementation method, comprises the steps:
Step 1, parametric controller create OIER, interrupt status register, interrupt clear register; Parametric controller has enable signal input end and interrupts application signal output part; Interrupt the interrupt request end that application signal output part connects pci system; Pci system communicates with parametric controller, reads or set the OIER in parametric controller, interrupt status register, interrupt clear register;
For n interrupt source:
OIER comprises n position, each corresponding interrupt source, when setting the i-th position, position of OIER, represents that interrupt source i# is enabled; I-th when not being set, represents that interrupt source i# is prohibited, wherein 1≤i≤n;
Interrupt status register comprises n position, each corresponding interrupt source, and when setting the i-th position, position of interrupt status register, interrupt event occurs mark interrupt source i#, otherwise mark interrupt source i# occurs without interrupt event or is prohibited;
Interrupt clear register comprises n position, each corresponding interrupt source, when set, removes the set of interrupt status register i-th for i-th of setting interrupt clear register;
Step 2, parametric controller receive the enable signal of user's input by enable signal input end and carry out set according to enable signal to specific bit in OIER;
Step 3, parametric controller detect that interrupt source i# produces interrupt event, detect that i-th of OIER is set, then by the i-th position, position of interrupt status register simultaneously; Every logic rules with setting of interrupt status register are carried out computing and are produced interruption application signal by parametric controller, and interruption application signal, by interrupting the output of application signal output part, delivers to the interrupt request end of pci system;
The logic rules wherein set are: more than 1 of interrupt status register or 1 is set i.e. generation and interrupts application signal;
Have in step 4, pci system and interrupt application zone bit, pci system receives and interrupts application signal, detects and interrupts application zone bit, is set if interrupt application flag, then continue to detect and interrupt application flag, until it is empty for interrupting application flag; If it is empty for interrupting application zone bit, then interruption application zone bit is carried out set, response is interrupted and enters interrupt service routine;
The workflow of interrupt service routine is:
First interrupt status register is read, obtain the sequence number of the position be set in interrupt status register, according to sequence number, set operation is carried out to the position in interrupt clear register, and call the handling procedure of interrupt source corresponding to sequence number, after handling procedure calls end, interruption application zone bit is emptied, exits interrupt service routine.
Further, the handling procedure calling interrupt source corresponding to sequence number is: when multiple positions of interrupt status register are set, and interrupt service routine successively calls the handling procedure of described multiple different interrupt source according to the interrupt priority level of setting.。
Beneficial effect:
1, the present invention comprises OIER, interrupt status register, the controlling and the register identified for interrupting of interrupt clear register by creating, and achieves the management to more Multiple Interrupt Sources and identification.Each interrupt source in this method all can be produced interrupt trigger signal and be interrupted to pci system application by interrupt request end, the method makes PCI board can respond more interrupt event to go forward side by side row relax, breach existing pci bus to each board device interrupt source number quantitative limitation, several times improve the quantity of the interrupt source of existing PCI board equipment, meet multifunction board card apparatus based on pci bus to the demand of interrupt source quantitative aspects;
2, a kind of pci bus non vector interrupt implementation method provided by the present invention, carry out register and sort out setting, rationally be provided with OIER, interrupt status register, interrupt clear register three class register, this kind arrange not only ensure that interrupt service routine can complete realization to the processing capacity of interrupt event, and enormously simplify interrupt service routine, make pci system realize on its basis for the function of multiple interrupt event process complete, program be more succinct, run more smooth.
Accompanying drawing explanation
Fig. 1 is parametric controller design diagram of the present invention;
Fig. 2 is OIER structural representation of the present invention;
Fig. 3 is interrupt status register structural representation of the present invention;
Fig. 4 is interrupt clear register structural representation of the present invention;
Fig. 5 is that application logical organization schematic diagram is interrupted in the present invention;
Fig. 6 is interrupt service routine schematic flow sheet of the present invention.
Embodiment
To develop simultaneously embodiment below in conjunction with accompanying drawing, describe the present invention.
The pci bus non vector interrupt implementation method that the present embodiment proposes is specially:
Step 1, as shown in Figure 1, creates OIER, interrupt status register, interrupt clear register at parametric controller; Parametric controller has enable signal input end and interrupts application signal output part; Interrupt the interrupt request end that application signal output part connects pci system; Pci system is read or set the OIER in parametric controller, interrupt status register, interrupt clear register by bus;
For n interrupt source:
As shown in Figure 2, OIER comprises n position to OIER structure, each corresponding interrupt source, and when setting the i-th position, position of OIER, mark interrupt source i# is enabled; I-th when not being set, mark interrupt source i# is prohibited, wherein 1≤i≤n.
Interrupt status register structure as shown in Figure 3, interrupt status register comprises n position, and each corresponding interrupt source, when setting the i-th position, position of interrupt status register, there is interrupt event in mark interrupt source i#, otherwise mark interrupt source i# occurs without interrupt event or is prohibited.Every logic rules with setting of interrupt status register are carried out computing and are exported interrupt request singal, by the output of interruption application signal output part.
As shown in Figure 4, interrupt clear register comprises n position to interrupt clear register structure, and each corresponding interrupt source, set i-th of interrupt clear register when set, parametric controller removes the set of interrupt status register i-th.
Visible, the present invention creates register according to register functions, creates OIER, interrupt status register, interrupt clear register three class register altogether.
Step 2, parametric controller receive the enable signal of user's input by enable signal input end, and parametric controller carries out set according to enable signal to the position of some in OIER; Namely the interrupt source that corresponding position is set be enabled.
Step 3, parametric controller detect that interrupt source i# produces interrupt event, detect that i-th of OIER is set, then by the i-th position, position of interrupt status register simultaneously.
Every logic rules with setting of interrupt status register are carried out computing and are produced interruption application signal by parametric controller, and interruption application signal, by interrupting the output of application signal output part, delivers to the interrupt request end of pci system.
The logic rules of setting are: more than 1 of interrupt status register or 1 is set i.e. generation and interrupts application signal; Then for n interrupt source, each interrupt source produces interrupt event all can produce interruption application signal by the logical operation of this setting.
Interruption application logical organization in the present embodiment as shown in Figure 5.
Have in step 4, pci system and interrupt application zone bit, pci system receives and interrupts application signal, detect and interrupt application zone bit, if interrupt application flag to be set, illustrate that interrupt service routine carries out, then continue to detect and interrupt application flag, until detect that interruption application flag is for empty; When interrupting application zone bit and being empty, then interruption application zone bit is carried out set, response is interrupted and enters interrupt service routine, and interrupt service routine runs according to the workflow of setting.
As shown in Figure 6, the workflow of interrupt service routine is:
First interrupt status register is read, obtain the sequence number of the position be set in interrupt status register, according to sequence number, set operation is carried out to the position in interrupt clear register, and call the handling procedure of interrupt source corresponding to sequence number, after handling procedure calls end, interruption application zone bit is emptied, exits interrupt service routine.
When multiple positions of interrupt status register are set, then interrupt service routine can get multiple sequence number, namely corresponding multiple different interrupt source produces interrupt event simultaneously, and interrupt service routine successively calls the handling procedure of described multiple different interrupt source according to the interrupt priority level of setting; After handling procedure calls end, interruption application zone bit is emptied, exits interrupt service routine.
As can be seen from the workflow of interrupt service routine, because the present invention creates register according to function, in interrupt service routine, can be completed the corresponding function of program by the corresponding positions identified or operate each register, this enormously simplify program circuit on the basis of complete function ensureing interrupt service routine.
Design according to the present invention, for 32 pci systems, 32 bit register structures can be created, OIER, interrupt status register, interrupt clear register are all set to 32, corresponding 32 interrupt sources of each interrupt request end that pci bus system then can be made to support, namely the interrupt source easily extensible that 4 interrupt request ends of pci bus system support are corresponding is 128, the interrupt source quantity that very big pci bus system is supported.
In the present embodiment, FPGA can be used as parametric controller, FPGA creates memory block as OIER, interrupt status register, interrupt clear register, and outside input and interrupt trigger signal can be received, system carries out communication by bus and FPGA, to read the position of the respective storage areas on FPGA.
In sum, these are only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (2)
1. a pci bus non vector interrupt implementation method, is characterized in that, comprises the steps:
Step 1, parametric controller create OIER, interrupt status register, interrupt clear register; Described parametric controller has enable signal input end and interrupts application signal output part; Interrupt the interrupt request end that application signal output part connects pci system; Pci system communicates with parametric controller, reads or set the OIER in parametric controller, interrupt status register, interrupt clear register;
For n interrupt source:
Described OIER comprises n position, each corresponding interrupt source, when setting the i-th position, position of OIER, represents that interrupt source i# is enabled; I-th when not being set, represents that interrupt source i# is prohibited, wherein 1≤i≤n;
Described interrupt status register comprises n position, each corresponding interrupt source, and when setting the i-th position, position of interrupt status register, interrupt event occurs mark interrupt source i#, otherwise mark interrupt source i# occurs without interrupt event or is prohibited;
Described interrupt clear register comprises n position, each corresponding interrupt source, when set, removes the set of interrupt status register i-th for i-th of setting interrupt clear register;
Step 2, parametric controller receive the enable signal of user's input by enable signal input end, carry out set according to enable signal to specific bit in OIER;
Step 3, parametric controller detect that interrupt source i# produces interrupt event, detect that i-th of OIER is set, then by the i-th position, position of interrupt status register simultaneously; Every logic rules with setting of interrupt status register are carried out computing and are produced interruption application signal by parametric controller, and interruption application signal, by interrupting the output of application signal output part, delivers to the interrupt request end of pci system;
The logic rules of described setting are: more than 1 of interrupt status register or 1 is set i.e. generation and interrupts application signal;
Have in step 4, pci system and interrupt application flag, pci system receives and interrupts application signal, detects and interrupts application flag, is set if interrupt application flag, then continue to detect and interrupt application flag, until it is empty for interrupting application flag; If it is empty for interrupting application flag, then interruption application flag is carried out set, response is interrupted and enters interrupt service routine;
The workflow of interrupt service routine is:
First interrupt status register is read, obtain the sequence number of the position be set in interrupt status register, according to sequence number, set operation is carried out to the position in interrupt clear register, and call the handling procedure of interrupt source corresponding to sequence number, after handling procedure calls end, interruption application flag is emptied, exits interrupt service routine.
2. a kind of pci bus non vector interrupt implementation method as claimed in claim 1, it is characterized in that, the described handling procedure calling interrupt source corresponding to sequence number is: when multiple positions of interrupt status register are set, and interrupt service routine successively calls the handling procedure of multiple different described interrupt source according to the interrupt priority level of setting.
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| CN104679687B (en) * | 2014-12-19 | 2018-04-20 | 杭州华为数字技术有限公司 | A kind of method and device for identifying interrupt source |
| CN107085532B (en) * | 2017-03-21 | 2019-12-13 | 东软集团股份有限公司 | task monitoring method and device |
| CN109343950B (en) * | 2018-10-16 | 2021-06-08 | 南京国电南自维美德自动化有限公司 | General interrupt processing method suitable for Xilinx soft-core processor |
| CN111081295A (en) * | 2018-10-22 | 2020-04-28 | 华邦电子股份有限公司 | Memory device and interrupt processing method thereof |
| CN111143047A (en) * | 2019-12-24 | 2020-05-12 | 北京无线电测量研究所 | Timing and random double-interrupt processing system and method |
| CN112069020B (en) * | 2020-08-13 | 2023-09-15 | 中国航空无线电电子研究所 | Embedded operating system-based on-board avionics software fault monitoring system |
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| CN101931580A (en) * | 2009-12-22 | 2010-12-29 | 中国航空工业集团公司第六三一研究所 | System on chip adopting ARINC 659 rear panel data bus interface chip |
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| CN101211323B (en) * | 2006-12-28 | 2011-06-22 | 联想(北京)有限公司 | Hardware interruption processing method and processing unit |
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| US5812858A (en) * | 1994-09-16 | 1998-09-22 | Cirrus Logic, Inc. | Method and apparatus for providing register and interrupt compatibility between non-identical integrated circuits |
| US6643724B2 (en) * | 2000-12-27 | 2003-11-04 | International Business Machines Corporation | Method and apparatus for interrupt routing of PCI adapters via device address mapping |
| CN101931580A (en) * | 2009-12-22 | 2010-12-29 | 中国航空工业集团公司第六三一研究所 | System on chip adopting ARINC 659 rear panel data bus interface chip |
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