KR101836578B1 - Semiconductor devices and methods of manufacture thereof - Google Patents

Abstract

The SRAM cell includes a first vertical pull-up transistor stacked on a first vertical pull-down transistor and a second vertical pull-up transistor stacked on a second vertical pull-down transistor. The gates of the first vertical pull-up transistor and the second vertical pull-down transistor are coupled by a first via while the gates of the second vertical pull-up transistor and the second vertical pull-down transistor are coupled by a second via . The gates of the first vertical pull-up transistor and the second vertical pass-rate transistor are coupled by the first conductive traces while the gates of the second vertical pull-up transistor and the second vertical pass- Lt; / RTI > The gate of the second vertical pull-up transistor is coupled to the second conductive trace by a third via while the gate of the second vertical pull-up transistor is coupled to the first conductive trace by a fourth via.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device,

The present invention relates to a semiconductor device and a manufacturing method thereof.

The semiconductor industry continues to improve the integration density of various integrated circuits by a continuous reduction of the minimum feature size, which means that more electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) .

In addition, static random access memory (SRAM) cells are commonly used in integrated circuits. An SRAM cell has an advantageous feature of retaining data without the need for regeneration. As the integration density of the integrated circuit is improved, it is desired to reduce the footprint of the SRAM cell and consequently to increase the integration density of the SRAM cell (for example, to increase the number of SRAM cells per unit area ) Demand is increasing.

According to various embodiments presented herein, a semiconductor device includes a first vertical source, a first vertical channel on the first vertical source, a first vertical drain on the first vertical channel, Down transistor including a first gate electrode around the first pull-down transistor. A second vertical drain on the first vertical drain, a second vertical channel on the second vertical drain, a second vertical source on the second vertical channel, and a second gate electrode on the second vertical channel, Up transistor including a first pull-up transistor. The semiconductor device further includes a first via coupling the first gate electrode and the second gate electrode and a first conductive trace having a first portion between the first vertical drain and the second vertical drain. The semiconductor device includes a first pass including a third vertical source, a third vertical channel on the third vertical source, a third vertical drain on the third vertical channel, and a third gate electrode around the third vertical channel, Gate transistor, said first conductive trace having a second portion above said third vertical drain, as well as a fourth vertical source, said fourth vertical source, Down transistor including a fourth vertical channel of the fourth vertical channel, a fourth vertical drain on the fourth vertical channel, and a fourth gate electrode around the fourth vertical channel. The semiconductor device includes a fifth vertical drain on the fourth vertical drain, a fifth vertical channel on the fifth vertical drain, a fifth vertical source on the fifth vertical channel, and a fifth vertical drain on the fifth vertical channel, Up transistor comprising a first gate electrode, a second pull-up transistor comprising a gate electrode, said fifth gate electrode having a distal portion extending over a second portion of said first conductive trace, And a second via coupling the fourth gate electrode and the fifth gate electrode. The semiconductor device further includes a second conductive trace having a first portion between the fourth vertical drain and the fifth vertical drain, a sixth vertical source, a sixth vertical channel on the sixth vertical source, A second pass-gate transistor comprising a sixth vertical drain on the vertical channel, and a sixth gate electrode around the sixth vertical channel, the second conductive trace having a second portion over the sixth vertical drain And the second gate electrode has a distal portion extending over the second portion of the second conductive trace. The semiconductor device also includes a third via for joining the distal portion of the second gate electrode to the second portion of the second conductive trace, and a second via for coupling the distal portion of the fifth gate electrode to the second portion of the first conductive trace. And a fourth vias coupling the second portion.

According to various embodiments presented herein, a semiconductor device includes a first vertical pull-down transistor at a first active level of the semiconductor device, the first vertical pull- Down transistor and a first vertical pull-up transistor stacked on the first vertical pull-down transistor, wherein the first vertical pull-up transistor comprises a first vertical pull-down transistor, The transistor having a second gate electrode at a second active level of the semiconductor device and extending laterally at the second active level; and a second vertical pull-up transistor at the second active level, A first via coupled to the first gate electrode and the second active electrode at the second activation level, and a second via coupled to the first vertical pull- Up transistor, wherein the first conductive trace couples the drain regions of the first vertical pull-down transistor and the first vertical pull-up transistor to each other, the first conductive trace being disposed between the first conductive pull- And a second vertical pull-down transistor at the first active level of the semiconductor device, wherein the second vertical pull-down transistor includes a third gate electrode extending laterally at the first active level Down transistor and a second vertical pull-up transistor stacked on the second vertical pull-down transistor, the second vertical pull-up transistor being connected to the second active level of the semiconductor device The second vertical pull-up transistor having a fourth gate electrode extending laterally at the second activation level, A second via coupled to the third gate electrode at the first activation level and the fourth gate electrode at the second activation level, and a second via coupled between the second vertical pull-down transistor and the second vertical pull- Wherein the second conductive traces couple the drain regions of the second vertical pull-down transistor and the drain of the second vertical pull-up transistor to each other; and a second conductive trace disposed between the second conductive traces, A first vertical pass-gate transistor at the second active level of the semiconductor device, wherein a portion of the first conductive trace extends over a drain region of the first vertical pass-gate transistor, Gate transistor at the first active level of the semiconductor device; and a second vertical pass-gate transistor Gate, the portion of the second conductive trace extending over, and in contact with, the drain region of the vertical pass-gate transistor; and the second vertical pass-gate transistor, A third via interconnecting a portion of the second conductive trace in contact with the drain region of the first pass-gate transistor and a portion of the second gate electrode extending over the second vertical pass-gate transistor; And a fourth via interconnecting a portion of the first conductive trace in contact with the drain region of the first pass-gate transistor and a portion of a fourth gate electrode extending over the first vertical pass-gate transistor.

According to various embodiments presented herein, a semiconductor fabrication method includes forming a first semiconductor region surrounded by a first dielectric layer, a first channel region over the first source region, a second channel region over the first channel region, Forming a first vertical transistor comprising a first drain region surrounded by a first gate electrode layer and a first gate electrode layer around the first channel region, Forming a second channel region over the first source region, a second channel region over the first source region, and a second channel region over the second source region, Forming a second vertical transistor having a second drain region surrounded by the second dielectric layer and a second gate electrode layer around the second channel region, Wherein the second gate electrode layer is different from the first gate electrode layer and is disposed between the first dielectric layer and the second dielectric layer; Forming a third vertical transistor over the transistor; and forming a via over the second vertical transistor, wherein a portion of the via is surrounded by a gate electrode of a fourth vertical transistor .

Embodiments of the disclosure are best understood from the following detailed description when read with reference to the accompanying drawings. Note that, according to standard practice in the industry, the various features are not shown in scale. In practice, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.
1 shows a circuit diagram of a static random access memory (SRAM) according to an embodiment.
FIG. 2 illustrates a three-dimensional (3D) layout of an SRAM according to one embodiment.
Figures 3 and 4 illustrate an overlaid top-down view of the SRAM shown in Figure 2 in accordance with one embodiment.
Figure 5 illustrates various shapes of vertical transistors according to an embodiment.
Figures 6 and 7 illustrate an overlaid top-down view of an SRAM having a bar-shaped vertical transistor according to one embodiment.
8-18 illustrate a process flow illustrating a portion of the steps of a method of manufacturing an SRAM according to one embodiment.
19 to 30 illustrate a process flow illustrating a portion of the steps of a method of manufacturing an SRAM cell in which a vertical transistor according to an embodiment is self-aligned.
31 illustrates an overlaid top-down view of a 2x2 array of SRAM cells according to one embodiment.
32-35 illustrate an overlaid top-down view of the source-level of the first active level of the 2x2 array of SRAM shown in Fig. 31 according to an embodiment.
Figure 36 illustrates an overlaid top-down view of the channel-level and drain levels of the first active level of the 2x2 array of SRAM cells shown in Figure 31 in accordance with one embodiment.
37 shows an overlaid top-down view of a trace level of a 2x2 array of SRAM cells shown in Fig. 31 according to one embodiment.
Figure 38 shows an overlaid top-down view of the channel-level and drain levels of the second active level of the 2x2 array of SRAM cells shown in Figure 31 in accordance with one embodiment.
Figures 39 and 40 illustrate an overlaid top-down view of the source-level of the second active level of the 2x2 array of SRAM shown in Figure 31 in accordance with one embodiment.

The following disclosure provides many different embodiments or examples for carrying out the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and not limitations. For example, in the following description, the formation of the first feature over the second feature or over the second feature may include embodiments in which the first and second features are formed in direct contact, 1 and the second feature may be indirectly contacted with the first feature. In addition, the present disclosure may repeat the reference numerals and / or characters in various examples. Such repetition is for simplicity and clarity and does not itself determine the relationship between the various embodiments and / or configurations discussed.

It will also be appreciated that spatially relative terms such as "under", "under", "under", "above", "above", etc. are used herein to refer to one element (s) The terms spatially relative are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be oriented differently (90 degree rotation or other orientation), the spatially relative descriptors used herein can be similarly interpreted accordingly.

Static random access memory (SRAM) cells, such as SRAM cells, including vertical transistors, are provided in accordance with various exemplary embodiments. Some variations of the embodiments are discussed. Throughout the various drawings and the exemplary embodiments, the same reference numerals are used to refer to the same elements. Also, while the method embodiments discussed herein may be discussed as being performed in a particular order, other method embodiments may be practiced in any logical order.

1 shows a circuit diagram of an SRAM cell 100 according to one or more embodiments. SRAM cell 100 includes pull-up transistors PU1 and PU2, pull-down transistors PD1 and PD2, and pass-gate transistors PG1 and PG2 ), Which may be included in the write portion of the SRAM cell 100. In some embodiments, the SRAM cell 100 also includes a readout section (not shown) that may be electrically coupled to the pull-up transistors PU1 and PU2, the pull-down transistors PD1 and PD2, (Not shown in Figure 1). As shown in the circuit diagram, the pull-up transistors PU1 and PU2 are p-type transistors while the pull-down transistors PD1 and PD2 and pass-gate transistors are n-type transistors.

As shown, transistors PU1 and PD1 form a first inverter INV1 between a first power voltage Vdd and a second power voltage Vss (e.g., ground). The drains of the pull-up transistor PU1 and the pull-down transistor PD1 are connected together and the gates of the pull-up transistor PU1 and the pull-down transistor PD1 are connected together. Transistors PU2 and PD2 form a second inverter INV2 between the first power voltage Vdd and the second power voltage Vss. The drains of the pull-up transistor PU2 and the pull-down transistor PD2 are connected together and the gates of the pull-up transistor PU2 and the pull-down transistor PD2 are connected together. The sources of the pull-up transistors PU1 and PU2 are connected to the first power voltage Vdd while the sources of the pull-down transistors PD1 and PD2 are connected to the second power voltage Vss.

As shown in Fig. 1, inverters INV1 and INV2 are cross-connected to form a data latch. For example, the gates (connected together) of the transistors PU1 and PD1 are further connected to the drains of the transistors PU2 and PD2. Similarly, the gates (connected together) of the transistors PU2 and PD2 are further connected to the drains of the transistors PU1 and PD1. The storage node N1 of the data latch is connected to the bit line BL through the first pass-gate transistor PG1 and the storage node N2 is connected to the bit line BL through the second pass- And is connected to the supplemental bit line BLB. Storage nodes N1 and N2 are complementary nodes that are open at the opposite logic level (high logic or low logic). The gates of the first pass-gate transistor PG1 and the second pass-gate transistor PG2 are connected to the write-in line WL.

The SRAM cell 100 may be a single SRAM cell. The pull-up transistors PU1 and PU2, the pull-down transistors PD1 and PD2 and the pass-gate transistors PG1 and PG2 included in the SRAM cell 100 reduce the footprint of the SRAM cell 100 As a result, can be formed as vertical transistors in an effort to increase the integration density of a plurality of such SRAM cells 100. An example of an SRAM cell 100 having transistors PU1, PU2, PD1, PD2, PG1, and PG2 formed as vertical transistors is shown in FIG.

FIG. 2 illustrates a three-dimensional (3D) layout of SRAM cells 100 in accordance with one or more embodiments. The SRAM cell 100 includes a source region 102, a drain region 106, and a channel region (not shown in FIG. 2) disposed between the source region 102 and the drain region 106 Down transistor PD1 (referred to as a first pull-down transistor PD1) including a first pull-down transistor PD1 (see characteristic portion 806b). Note that elements 102 and 106 are referred to as source and drain regions, respectively, but each of elements 102 and 106 may also be referred to as source / drain regions. The first pull-down transistor PD1 may be formed at the first active level L1. The source region 102, the drain region 106, and the channel region of the first pull-down transistor PD1 may be a vertical source, a vertical drain, and a drain region, respectively, And a vertical channel. 2, the channel region of the first pull-down transistor PD1 may be formed over the source region 102 while the drain region 106 may be formed over the channel region.

The first pull-down transistor PD1 also includes a gate electrode 104 (hereinafter referred to as gate 104) for the sake of brevity (for example, around the gate electrode 104) around the channel region of the first pull- ) "). As an example, as shown in FIG. 2, the gate 104 of the first pull-down transistor PD1 is connected to a conductive feature having a first portion wrapped around the channel region of the first pull- While the second portion of the gate 104 extends away from the channel region of the first pull-down transistor PD1. The gate 104 of the first pull-down transistor PD1 is formed of a metal-containing material such as TiN, TaN, TiAl, TaAl, a Ti-containing material, a Ta-containing material, an Al- , NiSi, PtSi, polysilicon having a silicide, a Cu-containing material, a refractory material, etc., a combination thereof, or a multilayer thereof. The first pull-down transistor PD1 may include a dielectric material (see the discussion below with respect to FIG. 11) disposed between the channel region of the first pull-down transistor PD1 and the gate 104.

In one embodiment, the first pull-down transistor PD1 may be a junction transistor. For example, the source region 102 and the drain region 106 may be formed of a semiconductor material that also includes a dopant that causes the source region 102 and the drain region 106 to have a first conductivity (e.g., n-type) . On the other hand, the channel disposed between the source region 102 and the drain region 106 includes a semiconductor material (for example, a p-type) having a second conductivity (e.g., p-type) . ≪ / RTI >

The source region 102, the channel region, and the drain region 106 may comprise any suitable semiconductor, such as silicon, germanium, silicon germanium, combinations thereof, and the like. For example, in one embodiment, each of the source region 102 and the drain region 106 comprises doped silicon, while the channel region comprises undoped (or lightly doped) silicon. However, in other embodiments, the channel region may comprise doped silicon, while the source region 102 and drain region 106 comprise doped silicon germanium. In one embodiment where the first pull-down transistor PD1 is an n-type transistor, the source region 102 and the drain region 106 may be doped with an N-type dopant such as phosphorus or arsenic while the channel region is doped with boron Or doped with a P-type dopant such as gallium.

In one embodiment, the dopant concentration of the source region 102 and the drain region 106 may be greater than the dopant concentration of the channel region. For example, the source region 102 and the dopant concentration of the drain region 106 is about 1 × 10 ²⁰ cm ^-3 to about 2 × 10 ²¹ cm ^{- 3} or in the number of days over the range On the other hand, the source region (102) And the drain region 106 may be less than about 1 x 10 ¹⁸ cm ^-3 .

In another embodiment, the first pull-down transistor PD1 may be a non-junction type transistor. In this example, the drain region 106, the source region 102, and the channel region of the first pull-down transistor PD1 comprise a polycrystalline semiconductor material such as silicon, germanium, silicon germanium, combinations thereof, and the like . The polycrystalline semiconductor material of the drain region 106, the source region 102, and the channel region of the first pull-down transistor PD1 may have the same conductivity (e.g., n-type).

The SRAM cell 100 includes a source region 108, a drain region 112, and a channel region (not shown in FIG. 2) disposed between the source region 108 and the drain region 112 Down transistor PU1 (referred to as a first pull-up transistor PU1) including a pull-down transistor PU1 (see below). Note that elements 108 and 112 are referred to as source and drain regions, respectively, but each of elements 108 and 112 may also be referred to as source / drain regions. The first pull-up transistor PU1 may be formed at a second activation level L2 that is different from the first activation level L1. As an example, the second activation level L2 may be above the first activation level L1. As a result, the first pull-up transistor PU1 may be formed on the first pull-down transistor PD1. As an example, the first pull-up transistor PU1 may be stacked over the first pull-down transistor PD1.

In some embodiments, the first pull-up transistor PU1 may be self-aligned with the first pull-down transistor PD1 (see, for example, the following discussion with respect to Figures 19-30). However, in other embodiments, the first pull-up transistor PU1 may be self-aligned with the first pull-down transistor PD1 (see, for example, the following description with respect to Figures 8-18) . The first pull-up transistor PU1 may be a vertical transistor so that the source region 108, the drain region 112, and the channel region of the first pull-up transistor PU1 are connected to a vertical source, And a vertical channel. 2, the channel region of the first pull-up transistor PU1 may be formed on the drain region 112 while the source region 108 is formed on the channel of the first pull-up transistor PU1, Region. ≪ / RTI > 2, the drain region 112 of the first pull-up transistor PU1 may be formed on the drain region 106 of the first pull-down transistor PD1.

The first pull-up transistor PU1 is also connected to a gate electrode 110 (hereinafter simply referred to as "gate 110 " for simplicity) around (e.g., around) the channel region of the first pull- ) "). 2, the gate 110 of the first pull-up transistor PU1 has a conductive characteristic with a first portion wrapped around the channel region of the first pull-up transistor PU1, While the second portion of the gate 110 may extend away from the channel region of the first pull-up transistor PU1. The gate 110 of the first pull-up transistor PU1 may comprise a material similar to the gate 104 of the first pull-down transistor PD1. The first pull-up transistor PU1 may include a dielectric material (see below, with respect to FIG. 16) disposed between the gate 110 and the channel region of the first pull-up transistor PU1 .

In some embodiments, the first pull-up transistor PU1 may be a non-junction transistor. In this example, the drain region 112, the source region 108, and the channel region of the first pull-up transistor PU1 comprise a polycrystalline semiconductor material such as silicon, germanium, silicon germanium, combinations thereof, and the like . The polycrystalline semiconductor material of the drain region 112, the source region 108, and the channel region of the first pull-up transistor PU1 may have the same conductivity (e.g., p-type).

As shown in Fig. 1, the drains of the first pull-up transistor PU1 and the first pull-down transistor PD1 are connected together. This results in a first conductive trace (not shown) disposed between the drain region 112 of the first pull-up transistor PU1 and the drain region 106 of the first pull-down transistor PD1, 114). The first conductive trace 114 may be disposed between the first active level L1 and the second active level L2. The first conductive traces 114 may be in contact (e.g., physically and / or electrically contacted) with each of the drain regions 106 and 112 so that the first pull-up transistor PU1 and the first pull- - The drain of the down transistor PD1 is electrically connected together. The first conductive traces 114 may comprise any suitable conductive material, such as copper, tungsten, combinations thereof, and the like. Alternatively or additionally, the first conductive traces 114 may comprise silicides such as silicides such as cobalt, titanium, nickel, palladium, platinum, erbium, combinations thereof, and the like.

As shown in Fig. 1, the gates of the first pull-up transistor PU1 and the first pull-down transistor PD1 are connected together. This results in the gate 110 of the first pull-up transistor PU1 (e.g., the second portion of the gate 110) and the gate 104 of the first pull-down transistor PD1 (e.g., (For example, physically and / or electrically contacting) the first pull-up transistor PU1 and the gate of the first pull-down transistor PD1 together Can be accomplished by a first via 202 (shown by dashed line 202 in FIG. 2) that can be electrically connected. In some embodiments, the first via 202 may comprise a silicide (e.g., including a material similar to the first conductive trace 114). In other embodiments, the first via 202 may comprise a metal-containing material (e.g., including a material similar to the gate 104 of the first pull-down transistor PD1).

As shown in Fig. 1, the sources of the first pull-up transistor PU1 and the first pull-down transistor PD1 may be connected to a first power voltage Vdd and a second power voltage Vss, respectively . As a result, the source regions 108 and 102 of the first pull-up transistor PU1 and the first pull-down transistor PD1 shown in FIG. 2 are respectively connected to the first power voltage Vdd and the second power voltage Vdd 0.0 > Vss. ≪ / RTI > This can be accomplished by the use of metal lines and / or vias (not shown in FIG. 2; see the discussion below with respect to FIGS. 33, 39, and 40).

The SRAM cell 100 includes a source region 116, a drain region 120, and a channel region (not shown in FIG. 2) disposed between the source region 116 and the drain region 120 Down transistor PD2 (see second pull-down transistor PD2) that includes a first pull-down transistor PD2 (see feature section 806b). Note that elements 116 and 120 refer to source and drain regions, respectively, although each of elements 116 and 120 may also refer to source / drain regions. A second pull-down transistor PD2 may be formed at the first active level L1. The second pull-down transistor PD2 may be a vertical transistor and therefore the source region 116, the drain region 120, and the channel region of the second pull-down transistor PD2 may be a vertical source, And a vertical channel. 2, the channel region of the second pull-down transistor PD2 may be formed over the source region 116 while the drain region 120 is formed over the channel of the second pull-down transistor PD2, Region. ≪ / RTI >

The second pull-down transistor PD2 also includes a gate electrode 118 (hereinafter simply referred to as "gate 118 " for simplicity) that surrounds (e.g., surrounds) the channel region of the second pull- ) "). As an example, the gate 118 of the second pull-down transistor PD2 has a first portion that is wrapped around the channel region of the second pull-down transistor PD2, While the second portion of the gate 118 extends away from the channel region of the second pull-down transistor PD2. The gate 118 of the second pull-down transistor PD2 may comprise a material similar to the gate 104 of the first pull-down transistor PD1. The second pull-down transistor PD2 may include a dielectric material (see below in conjunction with FIG. 11) disposed between the gate region 118 of the second pull-down transistor PD2 and the channel region .

In one embodiment, the second pull-down transistor PD2 may be a junction transistor (e.g., similar to a junction transistor as described above in connection with the first pull-down transistor PD1). In another embodiment, the second pull-down transistor PD2 may be a non-junction transistor (similar to the non-junction transistor described above with respect to the first pull-down transistor PD1, for example). The second pull-down transistor PD2 may have the same conductivity (e.g., n-type) as the first pull-down transistor PD1. The source region 116, the drain region 120 and the channel region of the second pull-down transistor PD2 are connected to the source region 102, the drain region 106 and the drain region of the first pull- Dopant, and / or dopant concentration that is similar to the channel region.

The SRAM cell 100 may include a pull-up transistor PU2 (referred to as a second pull-up transistor PU2). As shown in Fig. 2, the second pull-up transistor PU2 is formed at the second active level L2. As a result, the second pull-up transistor PU2 may be formed on the second pull-down transistor PD2. As an example, the second pull-up transistor PU2 may be stacked over the second pull-down transistor PD2. In some embodiments, the second pull-up transistor PU2 may be self-aligned with the second pull-down transistor PD2 (see, e.g., the discussion below with respect to Figures 19-30). However, in other embodiments, the second pull-up transistor PU2 may not be self-aligned with the second pull-down transistor PD2 (see, for example, the discussion below with respect to Figures 8-18) .

The second pull-up transistor PU2 includes a source region 122, a drain region 126, and a channel region (not shown in FIG. 2) disposed between the source region 122 and the drain region 126 ; See the discussion below with respect to FIG. 16). Note that elements 122 and 126 refer to a source region and a drain region, respectively, although each of elements 122 and 126 may refer to a source / drain region. The second pull-up transistor PU2 may be a vertical transistor so that the source region 122, the drain region 126, and the channel region of the second pull-up transistor PU2 are connected to a vertical source, And a vertical channel. 2, the channel region of the second pull-up transistor PU2 may be formed on the drain region 126 while the source region 122 may be formed on the channel of the second pull-up transistor PU2, Region. ≪ / RTI > Also, as shown in FIG. 2, the drain region 126 of the second pull-up transistor PU2 may be formed above the drain region 120 of the second pull-down transistor PD2.

The second pull-up transistor PU2 is also connected to a gate electrode 124 (hereinafter simply referred to as "gate 124 ") for the sake of simplicity ) "). As shown in Figure 2, the gate 124 of the second pull-up transistor PU2 is connected to a conductive feature having a first portion wrapped around the channel region of the second pull-up transistor PU2, While the second portion of the gate 124 may extend away from the channel region of the second pull-up transistor PU2. The gate 124 of the second pull-up transistor PU2 may comprise a material similar to the gate 104 of the first pull-down transistor PD1. The second pull-up transistor PU2 may comprise a dielectric material (see below, with respect to FIG. 16) disposed between the gate region 124 of the second pull-up transistor PU2 and the channel region .

In some embodiments, the second pull-up transistor PU2 may be a non-junction transistor (similar to the non-junction transistor described above with respect to the first pull-up transistor PU1, for example). The second pull-up transistor PU2 may have the same conductivity (e.g., p-type) as the first pull-up transistor PU1. The source region 122, the drain region 126 and the channel region of the second pull-up transistor PU2 are connected to the source region 108, the drain region 106 and the drain region of the first pull- Dopant, and / or dopant concentration that is similar to the channel region.

As shown in Fig. 1, the drains of the second pull-up transistor PU2 and the second pull-down transistor PD2 are connected together. This is because the second conductivity-type impurity is disposed between the drain region 126 of the second pull-up transistor PU2 and the drain region 120 of the second pull-down transistor PD2, Trace 128. < / RTI > The second conductive trace 128 may be disposed between the first active level L1 and the second active level L2. The second conductive traces 128 may be in contact (e.g., physically and / or electrically contacted) with each of the drain regions 120 and 126 so that the second pull-up transistor PU2 and the second pull- - The drain of the down transistor PD2 is electrically connected together. The second conductive traces 128 may comprise a material similar to the first conductive traces 114.

As shown in Fig. 1, the gates of the second pull-up transistor PU2 and the second pull-down transistor PD2 are connected together. This results in the gate 124 (e.g., the second portion of the gate 124) of the second pull-up transistor PU2 and the gate 118 of the second pull-down transistor PD2 (e.g., Up transistor PU2 and the gate of the second pull-down transistor PD2 are electrically connected (e.g., physically and / or electrically contacted) with the first pull- (Shown by dashed line 204 in FIG. 2) that can be connected together by a second via 204. The second via 204 is shown in FIG. In some embodiments, the second via 204 may comprise a material similar to the first via 202.

As shown in Fig. 1, the sources of the second pull-up transistor PU2 and the second pull-down transistor PD2 may be connected to a first power voltage Vdd and a second power voltage Vss, respectively . As a result, the source regions 122 and 126 of the second pull-up transistor PU2 and the second pull-down transistor PD2 shown in FIG. 2 are respectively connected to the first power voltage Vdd and the second power voltage Vdd 0.0 > Vss. ≪ / RTI > This can be accomplished by the use of metal lines and / or vias (not shown in FIG. 2; see the discussion below with respect to FIGS. 33, 39, and 40).

The SRAM cell 100 includes a first pass-gate transistor PG1 and a second pass-gate transistor PG2. Pass-gate transistors PG1 and PG2 may be formed at the same active level as the first pull-down transistor PD1 and the second pull-down transistor PD2. As shown in FIG. 2, the first pull-down transistor PD1 and the second pull-down transistor PD2 may be formed in the first active region and the second active region, respectively, While the first pass-gate transistor PG1 and the second pass-gate transistor PG2 may be formed in the third active region and the fourth active region, respectively, of the first active level L1.

The first pass-gate transistor PG1 includes a source region 130, a drain region 134, and a channel region (not shown in FIG. 2) disposed between the source region 130 and the drain region 134. (See characteristic portion 806b in Fig. 9). Note that elements 130 and 134 refer to a source region and a drain region, respectively, although each of elements 130 and 134 may refer to a source / drain region. The source region 130, the drain region 134, and the channel region of the first pass-gate transistor PG1 may be a vertical source, a vertical drain, and a drain region, respectively, And a vertical channel. 2, the channel region of the first pass-gate transistor PG1 may be formed on the source region 130 while the drain region 134 may be formed on the channel of the first pass-gate transistor PG1, Region. ≪ / RTI > The source region 130, the drain region 134 and the channel region of the first pass-gate transistor PG1 are made of a material similar to the first pull-down transistor PD1 of the second pull-down transistor PD2, , And / or a dopant concentration.

The first pass-gate transistor PG1 also includes a gate electrode 132 (hereinafter simply referred to as "gate 132 ") for the sake of brevity ) "). As shown in FIG. 2, the gate 132 of the first pass-gate transistor PG1 is electrically connected to the conductive feature having a first portion wrapped around the channel region of the first pass- While the second portion of the gate 132 may extend away from the channel region of the first pass-gate transistor PG1. The gate 132 of the first pass-gate transistor PG1 may comprise a material similar to the gate 104 of the first pull-down transistor PG1. The first pass-gate transistor PG1 may include a dielectric material (see below, with respect to FIG. 11) disposed between the gate 132 and the channel region of the first pass-gate transistor PG1 .

As shown in FIG. 1, the gates of the first pull-up transistor PU1 and the first pull-down transistor PD1 are connected to the gate of the first pass-gate transistor PG1. This can be accomplished using the first conductive traces 114 as shown in FIG. Illustratively, the first conductive traces 114 may have a first portion disposed between the drains 112 and 106 of the first pull-up transistor PD1 and the first pull-down transistor PD1. The first conductive trace 114 may additionally have a second portion extending across the drain region 134 of the first pass-gate transistor PG1. The second portion of the first conductive trace 114 contacts (e.g., physically and / or electrically contacts) the drain region 134 of the first pass-gate transistor PG1 to form a first pull- The gate of the transistor PU1 and the first pull-down transistor PD1 can be electrically connected to the gate of the first pass-gate transistor PG1.

1, the gate of the first pass-gate transistor PG1 is connected to the write line WL while the source of the first pass-gate transistor PG1 is connected to the bit line BL . Exemplarily, the source region 130 of the first pass-gate transistor PG1 is connected to a metal line and / or via (not shown in FIG. 2; see the discussion below with respect to FIGS. 33 and 34) And may be electrically connected to the bit line BL. The gate 132 of the first pass-gate transistor PG1 may also be connected to the write line WL (not shown in FIG. 2; see the discussion below with reference to FIG. 36) As shown in FIG.

The second pass-gate transistor PG2 includes a source region 136, a drain region 140, and a channel region (not shown in FIG. 2) disposed between the source region 136 and the drain region 140 (See feature 806b of FIG. 9). Note that elements 136 and 140 refer to a source region and a drain region, respectively, although each of elements 136 and 140 may refer to a source / drain region. The source region 136, the drain region 140, and the channel region of the second pass-gate transistor PG2 are connected to a vertical source, a vertical drain, and a drain region, respectively, And a vertical channel. 2, the channel region of the second pass-gate transistor PG2 may be formed on the source region 136 while the drain region 140 may be formed on the channel of the second pass-gate transistor PG2, Region. ≪ / RTI > The source region 136, the drain region 140 and the channel region of the second pass-gate transistor PG2 are made of a material similar to the first pull-down transistor PD1 or the second pull-down transistor PD2, , And / or a dopant concentration.

The second pass-gate transistor PG2 also includes a gate electrode 138 (hereinafter simply referred to as "gate 138 " for simplicity) around (e.g., around) the channel region of the second pass- ) "). As shown in FIG. 2, the gate 138 of the second pass-gate transistor PG2 is connected to the conductive feature having a first portion wrapped around the channel region of the second pass- While the second portion of the gate 138 may extend away from the channel region of the second pass-gate transistor PG2. The gate 138 of the second pass-gate transistor PG2 may comprise a material similar to the gate 104 of the first pull-down transistor PD1. The second pass-gate transistor PG2 may comprise a dielectric material (see below with respect to FIG. 11) disposed between the gate 138 of the second pass-gate transistor PG2 and the channel.

As shown in Fig. 1, the gates of the second pull-up transistor PU2 and the second pull-down transistor PD2 are connected to the gate of the second pass-gate transistor PG2. This may be accomplished using a second conductive trace 128 as shown in FIG. Illustratively, the second conductive trace 128 may have a first portion disposed between the drains 126 and 120 of the second pull-up transistor PU2 and the second pull-down transistor PD2. The second conductive trace 128 may additionally have a second portion extending across the drain region 140 of the second pass-gate transistor PG2. The second portion of the second conductive trace 128 contacts (e.g., physically and / or electrically contacts) the drain region 140 of the second pass-gate transistor PG2 to form a second pull- The gate of the transistor PU2 and the gate of the second pull-down transistor PD2 can be electrically connected to the gate of the second pass-gate transistor PG2.

1, the gate of the second pass-gate transistor PG2 is connected to the write line WL while the source of the second pass-gate transistor PG2 is connected to the complementary bit line BLB do. By way of example, the source region 136 of the second pass-gate transistor PG2 can be formed by the use of metal lines and / or vias (not shown in FIG. 2; see the discussion below with reference to FIGS. 33 and 34) And may be electrically connected to the supplemental bit line BL. In addition, the gate 138 of the second pass-gate transistor PG2 may be electrically connected to the write line WL by use of an electrically conductive layer and / or via (not shown in FIG. 2).

As shown in Fig. 1, the data latch is formed by connecting the gates of the transistors PU1 and PD1 to the drains of the transistors PU2 and PD2. This can be accomplished using a third via 206 and a second conductive trace 128 as shown in FIG. For example, the second portion of the gate 110 of the first pull-up transistor PU1 is connected to the drain region 140 of the second pass-gate transistor PG2, Can be further extended over two portions. The third via 206 may be positioned between the second portion of the gate 110 and the second portion of the second conductive trace 128 and the gate 110 and the second conductive traces 128 Thereby connecting the gates of the transistors PU1 and PD1 to the drains of the transistors PU2 and PD2. The third via 206 may be formed at a second active level L2 and may comprise a material similar to the gate 104 of the first pull-down transistor PD1. As a result, additional via levels may be used to form a contact between the gates of the pull-up transistors PU1 and PU2 and the gates of the pull-down transistors PD1 and PD2. In some embodiments, the third via 206 can be self-aligned with the second pass-gate transistor PG2 (see, e.g., the discussion below with respect to Figures 19-30). However, in other embodiments, the third via 206 may not be self-aligned with the second pass-gate transistor PG2 (see, for example, the following discussion with respect to Figures 8-18).

Similarly, the data latch is formed by connecting the gates of the transistors PU2 and PD2 to the drains of the transistors PU1 and PD1. This can be accomplished using a fourth via 208 and a first conductive trace 114 as shown in FIG. For example, the second portion of the gate 124 of the second pull-up transistor PU2 is connected to the drain region 134 of the first pass-gate transistor PG1, Can be further extended over two portions. A fourth via 208 may be positioned between a second portion of the gate 124 and a second portion of the first conductive trace 114 and may connect the gate 124 and the first conductive trace 114 to each other Thereby connecting the gates of the transistors PU2 and PD2 to the drains of the transistors PU1 and PD1. The fourth via 208 may be formed at a second active level L2 and may include a material similar to the gate 104 of the first pull-down transistor PD1. As a result, additional via levels may be used to form a contact between the gates of the pull-up transistors PU1 and PU2 and the gates of the pull-down transistors PD1 and PD2. In some embodiments, fourth vias 208 may be self-aligned with first pass-gate transistor PG1 (see, for example, the following discussion with respect to Figures 19-30). However, in other embodiments, the fourth vias 208 may be self-aligned with the first pass-gate transistor PG1 (see, for example, the following discussion with respect to Figures 8-18).

Figure 3 is a top view of an overlaid top-down view of a first active level (L1), a first conductive trace (114), and a second conductive trace (128) of the SRAM cell 100 shown in Figure 2 according to one or more embodiments. Lt; / RTI > FIG. 4 illustrates an overlaid top-down view of a second active level L2 of the SRAM cell 100 shown in FIG. 2 in accordance with one or more embodiments. As shown in FIG. 3, a single SRAM cell 100 has a first width of about 2F and a second width of about 2F, where F is the minimum printable pitch of the SRAM cell 100. Consequently, the footprint of the SRAM cell 100 is about 4F ^2. Current single SRAM cell design with a vertical transistor has a footprint of approximately 10F ^2. As a result, the SRAM cell 100 with the layout shown in FIGS. 2-4 has a reduced footprint (e. G., Reduced by about 60%) compared to the current SRAM cell design. As a result, the integration density of a plurality of such SRAM cells 100 can be increased.

3, the dimension DMV1 (e.g., width) of the first via 202 is substantially equal to the dimension DMG1 of the gate 104 of the first pull-down transistor PD1 (e.g., For example, width). In addition, the dimension DMV2 (e.g., width) of the second via 204 may be substantially the same as the dimension DMG2 (e.g., width) of the gate 118. [ 3 and 4 also illustrate in a top-down view a first pull-down transistor PD1, a second pull-down transistor PD2, a first pass-gate transistor PG1, and a second pass- 0.0 > PG2. ≪ / RTI > The relative positions of these transistors can also be observed in Fig. For example, the first pass-gate transistor PG1 is coupled to the first pull-gate transistor PG1 along a first direction (e.g. along the Y-direction) by a first distance (e.g., a distance substantially equal to F) Gate transistor PG2 may be separated laterally from the down transistor PD1 while a second pass-gate transistor PG2 is formed along a second direction that is substantially perpendicular to the first direction (e.g., X -Direction) from the first pull-down transistor PD1. In addition, the second pull-down transistor PD2 can be separated laterally from the first pass-gate transistor PG1 along the second direction (e.g., along the X-direction) by a substantially first distance have. In addition, the second pull-down transistor PD2 may be laterally separated from the second pass-gate transistor PG2 along the first direction (e.g., along the Y-direction) by a substantially first distance I will follow.

In the example shown in Figs. 2 to 4, the vertical transistors PU1, PU2, PD1, PD2, PG1, and PG2 have a circular cross-section. As a result, in the example shown in Figs. 2 to 4, the vertical transistors PU1, PU2, PD1, PD2, PG1 and PG2 may be formed as wires (e.g., nanowires). However, in other embodiments, the vertical transistors PU1, PU2, PD1, PD2, PG1, and PG2 may have different shapes. 5 illustrates an example of a shape that vertical transistors PU1, PU2, PD1, PD2, PG1, and PG2 may have, according to one or more embodiments. 5, any of the pull-up transistors PU1 and PU2, the pull-down transistors PD1 and PD2, and the pass-gate transistors PG1 and PG2 may include an ellipse 502, a bar 504 A square 508, a rectangle 510, a triangle 512, or a hexagon 514, as shown in FIG. Other shapes may also be possible. As an example, all of the transistors of the SRAM cell 100 may be formed as bars 504. In this embodiment, the overlaid top-down view of the first active level (L1), first conductive trace 114 and second conductive trace 128 of SRAM cell 100 can be as shown in FIG. 6 have. Likewise, in this embodiment, the overlaid top-down view of the second activation level L2 of the SRAM cell 100 may be as shown in FIG.

8-18 illustrate a process flow illustrating some of the steps of a method of manufacturing an SRAM cell 100 in accordance with one or more embodiments. 8-18 illustrate an example where the first conductive traces 114 and the second conductive traces 128 include silicide, but the first conductive traces 114 and the second conductive traces 128 128 are different conductive materials. Fig. Silicon-on-insulator (SOI); Germanium (Ge); A compound semiconductor including silicon carbide, gallium arsenide, gallium phosphorus, indium phosphorus, indium arsenide, and / or indium antimonide; An alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; Or a combination thereof, and may be a semiconductor wafer. The semiconductor substrate 802 may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multi-layer or a gradient semiconductor substrate, and the like. FIG. 8 also shows a first doped region 804 formed over the semiconductor substrate 802. FIG. The first doped region 804 may be a multilayer semiconductor substrate including a source layer 804a, a channel layer 804b, and a drain layer 804c. In a specific embodiment, at least some of the source layer 804a, channel layer 804b and drain layer 804c of the first doped region 804 are formed by a first pull-down transistor PD1, Are used to form the source regions, channel regions, and drain regions of the down-transistor PD2, the first pass-gate transistor PG1, and the second pass-gate transistor PG2. The source layer 804a, the channel layer 804b and the drain layer 804c of the first doped region 804 are connected to the source region 102, the channel region, and the drain region of the first pull- Dopant, and / or dopant concentration, respectively, that is similar to the dopant 106.

The first doped region 804 may be formed using an epitaxial growth process using an exposed region of the semiconductor substrate 802 as a growth initiator. For example, in some embodiments, the epitaxial growth process may be performed using molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG) . Other epitaxial growth processes are possible. In one embodiment, each of the source layer 804a, the channel layer 804b, and the drain layer 804c of the first doped region 804 may be formed using the same epitaxial growth process. However, in another embodiment, the source layer 804a, the channel layer 804b, and the drain layer 804c of the first doped region 804 can be formed using different epitaxial growth processes.

In one embodiment, the dopants are introduced into the source layer 804a, the channel layer 804b, and the drain layer 804c of the first doped region 804 as each layer is grown. In one example, during the epitaxial growth process of the source layer 804a, precursors containing desired dopants are placed in situ within the reaction vessel with precursor reactants for the semiconductor material of the source layer 804a . As such, the dopants are introduced and included in the semiconductor material of the source layer 804a to provide the desired conductivity to the source layer 804a while the source layer 804a is growing. While the foregoing example relates to source layer 804a, similar processes may be used to introduce dopants into the semiconductor material of channel layer 804b and drain layer 804c as each layer grows.

Alternatively, in another embodiment, the dopants may be introduced into the semiconductor material of the source layer 804a, the channel layer 804b, and the drain layer 804c of the first doped region 804 after each layer has grown have. In one example, the semiconductor material of the source layer 804a may grow without a dopant, and the source layer 804a may be grown using an implantation process, such as an implantation process or a diffusion process, before the channel layer 804b is grown, Source layer 804a. Once the dopants have been introduced into the source layer 804a, an annealing process may be performed to activate the dopants. The epitaxial growth of the channel layer 804b can then be initiated. Although the above example relates to the source layer 804a, similar processes can be used to introduce dopants into the semiconductor material of the channel layer 804b and the drain layer 804c after each layer has grown.

Referring to FIG. 9, a first vertical structure 806 is formed from the first doped region 804 using, for example, a masking and etching process. In one example, a patterned mask (not shown in FIG. 9) may be formed over a portion of the first doped region 804. The patterned mask may be patterned to form a first vertical structure 806 when the first doped region 804 is recessed using an anisotropic etch such as reactive ion etching (RIE) Lt; / RTI > Thereafter, the structure shown in FIG. 9 can be formed by removing the patterned mask using, for example, a peeling process (for example, a wet peeling process) or an etching process (for example, a plasma ashing process) . The first vertical structure 806 has a cross section in a plane parallel to the top surface of the semiconductor substrate 802, such as a circle, square, rectangular, oval, elliptical or the like (for example, Lt; / RTI > In the example of FIG. 9, only one first vertical structure 806 is shown to clearly and simply illustrate various aspects of some embodiments. However, in practice, a plurality of such vertical structures can be formed. In one example, four vertical structures 806 can be formed, and the four vertical structures 806 can be used to connect the pull-down transistors PD1, PD2 of the SRAM cell 100 shown in FIGS. 1 and 2 And the pass-gate transistors PG1 and PG2.

The first vertical structure 806 includes a source region 806a, a channel region 806b over the source region 806a, and a drain region 806c over the channel region 806a. As described above, the pull-down transistors PD1 and PD2 and the pass-gate transistors PG1 and PG2 of the SRAM cell 100 shown in FIGS. 1 and 2 are formed by using the first vertical structure 806, Can be produced. As such, the source region 806a of the first vertical structure 806 can be identified as any one of the source regions 102, 116, 130, 136 shown in FIG. Similarly, the drain region 806c of the first vertical structure 806 can be identified as any one of the drain regions 106, 120, 134, 140 shown in FIG. Similarly, the channel region 806b of the first vertical structure 806 is connected to the pull-down transistors PD1 and PD2 of the SRAM cell 100 shown in FIG. 2 and the pass-gate transistors PG1 and PG2 ). ≪ / RTI >

Referring to FIG. 10, a first dielectric layer 808 is formed on the semiconductor substrate 802 and around the source region 806a of the first vertical structure 806. In some embodiments, the first dielectric layer 808 is an oxide formed by flow-through CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system) and post-curing such as annealing. In other embodiments, the first dielectric layer 808 may be formed by other deposition techniques, such as CVD, PECVD, or a combination thereof, and may be formed from silicon oxide, phosphosilicate glass (PSG), borosilicate glass BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), nitride, oxynitride, and the like.

In some embodiments, the first dielectric layer 808 may cover the source region 806a, the channel region 806b, and the drain region 806c, as well as the top surface of the first vertical structure 806. In this embodiment, an etch back process is performed to remove the upper surface of the first vertical structure 806 from the upper surface of the first vertical structure 806 while leaving the sidewalls of the source region 806a covered by the first dielectric layer 80, Lt; RTI ID = 0.0 > 808b < / RTI >

Referring to FIG. 11, a first gate dielectric 810 and a first gate electrode layer 812 are formed. The first gate dielectric 810 is conformally deposited on the vertical channel structure 72, for example, on the sidewalls of the channel region 806b of the first vertical structure 806. [ According to some embodiments, the first gate dielectric 810 comprises silicon oxide, silicon nitride, or multiple layers thereof. In other embodiments, the first gate dielectric 810 comprises a high-k dielectric material, and in such embodiments, the first gate dielectric 810 may have a dielectric constant greater than about 7.0, or And may have a k value of greater than about 10.0. The dielectric material having a high dielectric constant may include SiON, Si ₃ N ₄ , Ta ₂ O ₅ , Al ₂ O ₃ , Hf oxide, Ta oxide, Al oxide, rare earth metal oxide, and combinations thereof. The method of forming the first gate dielectric 810 may include molecular beam deposition (MBD), ALD, PECVD, or the like, or a combination thereof. The first gate electrode layer 812 is then deposited over the first gate dielectric 810 and the first dielectric layer 808 using one or more of MBD, ALD, PECVD, and the like, for example. The first gate electrode layer 812 is formed of a metal-containing material such as TiN, TaN, TiAl, TaAl and TaC, a Ti-containing material, a Ta-containing material, an Al-containing material, a W-containing material, TiSi, NiSi, PtSi , Polysilicon having a silicide, a Cu-containing material, a refractory material, or the like, a combination thereof, or a multilayer thereof. The first gate electrode layer 812 can be identified as any one of the gates 104, 118, 132, 138 shown in FIG. 2, for example.

Referring to FIG. 12, a second dielectric layer 814 is formed over the first gate dielectric 810 and the first gate electrode layer 812. A second dielectric layer 814 is also formed around the drain region 806c of the first vertical structure 806. The second dielectric layer 814 may include materials similar to the first dielectric layer 808. The second dielectric layer 814 may be formed using processes similar to the first dielectric layer 808. Along with the formation of the second dielectric layer 814, at least a portion of the first active level L1 of the SRAM cell 100 may be formed.

13, the silicide layer 816 may be formed on the second dielectric layer 814 as well as on the drain region 806c of the first vertical structure 806 (e.g., one of MBD, ALD, PECVD, etc.) Or more). The silicide layer 816 may be identified as the first conductive trace 114 or the second conductive trace 128 shown in FIG. The silicide layer 816 is formed by a subsequent anneal step such as rapid thermal annealing (RTA) in which blanket deposition of one or more suitable metal layers and metal or metals are reacted with exposed underlying semiconductor material (e.g., silicon) . The unreacted metal can then be removed, for example, by a selective etching process.

14, the process flow includes forming a third dielectric layer 818 over the silicide layer 816, forming a second gate electrode layer 820 over the third dielectric layer 818, Lt; RTI ID = 0.0 > 820 < / RTI > The third dielectric layer 818 and the fourth dielectric layer 822 may comprise materials similar to the first dielectric layer 808. In addition, the third dielectric layer 818 and the fourth dielectric layer 822 may be formed using processes similar to the first dielectric layer 808. The second gate electrode layer 820 may comprise materials similar to the first gate electrode layer 812. In addition, the second gate electrode layer 820 may be formed using processes similar to the first gate electrode layer 820. [ The third dielectric layer 818, the second gate electrode layer 820, and the fourth dielectric layer 822 may define a second activation level L2 of the SRAM cell 100. The second gate electrode layer 820 also forms the gates 110 and / or 124 (shown in FIG. 2) of the first pull-up transistor PU1 and the second pull-up transistor PU2, respectively Can be used.

15, an opening 824 may be formed in the third dielectric layer 818, the second gate electrode layer 820, and the fourth dielectric layer 822 to expose a portion of the silicide layer 816 have. The openings 824 may be formed by lithographic and etching processes using patterned masks with openings formed therein. In some embodiments, the openings of the patterned mask are substantially aligned with the first vertical structure 806. The opening 824 may be formed using a suitable etching process (e.g., anisotropic etching such as RIE). Following formation of the openings 824, the process flow relies on whether the first vertical structure 806 is one of the pull-down transistors PD1, PD2 or one of the pass-gate transistors PG1, PG2 . In an embodiment where the first vertical structure 806 is one of the pull-down transistors PD1, PD2 or the pass-gate transistors PG1, PG2, the opening 824 of the second active layer L2 is connected to the first pull- Can be used to form the first pull-up transistor PU1 or the second pull-up transistor PU2 on the down transistor PD1 or the second pull-down transistor PD2, respectively. This step is shown in FIG. 16 where a second gate dielectric 826 is formed (e.g., conformally formed) on the sidewalls of the opening 824.

The second gate dielectric 826 may comprise materials similar to the first gate dielectric 810 and may be formed using processes similar to the first gate dielectric 810. [ Second vertical structure 828 may also be formed to fill opening 824. Second vertical structure 828 may comprise a polycrystalline semiconductor material such as silicon, germanium, silicon germanium, combinations thereof, and the like. As a result, the second vertical structure 828 can be identified as the first pull-up transistor PU1 and / or the second pull-up transistor PU2 shown in FIG. A portion of the second vertical structure 828 surrounded by the third dielectric layer 818 may be identified as any one of the drain regions 112, 126 shown in FIG. A portion of the second vertical structure 828 surrounded by the second gate electrode layer 820 may be identified as any one of the channel regions of the first pull-up transistor PU1 or the second pull- have. In addition, a portion of the second vertical structure 828 surrounded by the fourth dielectric layer 822 may be identified as any one of the source regions 108, 122 shown in FIG.

The second vertical structure 828 may be formed using an epitaxial growth process that utilizes the exposed regions of the silicide layer 816 as a growth initiator. For example, in some embodiments, the epitaxial growth process may be performed using molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG) . Other epitaxial growth processes are possible. In some embodiments, the second vertical structure 828 may overfill the opening 824. In this embodiment, a planarization step (e.g., a chemical mechanical polishing step) may be performed to remove portions of the second vertical structure 828 outside the opening 824.

In one embodiment, the dopants are introduced into the material of the second vertical structure 828 as the second vertical structure 828 grows. In one example, during the epitaxial growth process of the second vertical structure 828, the precursors containing the desired dopants are placed in place in the reaction vessel with the precursor reactants for the material of the second vertical structure 828. As such, the dopants are introduced into the material of the second vertical structure 828 to provide a desired conductivity (e.g., p-type) to the second vertical structure 828 while the second vertical structure 828 is growing . Alternatively, in another embodiment, the dopants may be introduced into the material of the second vertical structure 828 after the second vertical structure 828 has grown. In one example, the material of the second vertical structure 828 may grow without dopants and introduce dopants into the material of the second vertical structure 828 using an implant process, such as an implant process or a diffusion process.

Referring again to FIG. 15, following formation of the openings 824, the process flow continues until the first vertical structure 806 is one of the pull-down transistors PD1, PD2 or the pass-gate transistors PG1, PG2). ≪ / RTI > In an embodiment where the first vertical structure 806 is one of the pass-gate transistors PG1 and PG2, the opening 824 of the second active layer L2 is connected to the second pass- May be used to form a third via 206 or a fourth via 208 over the one pass-gate transistor PG1. This step is shown in Fig. 17 where metal features 830 can be formed to fill openings 824. Fig. The metal features 830 may include materials similar to the first gate electrode layer 812 and may be formed using processes similar to the first gate electrode layer 812. [ Subsequently, in some embodiments, the metal feature 830 may be formed such that the upper surface of the metal feature 830, for example, substantially overlaps the upper surface of the second gate electrode layer 820, (For example, by using an appropriate etching process such as RIE) so as to be in a hibernation state. Then, the upper surface of the metal feature 830 may be covered by a dielectric material (not shown in Fig. 18).

In the above example, the first one of the first vertical structures 806 is one of the pass-gate transistors PG1 and PG2 and the second one of the first vertical structures 806 is the pull-down transistors PD1 and PD2. The second vertical structure 828 and the second gate dielectric 826 are formed in the opening 824 over the pass-gate transistor PG1 or PG2 while the metal feature 830 is formed in the full- Is formed in the opening 824 over the down transistor PD1 or PD2. However, in another embodiment, the second vertical structure 828 and the second gate dielectric 826 are formed by the pass-gate transistors PG1 or PG2 (not shown) as well as the openings 824 on the pull-down transistors PD1 or PD2 May also be formed. Subsequently, a second vertical structure 828 and a second gate dielectric 826 over the pass-gate transistor PG1 or PG2 are removed (e.g., via an etch process) to remove a portion of the silicide layer 816 So that the opening 824 can be re-formed. 17 and 18, the opening 824 on the pass-gate transistor PG1 or PG2 may be filled with a conductive material to form the metal feature 830. [ As a result, in this embodiment, the p-channels on the pass-gate transistors PG1 and PG2 remove the second vertical structure 828 (e.g., poly-Ge) and the second gate dielectric 826 By filling the opening with metal, it can be converted to local drain-gate contacts.

The process flow shown in FIGS. 8 to 18 is the same as the process flow shown in FIG. 2 except that the pull-up transistors PU1 and PU2, pull-down transistors PD1 and PD2 of the SRAM cell 100 shown in FIG. 2, (PG1, PG2). As described above with respect to FIG. 15, the openings 824 may be formed by using a patterned mask as an etch mask. The alignment between the opening 824 and the underlying first vertical structure 806 depends on the alignment between the patterned mask and the first vertical structure 806. As a result, the metal feature 830 and the second vertical structure 828 formed in the opening 824 are not self-aligned with the first vertical structure 806.

Figures 19-30 illustrate a process flow illustrating some of the steps of a method of fabricating SRAM cells in which vertical transistors are self-aligned in accordance with one or more embodiments. 19 through 30 illustrate an example in which the first conductive trace 114 and the second conductive trace 128 include silicide, but the first conductive trace 114 and the second conductive trace 128 128 are made of different conductive materials. Referring to Fig. 19, a first vertical structure 806 may be formed on semiconductor substrate 802 (e.g., using the processes described above with respect to Figs. 8 and 9). In addition, a sacrificial vertical structure 902 is formed over the first vertical structure 806. The sacrificial vertical structure 902 may comprise a semiconductor material similar to the first vertical structure 806. The sacrificial vertical structure 902 may be formed using an epitaxial growth process that utilizes the exposed regions of the drain region 806c of the first vertical structure 806 as a growth initiator. For example, in some embodiments, the epitaxial growth process may be performed using molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG) Lt; / RTI > Other epitaxial growth processes are possible. The sacrificial vertical structure 902 is formed by utilizing the exposed regions of the drain region 806c of the first vertical structure 806 as a growth initiator so that the sacrificial vertical structure 902 is substantially perpendicular to the first vertical structure 806 They can have the same lateral dimensions.

20, a first dielectric layer 808, a first gate dielectric 810, a first gate electrode layer 812, and a second dielectric layer 814 form a first vertical structure 806 and a sacrificial vertical structure 902, respectively. In this example, a first dielectric layer 808 may be formed around the source region 806a of the first vertical structure 806 while the first gate dielectric 810 and the first gate electrode layer 812 may be formed around the source region 806a, May be formed around the channel region 806b of the vertical structure 806. [ A second dielectric layer 814 can be formed around the drain region 806c of the first vertical structure 806 and also around the sacrificial vertical structure 902. [ A first dielectric layer 808, a first gate dielectric 810, a first gate electrode layer 812, and a second dielectric layer 814 are formed around the first vertical structure 806 and the sacrificial vertical structure 902 So that similar processes as described above with respect to Figures 10 to 12 can be used.

21, a portion of the second dielectric layer 814 is recessed (e.g., using an appropriate etch process such as RIE) to form a sacrificial vertical structure 902 and a drain near the sacrificial vertical structure 902 A portion of the region 806c can be exposed. 22, over the remaining portion of the second dielectric layer 814 and around the exposed portion of the drain region 806c, using, for example, the processes described above with respect to the silicide layer 816. [ A silicide layer 904 can be formed. In addition, the silicide layer 904 may surround the first portion 902a of the sacrificial vertical structure 902 proximate the drain region 806c. The sacrificial vertical structure 902 also includes a second portion 902b on the first portion 902a, a third portion 902c on the second portion 902b, and a third portion 902b on the third portion 902c. 4 portion 902d.

In some embodiments, the silicide layer 904 may be formed on the top surface of the fourth portion 902d of the sacrificial vertical structure 902 and the first portion 902a of the sacrificial vertical structure 902, The second portion 902b, the third portion 902c, and the fourth portion 902d. The portion of the silicide layer 904 may then be planarized and / or etched to form the upper portion of the fourth portion 902d of the sacrificial vertical structure 902 and the second portion 902b of the sacrificial vertical structure 902, The second portion 902c, and the fourth portion 902d are exposed to form the structure shown in FIG. Along with the formation of the silicide layer 904, the first activity level L1 of the SRAM cell 100 is defined and the silicide layer 904 is processed in subsequent steps to form the first conductive trace 114 or 2 conductive traces 128 may be formed.

Referring to Figure 23, a third dielectric layer 818 may be formed over the silicide layer 904 and may be formed over the sacrificial vertical structure 902 using, for example, one or more of the processes described above with respect to Figure 14. [ As shown in FIG. In some embodiments, a third dielectric layer 818 may be formed over the top surface of the fourth portion 902d of the sacrificial vertical structure 902 and includes a second portion 902b of the sacrificial vertical structure 902, A portion 902c, and a fourth portion 902d. A portion of the third dielectric layer 818 may then be planarized and / or etched to form an upper surface of the fourth portion 902d of the sacrificial vertical structure 902 and a third portion 902c of the sacrificial vertical structure 902, The side walls of the portion 902d are exposed to form the structure shown in Fig.

Referring to FIG. 24, the process flow continues to form dummy gate dielectric 906 over third dielectric layer 818 and third portion 902c of sacrificial vertical structure 902. A second gate electrode layer 820 is also formed around the third dielectric layer 818 and around the dummy gate dielectric 906. The dummy gate dielectric 906 may include materials similar to the first gate dielectric 810 and may be formed using processes similar to the first gate dielectric 810. In some embodiments, the dummy gate dielectric 906 and second gate electrode layer 820 are formed on the top surface of the fourth portion 902d of the sacrificial vertical structure 902 and on the third portion 902c of the sacrificial vertical structure 902 ) And the fourth portion 902d. The dummy gate dielectric 906 and a portion of the second gate electrode layer 820 are then planarized and / or etched to form the top surface of the fourth portion 902d of the sacrificial vertical structure 902 and the top surface of the sacrificial vertical structure 902 The sidewalls of the fourth portion 902d are exposed to form the structure shown in Fig.

25, the process flow continues to form a fourth dielectric layer 822 over the dummy gate dielectric 906 and the second gate electrode layer 820. As shown in FIG. A fourth dielectric layer 822 is also formed around the fourth portion 902d of the sacrificial vertical structure 902. In some embodiments, a fourth dielectric layer 822 may be formed on the upper surface of the fourth portion 902d of the sacrificial vertical structure 902 and around the sidewalls. Thereafter, a portion of the fourth dielectric layer 822 may be planarized and / or etched to expose the top surface of the fourth portion 902d of the sacrificial vertical structure 902 to form the structure shown in FIG. In the embodiment of Figure 25, the fourth portions 902d of the sacrificial vertical structures 902 and the top surfaces of the fourth dielectric layer 822 are substantially coplanar. In addition, the third dielectric layer 818, the second gate electrode layer 820, and the fourth dielectric layer 822 may define a second activation level L2 of the SRAM cell 100.

The process flow may include the steps of removing the sacrificial vertical structure 902 (e.g., using a suitable etch process) to expose the top surface of the first vertical structure 806 to form the opening 908 . A metal layer 910 is also formed (e.g., conformally formed) on the sidewalls of the opening 908 and over the top surface of the fourth dielectric layer 822. The metal layer 910 may be formed using one or more of MBD, ALD, PECVD and may be formed of a suitable metal (e.g., cobalt, titanium, nickel, palladium, platinum, erbium, combinations thereof Etc.). Following metal layer 910 formation, rapid thermal annealing (RTA) or the like, in which metals or metals react with the underlying exposed semiconductor material (e.g., silicon in drain region 806c) of first vertical structure 806 A silicidation process may be performed to cause the metal layer 910 to pass through the annealing step. 27, the unreacted metal may be removed, for example, by a selective etching process to form a silicide region 806c overlying the drain region 806c of the first vertical structure 806 and a silicide region < RTI ID = 0.0 > (912) can be formed. The selective etch process can also remove the dummy gate dielectric 906 and thus expose the sidewalls of the second gate electrode layer 820 as shown in FIG. The silicide layer 904 may be identified with the silicide region 912 as the first conductive trace 114 or the second conductive trace 128 shown in FIG.

Following the formation of the silicide region 912 at the bottom of the opening 908, the process flow continues until the first vertical structure 806 is one of the pull-down transistors PD1, PD2 or the pass-gate transistors PG1 , PG2). ≪ / RTI > In an embodiment where the first vertical structure 806 is one of the pull-down transistors PD1 and PD2, the opening 908 of the second active layer L2 is connected to the first pull- Can be used to form the first pull-up transistor PU1 or the second pull-up transistor PU2 respectively on the pull-down transistor PD2. This step is illustrated in FIG. 28 where a second gate dielectric 826 is formed (e.g., conformally formed) on the sidewalls of the opening 908 using one or more of the processes described above with respect to FIG. . Second vertical structure 828 can also be used to fill opening 908 using, for example, one or more of the processes described above with respect to FIG. The second vertical structure 828 can be identified as the first pull-up transistor PU1 or the second pull-up transistor PU2 shown in FIG. In some embodiments, following the formation of the second vertical structure 828, an anneal step may be followed that allows the semiconductor material from the second vertical structure 828 to react with or diffuse into the silicide region 912 have.

Referring again to FIG. 27, following forming the silicide region 912 at the bottom of the opening 908, the process flow continues until the first vertical structure 806 is in contact with one of the pull-down transistors PD1, PD2 Or one of the sense or pass-gate transistors PG1, PG2. In an embodiment where the first vertical structure 806 is one of the pass-gate transistors PG1 and PG2, the opening 908 of the second active layer L2 is connected to the second pass-gate transistor PG2 or the first May be used to form the third via 206 or the fourth via 208 on the pass-gate transistor PG1, respectively. This step is shown in FIG. 29, which may form the metal feature 830 to fill the opening 824. FIG. The metal features 830 may include materials similar to the first gate electrode layer 812 and may be formed using processes similar to the first gate electrode layer 812. [ Subsequently, in some embodiments, the metal features 830 may be formed such that the upper surface of the metal feature 830, for example, substantially overlaps the upper surface of the second gate electrode layer 820, (For example, by using an appropriate etching process such as RIE) so as to be in a hibernation state. Then, the upper surface of the metal feature 830 can be covered by a dielectric material (not shown in FIG. 30).

In the above example, the first one of the first vertical structures 806 is one of the pass-gate transistors PG1 and PG2 and the second one of the first vertical structures 806 is the pull-down transistors PD1 and PD2. The second vertical structure 828 and the second gate dielectric 826 are formed in the opening 908 over the pass-gate transistor PG1 or PG2 while the metal feature 830 is formed in the pull- Is formed in the opening 908 over the transistor PD1 or PD2. However, in another embodiment, the second vertical structure 828 and the second gate dielectric 826 are formed by the pass-gate transistors PG1 or PG2, as well as the openings 908 on the pull-down transistors PD1 or PD2, May also be formed in the opening 908 above. Subsequently, the second vertical structure 828 and the second gate dielectric 826 over the pass-gate transistor PG1 or PG2 are removed (e.g., via an etching process) to expose the silicide region 912 , The opening 908 can be re-formed. The opening 908 over the pass-gate transistor PG1 or PG2 may then be filled with a conductive material to form the metal feature 830, for example, as shown in Figures 29 and 30. [

The process flow shown in Figs. 19 to 30 is the same as the process flow shown in Fig. 2 except that the pull-up transistors PU1 and PU2, pull-down transistors PD1 and PD2 of the SRAM cell 100 shown in Fig. 2, (PG1, PG2). The sacrificial vertical structure 902 is formed prior to formation of the dielectric layers 808, 814, 818, and 822, gate electrode layers 812 and 820, and gate dielectrics 810 and 906, as described above with respect to FIG. Lt; RTI ID = 0.0 > 806 < / RTI > In addition, the sacrificial vertical structure 902 defines the position of the opening 908 that is subsequently formed at the second activation level of the SRAM cell 100. [ As a result, the metal feature 830 and the second vertical structure 828 are self-aligned with the first vertical structure 806.

31 is a stacked top down view of a 2x2 array of RAM cells 100 in accordance with one or more embodiments. A larger array is possible, and a 2x2 array is shown to clearly and simply illustrate various aspects of some embodiments. 31 illustrates an example in which the first conductive trace 114 and the second conductive trace 128 include silicide, but the first conductive trace 114 and the second conductive trace 128 are different from each other Other examples involving conductive materials are possible. In an array, each SRAM cell 100 has an adjacent cell 100 in which the cells 100 are mirrored over an adjacent X-direction or Y-direction boundary. For example, cell 100-2 is a mirrored version of cell 100-1 along the X-direction boundary between cells 100-1 and 100-2. Similarly, cell 100-3 is a mirrored version of cell 100-1 along the Y direction boundary between cells 100-1 and 100-3. The 2 × 2 array shown in FIG. 31 illustrates circular nanowire transistors (eg, in cross-sectional view). However, the cross-sectional shape of the transistors may be any other shape, for example, rod-like, rectangular, or elliptical (as shown in FIG. 5). Each of the SRAM cells 100 is configured to reduce the footprint of the SRAM cell 100 and thereby increase the integration density of a plurality of such SRAM cells 100 (such as the 2x2 array shown in Figure 31) (3D) layout shown in Fig. 2 in which the vertical transistors are formed at the first activation level L1 and the second activation level L2.

Hereinafter, various aspects of the different levels of vertically stacked transistors of the SRAM cells 100 shown in FIG. 31 will be described. 32 shows a superposed top down view of a source level S1 of a first active level L1 of a 2x2 array of SRAM cells 100 shown in Fig. The source level S1 (see FIG. 2) may be, for example, the level of the first active level L1 at which the source regions of the pull-down transistors PD1 and PD2 and the pass-gate transistors PG1 and PG2 are formed . The source level S1 of the first activation level L1 includes a first n-well 1002, a second n-well 1004, a third n-well 1006 and a fourth n-well 1008 . The source region 136 of the second pass-gate transistor PG2 of the SRAM cells 100-1 through 100-4 includes a first n-well 1002, a second n-well 1004, a third n- Well 1006, and fourth n-well 1008, respectively.

The array may also include a variety of n-wells that may extend across multiple cells 100. For example, the array may include a fifth n-well 1010 extending along the Y direction across the cells 100-1, 100-2, and a Y-direction across the cells 100-3, 100-4 Lt; RTI ID = 0.0 > n-well < / RTI > The source region 116 of each second pull-down transistor PD2 of the cells 100-1 and 100-2 may extend from the fifth n-well 1010 while the source region 116 of each of the cells 100-3, The source region 116 of each second pull-down transistor PD2 of the first pull-down transistor 100-4 may extend from the sixth n-well 1012. 32, the first n-well 1002, the second n-well 1004, and the fifth n-well 1010 may be aligned. In addition, in some embodiments, the third n-well 1006, the fourth n-well 1008, and the sixth n-well 1012 may be aligned as shown in FIG.

The array includes a seventh n-well 1014 extending along the X direction across the cells 100-1 and 100-3 and a seventh n-well 1014 extending along the X direction across the cells 100-2 and 100-4. 8 < / RTI > well (1016). The seventh n-well 1014 may be located between the first n-well 1002 and the third n-well 1006 while the eighth n-well 1016 may be located between the second n-well 1004 Lt; / RTI > and the fourth n-well 1008, respectively. The source region 102 of each first pull-down transistor PD2 of the cells 100-1 and 100-3 may extend from the seventh n-well 1014 while the source regions 102 of the cells 100-2, The source region 102 of each first pull-down transistor PD1 of the first pull-down transistor 100-4 may extend from the eighth n-well 1016.

The array includes a ninth n-well 1018 extending along the X direction across the cells 100-1 and 100-3 and a ninth well 1018 extending along the X direction across the cells 100-2 and 100-4. 10 < / RTI > The ninth well 1018 may be located between the fifth n-well 1010 and the sixth n-well 1012 while the tenth n-well 1020 may be located between the fifth n-well 1010 ) And the sixth n-well (1012). The source region 130 of each first pass-gate transistor PG1 of the cells 100-1 and 100-3 may extend from the ninth n-well 1018 while the source regions 130 of the cells 100-2, The source region 130 of each first pass-gate transistor PG1 of the first n-well 100-4 may extend from the tenth n-well 1020.

As described above with respect to FIG. 2, the source regions 116, 102 of the pull-down transistors PD1, PD2 may be coupled to the second power voltage Vss. As shown in Fig. 33, this can be coupled to the fifth n-well 1010, the sixth n-well 1012, the seventh n-well 1014, and the eighth n- Lt; RTI ID = 0.0 > 1022 < / RTI > A plurality of power vias 1022 may include a conductive material (e.g., similar to the conductive material of first via 202 described above with respect to FIG. 2). The plurality of power vias 1022 are connected to the first n-well 1010, the sixth n-well 1012, the seventh n-well 1014 and the eighth n- Of the transistors PD1 and PD2 May be coupled to a second power rail 1024 that supplies the second power voltage Vss to the source regions 116, The second power rail 1024 may include a conductive material similar to the conductive material of the first via 202 described above with respect to FIG. 2 and may be formed in a 2x2 array of metallized layers.

As described above with respect to FIG. 2, the source region 130 of the first pass-gate transistor PG1 may be electrically coupled to the bit line BL. 34, this can be achieved by using a plurality of bit line vias 1026 that can be coupled to the n-well 1018 and the tenth n-well 1020, respectively. A plurality of bitline vias 1026 may include a conductive material (e.g., similar to the conductive material of first via 202 described above with respect to FIG. 2). The bit line vias 1026 may couple the ninth well 1018 and the tenth n-well 1020 to a bit line BL that may be formed in a 2x2 array of metallization layers . The bit line BL may be formed in another metal layer from the second power rail 1024.

As described above with respect to FIG. 2, the source region 136 of the second pass-gate transistor PG2 may be electrically coupled to the complementary bit line BBL. As shown in Figure 35, this can be coupled to the first n-well 1002, the second n-well 1004, the third n-well 1006, and the fourth n-well 1008, respectively Lt; RTI ID = 0.0 > 1028 < / RTI > A plurality of complementary bit line vias 1028 may include a conductive material (e.g., similar to the conductive material of first via 202 described above with respect to FIG. 2). The complementary bit line vias 1028 are connected to a first n-well 1002, a second n-well 1004, a third n-well 1006 and a fourth n-well 1008, To a complementary bit line (BBL) that may be formed in the metallization layer of the array. The complementary bit line BBL may be formed in the same metallization layer as the bit line BL.

In summary, FIGS. 32-35 illustrate an overlapping top down view of the source level S1 of the first active level L1 of the 2x2 array of SRAM cells 100 shown in FIG. FIG. 36 shows the overlapped top-down view of the channel level C1 and the drain level D1 of the first active level L1 of the 2x2 array of SRAM cells 100 shown in FIG. The channel level C1 and the drain level D1 (see FIG. 2) are connected to the first and second drain regions D1 and D2 (see FIG. 2) in which channel regions and drain regions of the pull-down transistors PD1 and PD2 and the pass- May be the level of the active level L1.

The drain region 140 of the second pass-gate transistor PG2 is connected to the channel region of the second pass-gate transistor PG2 for each of the cells 100-1 to 100-4, Lt; / RTI > Then, the channel region of the second pass-gate transistor PG2 may be surrounded by the gate 138 of the second pass-gate transistor PG2. As shown in FIG. 36, the drain region 106 of the first pull-down transistor PD1 is connected to the channel region of the first pull-down transistor PD1 for each of the cells 100-1 to 100-4. Lt; / RTI > The channel region of the first pull-down transistor PD1 may then be surrounded by the gate 104 of the first pull-down transistor PD1. As shown in Fig. 36, the drain region 120 of the second pull-down transistor PD2 is connected to the channel region of the second pull-down transistor PD2 for each of the cells 100-1 through 100-4, Lt; / RTI > The channel region of the second pull-down transistor PD2 may then be surrounded by the gate 118 of the second pull-down transistor PD2. The drain region 134 of the first pass-gate transistor PG1 is connected to the channel region of the first pass-gate transistor PG1 for each of the cells 100-1 to 100-4, Lt; / RTI > Then, the channel region of the first pass-gate transistor PG1 may be surrounded by the gate 132 of the first pass-gate transistor PG1.

As described above with respect to FIG. 2, the gates of pass-gate transistors PG1 and PG2 may be electrically coupled to write line WL. 36, this can be achieved by using a plurality of wordline vias 1030 that can be coupled to the gates 138 and 1332 of the pass-gate transistors PG1 and PG2, respectively. The plurality of wordline vias 1030 may include a conductive material (e.g., similar to the conductive material of the first via 202 described above with respect to FIG. 2). Word line vias 1030 may couple gates 138 and 132 of pass-gate transistors PG1 and PG2 to a word line WL that may be formed in a 2x2 array of metallization layers. Gates of the pull-down transistors PD1 and PD2 are coupled to the gates of the pull-up transistors PU1 and PU2 using the first via 202 and the second via 204, Lt; / RTI > 36 also shows the first via 202 and the second via 204, respectively, of the cells 100-1 through 100-4.

37 shows an overlapping top down view of a 2x2 array of trace levels SL of SRAM cells 100 shown in FIG. 31, in accordance with one embodiment. The trace level SL (see FIG. 2) can be, for example, the level at which the first conductive traces 114 and the second conductive traces 128 are formed. 37, the first conductive traces 114 surround the drain region 106 of the first pull-down transistor PD1 and the drain region 134 of the first pass-gate transistor PG1 The drain region 106 of the first pull-down transistor PD1 and the drain region 134 of the first pass-gate transistor PG1 can be coupled to each other. 37, the second conductive trace 128 is formed between the drain region 120 of the second pull-down transistor PD2 and the drain region 140 of the second pass-gate transistor PG2. The drain region 120 of the second pull-down transistor PD2 and the drain region 140 of the second pass-gate transistor PG2 can be coupled to each other.

Fig. 38 shows a top-down view of the drain level D2 and the channel level C2 overlapping the second active level L2 of the 2x2 array of the SRAM cells 100 shown in Fig. The drain level D2 and the channel level C2 (see FIG. 2) may be, for example, the level of the second active level L2 at which the channel regions and drain regions of the pull-up transistors PU1 and PU2 are formed. As shown in Fig. 38, the channel region 1032 of the first pull-up transistor PU1 is connected to the drain region of the first pull-up transistor PU1 for each of the cells 100-1 to 100-4, (Not shown). The channel region 1032 of the first pull-up transistor PU1 may then be surrounded by the gate 110 of the first pull-up transistor PU1. The channel region 1034 of the second pull-up transistor PU2 is connected to the drain region of the second pull-up transistor PU2 for each of the cells 100-1 through 100-4, (Not shown). The channel region 1034 of the second pull-up transistor PU2 may then be surrounded by the gate 124 of the second pull-up transistor PU2. 2, the gates of transistors PU2 and PD2 may be coupled to the drains of transistors PU1 and PD1 using fourth vias 208 while the gates of transistors PU1, PD1 may be coupled to the drains of the transistors PU2 and PD2 using a third via 206. [ The third via 206 and the fourth via 208 are also illustrated for each of the cells 100-1 through 100-4 in FIG. Gates of the pull-down transistors PD1 and PD2 are coupled to the gates of the pull-up transistors PU1 and PU2 using the first via 202 and the second via 204, Lt; / RTI > 38 illustrates the first via 202 and the second via 204 for each of the cells 100-1 through 100-4.

Figure 39 shows an overlapping top down view of the source level S2 of the second active level L2 of the 2x2 array of SRAM cells 100 shown in Figure 31 according to one embodiment. The source level S2 (see FIG. 2) can be, for example, the level of the second active level L2 at which the source regions of the pull-up transistors PU1 and PU2 are formed. As shown in FIG. 39, each of the cells 100-1 to 100-4 includes a source region 108 of the first pull-up transistor PU1 and a source region 108 of the second pull-up transistor PU2. (Not shown). As described above with respect to FIG. 2, the sources 108 and 122 of the pull-up transistors PU1 and PU2 are coupled to the first power voltage Vdd. As shown in FIG. 39, this can be achieved by forming a first power rail 1036 around each of the sources 108, 122 of the cells 100-1 through 100-4. The first power rail 1036 may include a conductive material similar to the conductive material of the first via 202 and may be electrically coupled to the first power voltage Vdd. 40 shows another embodiment in which the amount of conductive material used to form the first power rail 1036 is reduced.

31-40 may reduce the footprint of SRAM cell 100 and may eventually lead to a reduction in the number of such SRAM cells 100 (such as the 2x2 array shown in Figure 31) The integration density can be increased. For example, the first via 202, the second via 204, the third via 206, and the fourth via 208 may be connected to the pull-up transistors PU1 and PU2, (PD1, PD2), and pass-gate transistors (PG1, PG2), thereby reducing the footprint of the SRAM cell (100).

The foregoing description outlines features of several embodiments in order to enable those skilled in the art to better understand aspects of the disclosure. It should be understood by those skilled in the art that the present disclosure can readily be used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or to achieve the same advantages as the embodiments disclosed herein. Those skilled in the art will recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure and that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure.

Claims (10)

A semiconductor device comprising:
A first pull-down transistor including a first vertical source, a first vertical channel on the first vertical source, a first vertical drain on the first vertical channel, and a first gate electrode around the first vertical channel, ;
A second vertical drain on the first vertical drain, a second vertical channel on the second vertical drain, a second vertical source on the second vertical channel, and a second gate electrode around the second vertical channel A first pull-up transistor;
A first via coupled to the first gate electrode and the second gate electrode;
A first conductive trace having a first portion between the first vertical drain and the second vertical drain;
A first pass-gate including a third vertical source, a third vertical channel on the third vertical source, a third vertical drain on the third vertical channel, and a third gate electrode around the third vertical channel, pass-gate transistor, the first conductive trace having a second portion over the third vertical drain;
A second pull-down transistor including a fourth vertical source, a fourth vertical channel on the fourth vertical source, a fourth vertical drain on the fourth vertical channel, and a fourth gate electrode around the fourth vertical channel, ;
A fifth vertical drain on the fourth vertical drain, a fifth vertical channel on the fifth vertical drain, a fifth vertical source on the fifth vertical channel, and a fifth gate electrode around the fifth vertical channel The second pull-up transistor having the fifth gate electrode having a distal portion extending over a second portion of the first conductive trace;
A second via coupling the fourth gate electrode and the fifth gate electrode;
A second conductive trace having a first portion between the fourth vertical drain and the fifth vertical drain;
A second pass-gate transistor including a sixth vertical source, a sixth vertical channel on the sixth vertical source, a sixth vertical drain on the sixth vertical channel, and a sixth gate electrode around the sixth vertical channel, Wherein the second conductive trace has a second portion over the sixth vertical drain and the second gate electrode has a distal portion extending over the second portion of the second conductive trace, A gate transistor;
A third via for joining said distal portion of said second gate electrode to said second portion of said second conductive trace; And
And a fourth via for coupling the distal portion of the fifth gate electrode to the second portion of the first conductive trace. 2. The transistor of claim 1, wherein the first pass-gate transistor is laterally separated from the first pull-down transistor by a first distance along a first direction,
The second pass-gate transistor is laterally separated from the first pull-down transistor by the first distance along a second direction perpendicular to the first direction,
And the second pull-down transistor is laterally separated from the first pass-gate transistor by the first distance along the second direction. 2. The semiconductor device of claim 1, wherein at least one of the first pull-up transistor or the second pull-up transistor comprises a junctionless vertical transistor. The semiconductor device of claim 1, wherein at least one of the first conductive trace or the second conductive trace comprises a silicide. The semiconductor device of claim 1, wherein the second vertical drain is aligned with the first vertical drain, and the fifth vertical drain is aligned with the fourth vertical drain. The semiconductor device of claim 1, further comprising a word line coupled to the third gate electrode and the sixth gate electrode. The method according to claim 1,
A first n-well, said first vertical source extending from said first n-well;
A second n-well separated laterally by a first distance from the first n-well, the third vertical source extending from the second n-well;
A third n-well separated laterally by said first distance from said second n-well, said fourth vertical source extending from said third n-well; And
And a fourth n-well laterally separated from the first n-well and the third n-well by the first distance, the sixth vertical source extending from the fourth n- 4 n-well. 8. The method of claim 7,
A first power via coupled to the first n-well; And
And a second power via coupled to the third n-well,
Wherein the first power via and the second power via are coupled to the power rail. A semiconductor device comprising:
Down transistor comprises a first gate electrode extending laterally at the first level of activity, the first vertical pull-down transistor at a first level of activity of the semiconductor device, One vertical pull-down transistor;
A first vertical pull-up transistor stacked over the first vertical pull-down transistor, the first vertical pull-up transistor being at a second active level of the semiconductor device, and extending laterally at the second active level; The first vertical pull-up transistor having a second gate electrode coupled to the first vertical pull-up transistor;
A first via coupling the first gate electrode at the first activation level and the second gate electrode at the second activation level;
A first conductive trace disposed between the first vertical pull-down transistor and the first vertical pull-up transistor, the first conductive trace comprising a first vertical pull-down transistor and a first vertical pull- Said drain region of said first conductive trace being coupled to each other;
A second vertical pull-down transistor at the first active level of the semiconductor device, the second vertical pull-down transistor comprising a third gate electrode extending laterally at the first active level, A second vertical pull-down transistor;
A second vertical pull-up transistor stacked on the second vertical pull-down transistor, the second vertical pull-up transistor being at the second active level of the semiconductor device, The second vertical pull-up transistor having a fourth gate electrode extending therefrom;
A second via coupling the third gate electrode at the first activation level and the fourth gate electrode at the second activation level;
And a second conductive trace disposed between the second vertical pull-down transistor and the second vertical pull-up transistor, the second conductive trace comprising a second vertical pull-down transistor and a second vertical pull- The second conductive trace coupling the drain regions of the transistor to each other;
A first vertical pass-gate transistor at the first active level of the semiconductor device, wherein a portion of the first conductive trace extends over a drain region of the first vertical pass-gate transistor, The first vertical pass-gate transistor;
A second vertical pass-gate transistor at the first active level of the semiconductor device, wherein a portion of the second conductive trace extends over a drain region of the second vertical pass-gate transistor, The second vertical pass-gate transistor;
A third via interconnecting a portion of the second conductive trace in contact with the drain region of the second vertical pass-gate transistor and a portion of the second gate electrode extending over the second vertical pass-gate transistor; And
And a fourth via interconnecting a portion of the first conductive trace in contact with the drain region of the first vertical pass-gate transistor and a portion of the fourth gate electrode extending over the first vertical pass-gate transistor Lt; / RTI > In the method,
A first drain region surrounded by a first dielectric layer, a first channel region over the first source region, a first drain over the first channel region and surrounded by a second dielectric layer, and a second drain region surrounding the first channel region, Forming a first vertical transistor comprising a first gate electrode layer, wherein the first gate electrode layer is disposed between the first dielectric layer and the second dielectric layer Step,
A second source region surrounded by the first dielectric layer, a second channel region over the second source region, a second drain region over the second channel region and surrounded by the second dielectric layer, Forming a second vertical transistor comprising a second gate electrode layer around the region, wherein the second gate electrode layer is different from the first gate electrode layer and between the first dielectric layer and the second dielectric layer Said second vertical transistor being disposed on said first vertical transistor,
Forming a third vertical transistor on the first vertical transistor;
Forming a via over the second vertical transistor, wherein the portion of the via is surrounded by a gate electrode of a fourth vertical transistor.

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