KR101829576B1 - Low latency successive cancellation decoder - Google Patents

Abstract

The present invention relates to a low latency successive cancellation decoder. It is possible to shorten a decoding time by transforming the stage of a continuous elimination decoding device according to a code length into grouped merging operation block parts where a merging operation part stores each of operation values according to a combination of a binary signal and a decoded bit. The present invention has an effect that a user can easily design a decoding device by identifying the number of merging operation block parts, reduced decoding time, and outputted decoded bits according to the number of deformation stages. The low latency successive cancellation decoder includes a main frame part.

Description

[0001] LOW LATENCY SUCCESSIVE CANCELLATION DECODER [0002]

More specifically, the present invention relates to a continuous elimination decoding apparatus of a low delay, more particularly, to a stage of a consecutive elimination decoding apparatus according to a code length, in which a further merging operation section in which arithmetic values according to a combination of a binary signal and a decoding bit are stored, And to a low-delay consecutive-cancellation decoding device capable of shortening a decoding time by modifying it into a merge operation block portion.

A technique such as a channel code for converting a signal from a transmission source has been developed so that information transmitted through a channel can be detected and corrected at the receiving side by itself. Polar code is a code capable of achieving channel capacity with a wide binary input discrete memoryless channel (DMC) under the assumption that the length of the code is very long. The polarity code is one of the error correction codes such as turbo code and LDPC, and is composed of an easy decoding process and a simple structure. Many researches are underway to use these pole codes as next generation error correction codes in communication fields such as 5G and wiretap channels.

Korean Patent No. 10-1600759 (hereinafter referred to as " Prior Art Document ") relates to a soft decision forward error correction method and apparatus for a receiver to determine an error occurring in data during a data transmission process in a transmitter in a digital communication system. The prior art is an efficient polynomial decoding device with high data throughput and low hardware complexity through optimization of the main frame and memory based feedback structure by using a one's complement scheme in the design of polar code decoders.

However, as the code length increases, the continuous elimination decoding algorithm has a disadvantage that the decoding performance increases and the decoding time becomes long as it is decoded through not only the long code length but also the feedback of the decoding bit.

Korean Registered Patent No. 10-1583139 (Title: Continuous-canceled code decoding apparatus and method with high throughput and low complexity, registration date: December 30, 2015)

In order to solve the above problems, another merge operation unit in which operation values according to all cases where a combination of a binary signal and a decode bit are stored is stored, and a stage of a consecutive cancellation decoding apparatus is constituted by a grouped merge operation block unit. There is a purpose.

Further, the present invention has an object to identify the number of the merge operation block units, the decode time to be reduced, and the decoded bits to be outputted according to the number of deformation stages.

According to another aspect of the present invention, there is provided a decoding apparatus including a main frame unit for sequentially decoding at least one stage for decoding a code signal input in accordance with a code length and outputting the code signals as decoding bits according to a predetermined decoding order, Wherein the main frame unit comprises a first stage in which at least one merge operation unit for performing a merge operation on the sign signals and determining a binary signal according to the decoding order and outputting an operation value is provided corresponding to the code length, At least one further merging operation unit in which operation values according to all cases in which combinations are possible through the binary signal and the decoding bits are stored, and a merging operation block unit grouped by the merging operation block unit and the deformation stage consisting of the merging operation block unit And a stage determining unit for determining the number of stages.

The number of the merge arithmetic block units constituting the deformation stage is specified according to the order of enumeration of the stages and the number of deformation stages.

The main frame unit further includes a final stage including a decoded bit determiner for deciding a decoded bit of any one of binary numbers according to a likelihood ratio according to a specific computation value to be greater than or less than a preset value, Is changed by the number of the merge operation block units included in the last stage and output.

The low delay consecutive cancellation decoding apparatus according to the present invention further includes a feedback unit for receiving at least one of the decoding bits from the decoding bit determining unit and for transmitting the decoding bits to the initial stage.

The merging operation unit according to the present invention includes a signal operation unit for operating the sign signal using a first function and a second function through different computation methods, a memory unit for storing the first function and the computed values of the second function, And a function selection unit for determining a specific binary signal according to the decoding order and selecting a specific function value of either the first function or the second function according to the specific binary signal.

The merging operation unit included in the initial stage according to the present invention further includes a decoding bit receiving unit for receiving at least one of the decoding bits from the feedback unit.

The present invention is characterized in that a stage of a continuous cancellation decoding apparatus is constituted by another merging operation block unit grouped by another merging operation unit in which operation values according to all cases in which a combination of a binary signal and a decoding bit are possible are stored, It is effective.

Further, the present invention has an effect that the user can easily design the decryption apparatus by identifying the number of the merge operation block units, the decryption time to be reduced, and the decryption bit to be outputted according to the number of deformation stages.

1 is a configuration diagram of a low-delay consecutive elimination decoding apparatus according to the present invention.
2 is a configuration diagram of a merge operation unit according to the present invention.
3 is a diagram for explaining a decoding time and a decoding bit according to the number of deformation stages according to the present invention.
FIG. 4 is a block diagram of a continuous removal decoding apparatus to which a deformation stage according to the present invention is applied.
FIG. 5 is another embodiment for explaining a continuous removal decoding apparatus to which a deformation stage according to the present invention is applied.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

1 is a configuration diagram of a low-delay consecutive elimination decoding apparatus according to the present invention. Referring to FIG. 1, the low-delay consecutive cancellation decoding apparatus may include a main frame unit 1000 and a feedback unit 4000. FIG. 1 is a diagram showing an example in which the code length is 8; FIG.

The main frame unit 1000 is a device for outputting a sign signal as a decoded bit in accordance with a predetermined decoding order. Fig. 1 shows a case where the main frame 1000 is composed of an initial stage, a last preceding stage, and a last stage. Here, a stage is a device for decoding an input sign signal, and at least one stage is sequentially listed according to a code length.

의 식을 통해 결정된다. 여기서 N는 코드길이를 의미한다. 예를 들어 코드길이 N이 8일 경우, 스테이지의 개수는 3이 된다. The sign signal input to the initial stage is proportional to the code length. For example, when the code length is 8, eight code signals are input. In addition, the number of stages is determined according to the code length. The number of stages is

. Where N is the code length. For example, if the code length N is eight, the number of stages is three.

As shown in FIG. 1, the initial stage 1100 includes at least one merge arithmetic unit 2000 that performs a merge operation on a sign signal, determines a binary signal according to a decoding order, and outputs a calculated value, corresponding to the code length. The merge operation unit 2000 has a structure in which two sign signals are received. Therefore, when the sign signal is 8, the first stage 1100 is composed of four merging and arithmetic operation units 2000. When the initial stage is composed of four merging arithmetic units 2000, the next stage 1200 of the first stage has two merging arithmetic units 2000 and the last stage 1300 has one merging arithmetic unit 2000 ). Hereinafter, the next stage 1200 of the first stage is referred to as a second stage for convenience.

The structure of the merge operation unit will be described in detail with reference to FIG. 2, the merge operation unit 2000 may include a signal operation unit 2100, a memory unit 2200, a function selection unit 2300, and a decoded bit receiving unit 2400.

The signal computing unit 2100 is a device for computing a sign signal using a first function and a second function through different computation methods. F signal calculating unit 2110 calculates a first function, and the G signal calculating unit 2120 calculates a second function. When the sign signals a and b are input to the signal operation unit 2100, the F signal operation unit computes a first function c of sgn (a) sgn (b) min (| a |, | b | The signal operation unit calculates the second function (d0, d1) of a + b and ba.

The memory unit 2200 is a device in which arithmetic values of the first function and the second function are stored.

The function selection unit 2300 determines a specific binary signal according to the decoding order and selects a specific function value of either the first function or the second function according to the specific binary signal. The general decoding order is a first function (F function) first, and then a second function (G function). On the other hand, the decoding order can be changed according to the length of the stage. A binary signal of '0' is determined in the decoding order in which the F function is to be performed, and a binary signal of '1' is determined in the decoding order in which the G function is to be advanced. If the binary signal of '0' is determined, the function selection unit 2300 selects the operation value of the first function and transmits it to the next stage. On the other hand, when the binary signal of '1' is determined, the operation value of the second function is selected and transmitted to the next stage.

The decoding bit receiving unit 2400 is a device for receiving at least one decoding bit from the feedback unit 4000. [ The decoded bit is a signal determined by the last stage 1300 and is binary output information that has been decoded.

The stage decision unit 1400 determines the number of deformation stages constituted by the merge operation block unit 3000 among the stages arranged in the main frame unit 1000.

Fig. 1 shows an embodiment in which two stages of deformation are determined by the stage determining section 1400. Fig. Thus, the second stage 1200 and the last stage 1300 are made of deformation stages.

Referring to FIG. 1, the second stage 1200 includes two merging operation block units 3000. The merge operation block unit 3000 is a grouped device of another merge operation unit in which operation values according to all cases where a combination of a binary signal and a decode bit are possible are stored.

The method of determining the number of deformation stages may be determined by the following equation.

[Determination of deformation stage]

denotes the number of deformation stages, and the number of the merging operation block units and the decoding time are determined according to?. MPSBs means the number of merging operation block units.

3 is a table showing the number of merging operation block units according to? And a decoding time. As shown in FIG. 3, the decoded bits outputted when the number of deformation stages is 0 are 2 bits, which is the same as the decoded bits output from the conventional continuous elimination decoding apparatus. When the deformation stage is 1, the output decoded bit becomes 4 bits, and the decoding time is reduced from the existing N-1 to 3/4. As described above, as the deformation stage increases, the output decoded bits gradually increase, and the decode time gradually decreases.

Referring to FIG. 1 again, the merge operation block unit 3000 may include an FF operation unit 3100, a G00 operation unit 3200, a G01 operation unit 3300, a G10 operation unit 3400, and a G11 operation unit 3500. Here, the FF operation unit 3100, the G00 operation unit 3200, the G01 operation unit 3300, the G10 operation unit 3400, and the G11 operation unit 3500 are still another merge operation unit, And outputs the calculated value when the binary signal of the binary signal is determined. The G 00 arithmetic unit 3200 is a device for outputting a computed value when a binary signal of '1' is determined according to a decoding order and a decoded bit is 0 or 0 is input. The G01 arithmetic unit 3300 is a device for outputting a computed value when a binary signal of '1' is determined according to the decoding order and a decoding bit of 0 or 1 is input. The G11 arithmetic unit 3400 is a device for determining a binary signal of '1' according to the decoding order and outputting a computed value when a decoding bit is 1 or 0 is inputted. The G11 arithmetic operation unit 3500 is a device for outputting a computed value when a binary signal of '1' is determined according to a decoding order and a decoding bit of 1 or 1 is input.

As described above, the merge operation block unit 3000 includes another merge operation unit corresponding to the number in all cases according to the combination of the binary signal and the decoded bit, thereby reducing the decoding time. This will be described in more detail with reference to FIG.

In the second stage 1200, the first stage 1100 is composed of four merge arithmetic operation units 2000, so that the merge arithmetic block units 3000 are two.

The final stage 1300 is composed of a total of 17 merging operation block units according to a combination of another merging operation units included in the two merging operation block units 3000. [ The final stage 1300 includes a decoding bit determiner 1310 for determining a decoding bit of any one of the binary numbers according to a likelihood ratio according to a specific computation value that is greater than or less than a predetermined value.

The decoded bits output from the last stage will be described with reference to FIG. Fig. 4 shows an embodiment in which one stage of deformation is constituted by the stage determining section 1400. Fig.

Referring to FIG. 4, the first stage (stage 1) is composed of four merged operation units (Merged PE) upon reception of a total of eight sign signals. The second stage (stage 2) consists of two merging operation units for receiving the first function or the second function from the initial stage. On the other hand, according to the calculation of all the operation values in the last stage (stage 3), the merging operation unit of the second stage does not include a decoding bit receiving unit for receiving the decoding bit and a function selecting unit for determining the binary signal according to the decoding order.

The last stage (stege 3) consists of a merge operation block unit 3000 and generates decode bits u1 and u2 through the FF operation unit 3100 of the merge operation block unit 3000 according to the decode order.

In the case of the conventional continuous cancellation decoding apparatus, the decoding bits u1 and u2 are transmitted to the feedback unit 4000, and the feedback unit 4000 transmits the decoding bits u1 and u2 to the second stage (stage 2). The second stage transmits a second function according to the received decoding bits u1 and u2 to the final stage.

However, the present invention does not transmit the decoded bits u1 and u2 to the second stage (stage 2), and the G00 arithmetic unit to the G01 arithmetic unit (Merged PE (00) to M04) of the merge operation block unit 3000 of the last stage Merged PE 11) to generate information bits u3 and u4. The conventional decoding bits u1 and u2 are transmitted to the feedback unit 4000 and the decoding unit 4000 shortens the decoding time by omitting the process of transmitting the decoding bits u1 and u2 to the second stage.

는 최후스테이지며, stage

는 최후스테이지의 전스테이지를 의미한다. 편의상 최후스테이지는 N스테이지, 전스테이지는 N-1스테이지, 전전 스테이지는 N-2스테이지로 칭한다. 도 5는 N-1스테이지와 N스테이지가 변형스테이지로 구성된 경우로써, N-1스테이지는 2개의 병합연산블록부(MPEB)로 구성된다. Fig. 5 shows another embodiment of the deformation stage according to the present invention, in which the deformation stage is composed of two. Referring to FIG. 5,

Is the last stage, stage

Means the last stage of the last stage. For the sake of convenience, the last stage is referred to as an N stage, the front stage as an N-1 stage, and the pre-stage as an N-2 stage. FIG. 5 shows a case where the N-1 stage and the N stage are composed of the deformation stages, and the N-1 stage is composed of two merge operation block units (MPEB).

N stage includes another merge operation unit for the operation value according to the combination of the FF operation unit MPE (FF) of the first merge operation block unit of the N-2 stage and the FF operation unit MPE (FF) of the second merge operation block unit, 16 arithmetic operations according to combinations between the G00 arithmetic units MPE (G00) to G11 arithmetic units (MPE (G11)) and the G00 arithmetic units MPE (G00) to G11 arithmetic units (MPE Lt; / RTI > Therefore, the N stage consists of 17 other merge operation units. The N stage outputs eight decoded bits.

As shown in FIGS. 4 and 5, the present invention increases the number of output decoded bits as the number of deformation stages increases, thereby reducing the decoding time. On the other hand, the present invention is not limited to the number of deformation stages shown in Figs. 4 and 5, and the number of deformation stages can be increased or decreased by the user.

1000: Main frame part 1100: Initial stage
1200: Second stage 1300: Last stage
1310: Decoding bit determiner 1400:
2000: merge operation unit 2100: signal operation unit
2110: F signal operation unit 2120: G signal operation unit
2200: memory unit 2300: function selection unit
2400: decoding bit receiving section 3000: merging operation block section
3100: FF operation unit 3200: G00 operation unit
3300: G01 computing unit 3400: G10 computing unit
3500: G11 computing unit 4000: feedback unit

Claims (6)

And a main frame unit for sequentially outputting at least one stage for decoding a code signal inputted in accordance with a code length and outputting the code signal as a decoded bit according to a predetermined decoding order,
The main frame portion
An initial stage in which at least one merge operation unit for performing a merge operation on the sign signal and outputting a calculated value is provided corresponding to the code length;
A binary signal of either '0' or '1' decoded in the previous stage and a binary signal At least one further merging operation unit in which operation values according to all possible cases of combining through decoding bits are stored, respectively;
And
And a stage determining unit for determining the number of deformation stages constituted by the merging operation block unit among the listed stages.
The method according to claim 1,
And the number of the merging operation block units constituting the deforming stage is specified according to the order of arranging the stages and the number of the deforming stages.
3. The method of claim 2,
The main frame unit further includes a final stage including a decoded bit determining unit for determining a bit value of the decoded bit corresponding to the number of the deformation stages according to a likelihood ratio according to a specific computation value that is greater than or less than a preset value However,
Wherein the decoding bits are changed by the number of the merge operation block units included in the last stage and output.
The method of claim 3,
The low-delay consecutive elimination decoding apparatus
Further comprising a feedback unit for receiving at least one of the decoding bits from the decoding bit determining unit and for transmitting the decoding bits to the initial stage.
5. The apparatus of claim 4, wherein the merging operation unit
A signal operation unit for operating the sign signal using a first function and a second function through different arithmetic operations;
A memory unit in which operation values of the first function and the second function are stored; And
A function selecting unit for determining a specific binary signal among the binary signals of '0' or '1' according to the decoding order and selecting a specific function value of either the first function or the second function according to the specific binary signal Delay decoding unit.
6. The method of claim 5,
Wherein the merging operation unit included in the initial stage further includes a decoding bit receiving unit for receiving at least one of the decoding bits from the feedback unit.

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