JPH07162319A - Error correcting circuit - Google Patents

Abstract

PURPOSE:To execute soft decision decoding by a simple circuit configuration and to obtain a high correction effect for a receiver, a reader, etc., in a transmission system or a recording system using a code to be decoded by a majority logic circuit by applying a trellis decoding method to be easily applied to a soft decision decoding method to a code to be decoded by majority logic. CONSTITUTION:A difference set circulating code is fetched by an n-bit shift register circuit 4 (21, 11) and shifted to generate data S1 to Sm and the data S1 to Sm outputted from the circuit 4 are fetched through a branch metric comparing circuit 5, two addition circuits 6 and a decision circuit 7 and the difference set circulating code is decoded by majority logic decoding using a Tolleris diagram (21, 11).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is an apparatus for transmitting and recording digital signals such as digital receivers for TV multiplex character broadcasting, FM multiplex broadcasting, satellite data channels, etc., and optical card readers. The present invention relates to an error correction circuit that corrects an error in a majority logic decodable code used.

SUMMARY OF THE INVENTION The present invention is based on a majority decision logic among error correction codes (block codes) for correcting a bit error of a digital signal generated in digital transmission, digital recording, etc. by performing a certain kind of operation in block units. The present invention relates to an error correction circuit that decodes a code that can be decoded by a circuit, and significantly improves error correction capability by performing an operation using a trellis diagram in the operation unit of the syndrome register circuit.

[0003]

2. Description of the Related Art A system for decoding a majority logic decodable code used in a device such as a digital receiver for TV multiplex character broadcasting, FM multiplex broadcasting, satellite data channels, etc., or an optical card reader device, has been conventionally described. Fairness 3-76612
(Japanese Patent Application No. 58-6579), Japanese Patent Publication No. 2-111
There is known a method of improving the correction effect by varying the threshold value as disclosed in Japanese Patent Application No. 84-54002.

As another decoding method, for example,
As a method (soft decision decoding method) for decoding an input signal using digital values of "1" and "0", APP (A Posterior
Probability) decoding method has been proposed (JLMassey
“Threshold decoding” Cambridge Massachusetts MIT P
ress (1963)).

A Viterbi decoding method using a trellis diagram has been proposed as a decoding method for codes other than the above-mentioned codes, for example, a convolutional code.

[0006]

However, the above-mentioned conventional decoding methods have the following problems.

That is, Japanese Patent Publication No. 3-76612,
In the method of varying the threshold value to improve the correction effect as disclosed in Japanese Patent Publication No. 2-11184, it is possible to deal with digital data such as "1" or "0" as an input signal. Although possible, there is a problem that it cannot be applied to the soft-decision decoding method in which the input signal is an analog value or a digital value of multiple bits.

Further, since the APP decoding method is based on the soft-decision decoding method, the error correction capability can be improved as compared with the above-mentioned variable threshold method, but the decoding method is complicated, so that the apparatus There was a problem that it was difficult to realize.

Further, the Viterbi decoding has a problem that it can be used for decoding a convolutional code but cannot be applied to a code capable of majority logic decoding, for example, a block code.

In view of the above circumstances, the present invention can perform soft-decision decoding with a simple circuit configuration by applying the trellis decoding method, which is easy to apply to the soft-decision decoding method, to a code capable of majority logic decoding. Therefore, it is an object of the present invention to provide an error correction circuit that can obtain a high correction effect in a receiver of a transmission system or a recording system using a code that can be decoded by a majority logic circuit, a reader, or the like.

[0011]

In order to achieve the above object, an error correction circuit according to the present invention takes in a code capable of majority logic decoding and shifts it to shift the data S _{1 to} S _m.
And a decoding circuit for taking in the data S _{1 to} S _m output from the shift register circuit and for decoding a majority-decision-logic decodable code input by majority-logic decoding using a trellis diagram. It is characterized by having and.

[0012]

In the above configuration, the shift register circuit takes in a code capable of majority logic decoding and shifts it to generate the data S _{1 to} S _m , and
The decoding circuit takes in the data S _{1 to} S _m output from the shift register circuit, and decodes the inputted majority logic decodable code by the majority logic decoding using the trellis diagram.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a kind of code which can be majority-decodable by using an embodiment of an error correction circuit according to the present invention (2
1 and 11) is a block diagram illustrating an example of an error correction circuit that decodes a difference set cyclic code while performing error correction.

The error correction circuit 1 shown in FIG.
A / D conversion circuit 2, a switch circuit 3, an n-bit shift register circuit 4, a branch metric comparison circuit 5, two adder circuits 6 and a decision circuit 7 are provided, and the majority logic decodable code is provided. One kind of (21,11) difference set cyclic code is taken in, and this is shifted while A / D converting, and the data S ₁ to
While correcting errors of the (21, 11) a difference set cyclic code by performing a majority logic decoding using a trellis diagram with respect to S _21, decodes it.

The sample A / D conversion circuit 2 samples the received analog type (21, 11) difference set cyclic code at an appropriate clock speed and quantizes the digital signal into a digital value of several bits (n bits). It is generated and supplied to the switch circuit 3.

The switch circuit 3 is provided with a switch that can be switched between a signal input operation and a correction operation. During the signal input operation, the n-bit digital signal output from the sample A / D conversion circuit 2 is taken in. Then, this is supplied to the n-bit shift register circuit 4, and at the time of the correction operation, the feedback value output from the decision circuit 7 is fetched and supplied to the n-bit shift register circuit 4.

The n-bit shift register circuit 4 is a circuit for shifting and accumulating the quantized digital signal while taking in the quantized digital signal. The n-bit shift register circuit 4 shifts while taking in the digital signal output from the switch circuit 3 and shifts from the first to 21st. The data S _{1 to} S ₂₁ each having a data length of n bits corresponding to each of the th address are generated, the data S _{1 to} S ₂₀ are supplied to the branch metric comparison circuit 5, and the data S ₂₁ is determined.
Supply to.

The branch metric comparator circuit 5 is provided with 20 branch metric comparators 9 arranged in 5 stages, which are connected in cascade to form a syndrome register circuit for the n-bit shift register circuit 4. The branch metric comparators 9 take in the data S _{1 to} S ₂₀ output from the n-bit shift register circuit 4, respectively, and perform a comparison process using a trellis diagram to obtain the comparison results in the comparison circuits 6, respectively. , Supply.

In this case, each branch metric comparator 9 outputs preset data S _j (where _j is among the data S _{1 to} S ₂₀ output from the n-bit shift register circuit 4 as shown in FIG. 2). = 1, ..., 20) and one of the squared Euclidean distance calculation circuits 10 for calculating the Euclidean distance between the data S _j and the “0” level, and the data S _j and “1”. From the other squared Euclidean distance calculation circuit 11 for calculating the Euclidean distance with the level, and from one output terminal of the other Euclidean distance squared Euclidean distance calculation circuit 11 and the branch metric comparator 9 in the front row Output sum (however, in the leading branch metric comparator 9,
"0"), the Euclidean distance output from the one squared Euclidean distance calculation circuit 10 and the sum output from the other output terminal of the branch metric comparator 9 in the preceding column (however, Leading edge metric comparator 9
In addition, the adder 13 for adding "0") is compared with the sum output from each of the adders 12 and 13, and the comparison circuit 14 for selecting the one having the smaller value and outputting this as the sum. It has and.

Further, each of these branch metric comparators 9
Is the sum of the Euclidean distance output from the one squared Euclidean distance calculation circuit 10 and the output from one output terminal of the branch metric comparator 9 in the preceding column (however, in the leading branch metric comparator 9, “0 ”), The Euclidean distance output from the other squared Euclidean distance calculation circuit 11 and the sum output from the other output terminal of the branch metric comparator 9 in the preceding column (however, In the branch metric comparator 9, "0")
And an adder 16 for adding
The comparison circuit 17 compares the sums output from 6 and selects the one with the smaller value and outputs the sum as the sum.

Then, each branch metric comparator 9 in the first column
, "0" is taken in, and the branch metric comparators 9 in the second to fourth columns take in the outputs on the corresponding sides of the branch metric comparators 9 in the previous row. Furthermore, n
Data S ₁ output from the bit shift register circuit 4
~ S ₂₀ is taken in to calculate the Euclidean distance from the “0” level and the Euclidean distance from the “1” level, and each of these Euclidean distances,
The outputs on the corresponding side of the front row are added to select the smaller sum, and this is output from the output terminal on the corresponding side, or the input terminal on the corresponding side of the branch metric comparator 9 in the rear row, or They are supplied to the adder circuits 6 on the corresponding sides.

In FIG. 2, the "0" level is expressed as "-1" and the "1" level is expressed as "+1".

Each adder circuit 6 takes in the sum output from the output terminal on the corresponding side of each branch metric comparator 9 in the last column, adds them, and calculates the sum. Is supplied to the input terminal on the corresponding side of the decision circuit 7.

The decision circuit 7 takes in the data S ₂₁ output from the n-bit shift register circuit 4 as shown in FIG. 3 and calculates the Euclidean distance between the data S ₂₁ and the "0" level, which is one of the squared Euclidean signals. The distance calculation circuit 20, the other squared Euclidean distance calculation circuit 21 for calculating the Euclidean distance between the data S ₂₁ and the “1” level, and the other squared Euclidean distance calculation circuit 2
The Euclidean distance output from 1 and the sum total output from the one adder circuit 6 are added, and the adder 22 that outputs the addition result A and the one square Euclidean distance calculation circuit 20 are output. The Euclidean distance and the sum total output from the other adder circuit 6 are added, and the adder 23 that outputs the addition result B and the addition results A and B output from the adders 22 and 23 are added. Compare
If “A ≧ B”, “0” is generated, and if “A <B”, “1” is generated, and this is output to the output terminal. The input signal is back-calculated, and if necessary, appropriate scaling is performed to adjust the value to generate a feedback value, which is used as the switch circuit 3
And a comparator 24 for returning to the.

Then, the data S ₂₁ output from the n-bit shift register circuit 4 is taken in, the Euclidean distance from the "0" level and the Euclidean distance from the "1" level are calculated, and these Euclidean distances are calculated. When,
The sums output from the adder circuits 6 are added to obtain addition results A and B, and the addition results A and B are compared. If “A ≧ B”, “0” If "A <B", then "1" is generated, this is output to the output terminal, the input signal is back-calculated from the values of the respective addition results A and B, and this back-calculation result is obtained. On the other hand, if necessary, appropriate scaling is performed to adjust the value, and this value is returned to the switch circuit 3 as a feedback value.

As described above, in this embodiment, a (21,11) difference set cyclic code, which is one type of code capable of majority logic decoding, is taken in, and this is shifted while A / D converting, and this shift operation is performed. Data obtained by S
While by performing majority logic decoding using trellis diagram corrects an error of the (21, 11) a difference set cyclic code with respect to ₁ to S _21, since so as to decode it, with a simple circuit configuration Soft-decision decoding can be performed, whereby a high correction effect can be obtained in a receiver or reader of a transmission system or a recording system that uses a code that can be decoded by a majority logic circuit.

In the above embodiment, the branch metric comparator 9 and the decision circuit 7 use the squared Euclidean distance to determine the branch metric. The squared Euclidean distance calculation circuits 10 and 11 and the squared Euclidean distance calculation circuits 20 and 21 of the decision circuit 7 are changed to other calculation circuits,
The branch metric may be determined using a value other than the squared Euclidean distance.

Further, in the above-described embodiment, only one n-bit shift register circuit 4 is used, but two such n-bit shift register circuits 4 are used.
One may be prepared, and the calculated value of the distance from the "0" level may be pre-calculated in one side and the calculated value of the distance from the "1" level may be pre-calculated in the other side.

As a result, the respective Euclidean distances output from the respective n-bit shift register circuits 4 are converted into the respective adders 12, 13, 15, 1 of the branch metric comparator 9.
6, can be directly input to the respective adders 22 and 23 of the decision circuit 7, whereby the squared Euclidean distance calculation circuits 12, 13, 15, 16 of the branch metric comparator 9 and the decision circuit 7 of the decision circuit 7 can be directly inputted. Each squared Euclidean distance calculation circuit 22,
23 can be omitted.

In the above embodiment, the threshold value of the decision circuit 7 is fixed and the comparison process is performed.
Introducing a certain positive number as a threshold, each adder circuit 22,
When the difference between the addition results A and B obtained in step 23 is equal to or greater than the threshold value, correction is performed, and the threshold value is changed as necessary. You may make it perform a comparison process.

Further, in the above-described embodiment, the branch metric comparison circuit 5 is constructed by forming five stages of circuits in which each branch metric comparator 9 is cascade-connected in units of 4 units. As a method, for example, one branch metric comparator 9 may be repeatedly used. In addition, when performing comparison, the n-bit shift register circuit 4
The bit content of the data S _{1 to} S ₂₁ output from is “1”
It is also possible to perform the comparison calculation only when it is close to or when it is close to “0”, thereby reducing the number of calculations.

Further, in the above-described embodiment, the "0" level and the "S" of all the data S _{1 to} S ₂₁ output from the n-bit shift register circuit 4 by the branch metric comparator 9 and the decision circuit 7 are set. 1 "although to perform a comparison operation between the level, bits of data S ₁ to S ₂₁ outputted from the n-bit shift register circuit 4 is" what value close to 0 "" value or close to "1 It is also possible to select a fixed number of to perform the comparison operation, or to limit the value close to “0” or “1” to a fixed number for each check sum matrix.

As a result, the operation time required for the comparison operation can be greatly shortened and the operation speed of the error correction circuit 1 as a whole can be improved.

[0034]

As described above, according to the present invention, by applying the trellis decoding method, which can be easily applied to the soft-decision decoding method, to the code capable of majority logic decoding, the soft-decision decoding can be performed with a simple circuit configuration. As a result, a high correction effect can be obtained in a receiver of a transmission system or a recording system using a code that can be decoded by the majority logic circuit, a reader, or the like.

[Brief description of drawings]

FIG. 1 is a kind of code capable of majority logic decoding using an embodiment of an error correction circuit according to the present invention (21, 1).
1) A block diagram showing an example of an error correction circuit that decodes a difference set cyclic code while performing error correction.

FIG. 2 is a block diagram showing a detailed circuit configuration example of each branch metric comparator shown in FIG.

FIG. 3 is a block diagram showing a detailed circuit configuration example of a decision circuit shown in FIG.

[Explanation of symbols]

1 error correction circuit 2 sample A / D conversion circuit 3 switch circuit 4 n-bit shift register circuit (shift register circuit) 5 branch metric comparison circuit (decoding circuit) 6 adder circuit (decoding circuit) 7 decision circuit (decoding circuit)

[Procedure amendment]

[Submission date] December 10, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

[Figure 3]

Front page continuation (72) Inventor Satoshi Yamada 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Japan Broadcasting Corporation Broadcasting Technology Laboratory

Claims (7)

[Claims] 1. A code capable of majority logic decoding is loaded,
A shift register circuit for generating data S ₁ to S _m by shifting this data S ₁ to S output from the shift register circuit
An error correction circuit comprising: a decoding circuit that takes in _m and decodes a majority-logic-decoding code that is input by majority-logic decoding using a trellis diagram. 2. The error correction according to claim 1, wherein when the decoding circuit calculates a trellis diagram, an analog value to which a squared Euclidean distance is applied or a digital value of a plurality of bits is used as a metric which is a value of each branch. circuit. 3. The error correction circuit according to claim 1, wherein the decoding circuit returns the calculation result of the already decoded bits to the input side of the shift register circuit and corrects the bits inputted thereafter. . 4. The decoding circuit according to claim 1, wherein the decoding circuit sets a threshold value to perform decoding, and changes the threshold value as necessary to enhance error correction capability. The error correction circuit according to any one. 5. The error correction circuit according to claim 4, wherein the decoding circuit varies a threshold value between a preset positive value and zero. 6. The decoding circuit performs an operation only on data having a fixed number of values close to “0” or “1” among the data S _{1 to} S _m output from the shift register circuit. 5. The error correction circuit according to any one of 5 to 5. 7. The decoding circuit, when calculating a trellis diagram, calculates only for each check sum matrix having a constant number of values close to “0” or “1”. 6. The error correction circuit according to any one of 6 above.