JP3452725B2 - Trellis soft decision error correction circuit and trellis variation adjustment method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trellis soft-decision error correction circuit and a trellis variation adjustment method, and in particular, by allowing a delay to a main functional block constituting the error correction circuit, error correction can be performed at high speed. Related to the technology that constitutes the circuit to be performed.

The present invention is applicable to, for example, TV multiple character broadcasting, FM.
For error correction circuits that perform error correction for majority logic decodable codes used in devices that transmit and record digital signals, such as digital receivers for multiple broadcasts and satellite data channels, and readers for optical cards. It is suitable.

In particular, according to the present invention, among the error correction codes (block codes) for performing a certain kind of operation in block units to correct the bit error of the digital signal generated in digital transmission, digital recording, etc., majority logic decoding is possible. The present invention relates to a trellis soft decision error correction circuit for decoding a code.

[0004]

2. Description of the Related Art A basic configuration example of a conventional trellis soft-decision error correction circuit of this type inputs a binary signal of m (> 1) bit width from a received word input terminal 100, as shown in FIG. n × m-bit shift register 10 and J (orthogonal composite parity check sum) trellis calculation circuits 2
0, the threshold control circuit 40, the error determination unit 30, and the output signal (error determination output) 30 from the error determination unit 30.
An output processing unit 50 for converting 0 into a desired binary output, and an error determination output 300 is fed back to the received word input terminal of the shift register (Kuroda et al .: Japanese Patent Application No. 5-3030).
03).

At this time, the configuration or function of each part is roughly as follows.

FIG. 2 showing the configuration of a conventional trellis calculation circuit.
, The trellis calculation circuit 20 includes J-thresholds taken from different positions of the shift register 10 respectively.
One m-bit signal is input.

The following Table 1 and Tables 2 to 5 show (273,191) difference set cyclic codes and (1057,8), respectively.
13) Complex parity check sum (CPC) of the difference set cyclic code
(S) is an example in which the bit position of the shift register used to calculate A _i is counted from the reception word input end side of the shift register (S _i is the i-th register output as seen from the reception word input end). Represent).

[0008]

[Table 1]

[0009]

[Table 2]

[0010]

[Table 3]

[0011]

[Table 4]

[0012]

[Table 5]

The trellis calculation circuit 20 has a function of m by connecting, for example, J-2 arithmetic units 27 in series.
It has a function of calculating and accumulating the square of the difference from the minimum signal value 0 of the bit signal and the square of the difference from the maximum signal value I _max (= 2 ^m −1) as a branch scale (metric). The accumulation result of each trellis calculation circuit 20 is two intermediate results I0.
(I) and I1 (i) are output from the intermediate result output terminal 31 (1 ≦ i ≦ J).

Each arithmetic unit 27 comprises a squaring circuit 22, a difference squaring circuit 23, four adding circuits 24, two minimum value circuits 25, and an output determining circuit 26. Each arithmetic unit 27 has one m-bit input and two 2 m
It has a bit input and two 2m bit outputs. In the first-stage arithmetic unit 27-2, S _i2 is input to the m-bit input, and the square circuit 22-1 is input to the two 2 m-bit inputs.
And (S _i1 ) ² and (I _max −S _i1 ) ² are input as initial values from the difference square circuit 23-1. Where I
_max = 2 ^m -1, and S _ij is the composite parity check sum A
The register output of the shift register 10 used to calculate _i is shown. Further, for convenience, in the following, the 2m-bit input of the one inputting (S _i1 ) ² is the 0 (zero) side input, (I _max −
The method of inputting S _i1 ) ² is called the 1 (side) input.

The two outputs I0 (i, i,
The calculation procedure of 1) and I1 (i, 1) will be described below by taking the arithmetic unit 27-2 at the first stage as an example.

(Example of calculation procedure of first-stage arithmetic unit)

[0017]

## EQU1 ## A = min ((S _i1 ) ² + (S _i2 ) ² , (I _max −S _i1) ² + (I
_max −S _i2) ² ) B = min ((S _i2 ) ² + (I _max −S _i2) ² , (S _i1 ) ² + (I _max −S
_i2) ² ) if (A ≧ B) then I0 (i, 1) = A−B I1 (i, 1) = 0 else I0 (i, 1) = 0 I1 (i, 1) = B−A The signal A is output from one minimum value circuit 25-2-1, and the signal B is output from the other minimum value circuit 25-2-2. The calculation below the above if is performed by the output determination circuit 26.
-2.

Arbitrary arithmetic unit 27-j of the second and subsequent stages
, S _ij for the m-bit input, I0 (i, j−1) for the 0-side input of the two 2m-bit inputs, and 1
Except that I1 (i, j-1) is added to the side input, the same calculation as in the calculation procedure example of the above-mentioned first-stage arithmetic unit is performed.

The output of the trellis calculation circuit 20 is the output of the arithmetic unit 27- (J-1) at the final stage, and I0 (i) = I0 (i, J-2) I1 (i) = I1 (i, J-2).

FIG. 3 showing a configuration example of the conventional error determination unit 30.
Referring to, the error determination unit 30 determines that the two summing circuits 32
-1, 32-2 and two square circuits 34-1, 34-2
, Two adder circuits 35-1 and 35-2, and a subtractor circuit 3
It has 5-3, a D value calculation circuit 36, a comparison circuit 37, and a determination circuit 38. D value calculation circuit 36 and comparison circuit 37
And the decision circuit 38 constitute an error decision basic unit 30 '.

The calculation performed by the error determination unit 30 can be shown as follows.

(Calculation by the error determination unit)

[0023]

[Equation 2]

The summing circuit 32 calculates the sums of I0 (i) and I1 (i) calculated by the J trellis calculating circuits 20. For each of the calculated sums, (S _n ) ² and (I _max −S _n ) ² are calculated for the nth bit of the syndrome register (final bit output S _n of the shift register 10) using the squaring circuit 34. In addition, the above signals A and B are obtained.

The subtractor 35-3 is a circuit for calculating C (= AB). The comparison circuit 37 calculates the absolute value of C | C |
Threshold input circuit 3 supplied from the threshold control circuit 40
It is a circuit that compares the threshold value TH added from 9 and generates a control signal F according to the magnitude relation. The D value calculation circuit 36 is a circuit that generates the signal D shown in the above equation (* D) using the values of C and I _max . The determination circuit 38 is
This is a circuit that switches the signals D and E (= S _n ) according to the level of the control signal F to generate the feedback signal 300. The error correction basic unit 30 ′ is a part of the function of the error determination unit 30 that performs the arithmetic operations after the above equation (* D).

The output processing section 50 of FIG.
Is a circuit that outputs a binary output to the decoding output terminal 200 by applying an appropriate threshold value to

[0027]

Generally, the throughput of a signal processing device (the amount of signal that can be processed in a unit time: in this case, the number of received words that can be decoded per unit time) is different from the register output in the circuit or the same. The smaller the number of logic elements existing in the signal path to the register input, the larger (higher speed). In the case of the trellis soft decision error correction circuit shown in FIGS. 1, 2 and 3, the shift register 10
Trellis calculation unit 20
Since the number of logic elements in the signal path returning to the input of the shift register 10 via the error determination unit 30 increases with the code length n, for example, (273,191) difference set cyclic code or (1057,813) difference set cyclic code. As described above, there is a problem to be solved that it becomes difficult to operate the trellis soft decision error correction circuit at a practical speed as the code length increases.

As a general means for solving the problem in realizing a circuit of this kind, a method of dividing a signal path between registers, which is a factor limiting the speed, and newly inserting a register at the dividing point. (So-called pipeline). However, in general, when the signal path to be divided is a feedback loop as described above, this pipelined method causes a time lag between the timings of data groups to be used for signal processing. It cannot be applied without some compensation measures to avoid the occurrence of

The present invention has been made in view of the above points, and an object thereof is to be used for signal processing when the feedback path in the above trellis soft decision error correction circuit is pipelined. To provide a circuit configuration method of a delay correction type trellis soft-decision error correction circuit having an effective compensating means for avoiding a time lag of timing between data groups, and an error compensating method of a trellis calculation associated therewith. It is in.

[0030]

In order to achieve the above object, the present invention has the following constitution.

(1) In order to realize a high-speed error correction circuit, the trellis calculation section and the error determination section are set with a delay in units of an appropriate clock cycle (data transfer clock).

(2) The generation of the feedback signal is delayed by allowing a delay inside the error correction circuit as described above. Therefore, this feedback signal is delayed not by the signal input stage of the shift register, but by being delayed by an amount considering the required delay of feedback signal generation. Hereinafter, this is called delay correction.

(3) When this delay correction is performed, the signal to be originally returned does not arrive at the register between the first bit of the shift register and the stage immediately before the register to which the feedback signal is input. As a result, the output of the trellis calculation unit that uses these register outputs that do not have originally expected values for the calculation includes an error. These errors are compensated for in the trellis variation adjustment unit inserted between the trellis calculation unit and the error determination unit.

More specifically, the trellis soft decision error correction circuit of the present invention receives a binary signal having an m (m> 1) bit width as an input and decodes a code capable of majority logic decoding with a code length n. In the error correction circuit, m is a unit of a shift register having a determination result input terminal fed back to the β-th (β> 1) register from the received word input end, and a data transfer clock from the shift register to the trellis calculation circuit. _It has a trellis calculation unit that delays by _one clock and outputs the calculation result, and an error determination unit that delays by m ₂ clocks in units of the data transfer clock from the shift register to the trellis calculation circuit and outputs the calculation result.

As one form of the present invention, the constants of m ₁ , m ₂ and β are such that m ₂ is a positive integer and m ₁ = α.
× m ₂ , α = 0 or a positive integer, β = α + 2 or β =
(Α + 1) × m ₂ +1. Further, the error determination unit monitors the feedback signal to the shift register while
A trellis variation adjusting unit for compensating an error with the trellis soft decision error decision circuit in the case of = 1. When the trellis variation adjusting unit sets the i-th register output counted from the received word input terminal of the shift register to S _i ,

[0036]

[Outside 5]

Is set to a value 0 (minimum signal value of m-bit signal) at the time of error correction operation, and while monitoring the feedback signal of every clock, if necessary.

[0038]

[Outside 6]

Amplitude limiting operation and exchange operation are performed. Further, the amplitude limiting operation of the trellis variation adjusting unit is performed by the maximum signal value I _max (2 ^m −1) of the m-bit signal, the feedback signal I _fb ,
When the absolute value operation is represented by |. |, The output signal value of the trellis calculation circuit is limited to I _max × | I _max −2 × I _fb | When the operation is I _th = (I _max +1) / 2, I
It can be characterized by an operation of exchanging the two outputs of the trellis calculation circuit when _fb ≧ I _th .

The trellis variation adjustment method of the present invention is
When the i-th register output counted from the received word input terminal of the shift register is S _i ,

[0041]

[Outside 7]

Is set to a value 0 (minimum signal value of m-bit signal) at the time of error correction operation, and if necessary while monitoring the feedback signal of every clock.

[0043]

[Outside 8]

There is a step of performing an amplitude limiting operation and an exchange operation. In the step of performing the amplitude limiting operation, the maximum signal value I _max (2 ^m −1) of the m-bit signal, the feedback signal I _fb , and the absolute value operation. Is represented by | · |, the output signal value of the trellis calculation circuit is limited to I _max × | I _max −2 × I _fb | or less, and I _th = (I
_{When max} +1) / 2, when I _fb ≧ I _th , an operation of exchanging two outputs of the trellis calculation circuit is executed.

[0045]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 4 shows a basic configuration for a majority logic decodable code having a code length n and the number J of orthogonal composite parity check sums in an embodiment of a delay correction type trellis soft decision error correction circuit according to the present invention. Show.

The delay correction type trellis soft decision error correction circuit shown in FIG. 4 has a received word input terminal 10 of m (> 1) bit width.
0, the shift register circuit 10, and the trellis calculator 20
The error determination unit 30, the threshold control circuit 40, the output processing unit 50, and the decoding output terminal 200 are provided, and the error determination unit 30 includes the trellis variation adjustment unit 60 and the error determination basic unit. And part 30 '.

The shift register circuit 10 is composed of at least (n + α) × m × m ₂ bits of registers, and as shown in FIG. 5A, all m-bit registers of (n + α) × m ₂ are included. Connect them in series or, as shown in FIG. 5 (b), set the m-bit register to n + α.
It is configured by using m ₂ pieces connected in series in parallel. Here, m ₂ is the signal delay inside the error determination unit 30 expressed by the number of clocks (a positive integer), α is 0 or a positive integer, and the signal delay in the trellis calculation unit 20 is Be m ₁ and α = m ₁ / m ₂
Shall be However, when using the structure of (b) in FIG. 5, _two different received word m type in parallel, when using the configuration of FIG. 5 (a), previously m ₂ given order received word of Shall be supplied while switching.

The shift register circuit 10 receives only n × m ₂ clock periods (in the case of the configuration of FIG. 5A) or m clock periods (in the case of the configuration of FIG. 5B) from the start of decoding. Received word data is read from the word input terminal 100 in synchronization with a clock (data transfer clock).
Here, the shift register circuit illustrated in FIG. 5B is 1 / m less than the shift register circuit illustrated in FIG.
Driven at _twice the clock but, m ₂ by the switch circuit
By switching the register data in a fixed order, the data transfer rate to the trellis calculation unit 20 becomes the same in any case.

The following clock as a unit of delay is assumed to be the clock used for data transfer from the shift register circuit 10 to the trellis calculation unit 20. After the input of the received word to the shift register is completed and before the decoding operation is completed, the error determination unit 30 is input to the shift register circuit 10.
Output (feedback signal) 300 of the shift register circuit 10
It is fed back to the β-th register input of. Here, β is (α + 1) × m _{2 in} the configuration of FIG.
In the configuration of FIG. 5B, α is +2 for each of the m ₂ shift registers configured in parallel. In the case of the latter, the error determination unit 30 while maintaining a certain order in each α + 2th register of the shift register.
Output 300 of

The trellis calculation unit 20 is composed of, for example, J trellis calculation circuits shown in FIG.

Since there is a delay in the trellis calculation unit 20 and the error determination unit 30 as described above, the feedback signal 300 is
As compared with the conventional circuit of FIG. 1, it is generated with a certain delay. The feedback signal 300 generated in this way is not a received word input end (first bit) of the shift register circuit 10 but a trellis calculation in order to prevent an error during decoding as an error determination circuit from propagating backward. It is necessary to shift backward by β, which is an amount corresponding to the delay of the unit 20 and the error determination unit 30, to be fed back. This is called delay correction.

Kuroda et al. Of the prior art: Japanese Patent Application No. 5-30
The configuration disclosed in No. 3003 corresponds to the case of β = 1. On the other hand, the present invention is intended for the case of β> 1.

When the delay correction is performed, the data to be originally input arrives at the register located before the β-th register from the received word input end of the shift register (closer to the received word input end). For this reason, an incorrect result will appear in the result of the trellis calculation unit 20 that uses these register data, and the decoding will not be performed correctly, for the following reason.

(Situation of defect at delay correction)
When the k-th register counted from the received word input terminal of the shift register circuit 10 or the output of that register is S _k , at the time of delay correction,

[0056]

[Outside 9]

There is no new signal input ^{* 1)} . Originally, what these values take depends on the circuit configuration method, but here, for simplicity, a significant feedback signal ^{* 2)}

[0058]

[Outside 10]

At subsequent times, it is assumed that these register groups are reset to the minimum signal value 0 ^{* 3).}
Then, the problem in this case is that in the trellis calculation circuit of FIG. 2, some failures occur when some of the inputs are stuck at 0. Trellis calculation circuit sees when the input number of odd and even closer to the I _max to the macro, the two outputs I0
And I1 operate so as to be inverted. Therefore, when the value of the input fixed to 0 (stacked with 0) is close to I _max , not only an error occurs in the output of the trellis calculation circuit, In some cases, a problem occurs that the values of I0 and I1 are inverted.

* 1), * 2): In this type of error correction circuit, all the n-bit received word data are stored in the shift register before starting a series of decoding operations for the received word of code length n. There is a need to. The feedback signal 300 calculated by the error determination unit 30 at the stage when all the received words are stored in the shift register corresponds to the determination result of right or wrong with respect to a certain reference bit (S _n ). The value of the feedback signal 300 is fed back to an appropriate position of the shift register circuit 10 as a new value of S _n when the received word, that is, the shift register circuit 10 is cyclically shifted. As described above, the operation of the shift register 10 includes a storage period of received words and a sequential decoding operation period of received words. The period when there is no new signal input in the text is
The above-mentioned successive decoding operation period, and the significant feedback signal is the feedback signal 300 generated in the above-mentioned period.

* 3): It is not desirable that the input of the register is indefinite from the viewpoint of stable operation of the circuit. However, the fixed value is not necessarily 0 (minimum signal value), and 0 to I
It is sufficient to know which value up to _max is fixed. However, since it is complicated to describe all cases, only the case where the minimum signal value is fixed will be described below.

Before describing the solution to the above-mentioned problem at the time of delay correction, in the trellis calculation circuit of FIG. 2, what kind of damage is caused to the output when the feedback signal 300 is to be input and 0 is stuck. Consider whether there is a possibility with reference to Table 6. Table 6 shows the range in which the amplitude control operation and the exchange operation need to be performed in accordance with the feedback signal fb among the outputs of the trellis calculation circuit having 0 stacks when the input bit width is 4 (m = 4).

[0063]

[Table 6]

Table 6 shows that in the first-stage arithmetic unit 27-2 shown in FIG. 2, outputs I0 (i, 1) and I1 (i, i, 1) of the arithmetic unit 27-2 corresponding to two inputs S _i1 and S _i2 .
1) in the case of m = 4, I0 (i, 1) / I1
This is illustrated in the form of (i, 1).

[0065]

[Outside 11]

According to the above description, in the delay correction type error correction circuit, the output of the arithmetic unit 27-2 is as shown in the second column of Table 6 in the state where S _i1 is 0 stacked. If the value of 300 (the feedback signal is fb in Table 6 and Table 7 described later) is known by some method, depending on the value, (a) for the area surrounded by the thick frame in Table 6, The maximum output value of the arithmetic unit

[0067]

## _EQU00003 ## I _max × | I _max −2 × fb | (1) It is necessary to limit to the following, and (b) when fb of the feedback signal is (I _max +1) / 2 or more. Is the two outputs of the trellis calculation circuit (I0 and I
It turns out that 1) must be replaced.

The amplitude limiting operation for executing the restriction of (a) and the exchange operation for executing the exchange of (b) are collectively referred to as a trellis variation adjustment (operation).

In Table 7 below, when a non-zero feedback signal fb is detected at time t, it is necessary to perform trellis variation adjustment on its output in order to correctly make feedback signal determination at times after time t + 1. The trellis calculation circuit with (273,
The case of 191) difference set cyclic code and (1057,813) difference set cyclic code is illustrated.

[0070]

[Table 7]

It should be noted here that the output of the trellis calculation circuit does not depend on the position of the signal input that stacks 0. This is clear from the fact that the trellis calculation circuit should basically function as an odd / even decision device among a large number of inputs, and the calculation result should not change depending on the physical position of the signal input. . Therefore,
The above description also holds true when the inputs of the arithmetic units other than the first stage of the trellis calculation circuit are zero-stacked.

When a plurality of inputs of the same trellis calculation circuit are 0-stacked ((β> 3, in Table 7 (105
78.13), etc. A ₃ symbols are examples. ) But
Due to the sequential decoding property of this circuit, no problem occurs in the calculation of the original value (the value of fb that is sequentially calculated) at the 0 stack position. However, the following additional procedure is required.

(C) Feedback signal f for 0 stack position
The value that minimizes the above equation (1) for each of b should be the maximum value of the output amplitude of the trellis calculation circuit.

(D) Only when the number of feedback signals fb exceeding the threshold value (I _max +1) / 2 in the exchange operation of the above (b) is an odd number, the exchange operation is performed.

The error determination unit 3 including the trellis variation adjustment unit 60 according to the present invention, which executes the above operations (a) to (d).
An example of the configuration of 0 is shown in FIG. 6, intermediate result input terminals 31-0 and 31-1 to which the output of the trellis calculation circuit 20 is input, summing circuits 32-1 and 32-2,

[0076]

[Outside 12]

It includes square circuits 34-1, 34-2, addition circuits 35-1, 35-2, a subtraction circuit 35-3, an error correction basic section 30 ', and a trellis variation compensation circuit 60'. . In this configuration, the portion excluding the error correction basic unit 30 'is called a trellis variation adjustment unit 60. In addition, I in the figure
0 '(j) and I1' (j) are

[0078]

[Outside 13]

It is

Here, the summing circuits 32-1 and 32-2 have basically the same function as the summing circuit of FIG. 3, but a trellis calculation circuit including a 0 stack.

[0081]

[Outside 14]

[0082]

[Equation 4]

Only the outputs I0 'and I1' of (3) are separately added after performing a trellis variation adjustment operation to obtain a correct value. The total delay of the trellis variation adjustment unit 60 and the error determination basic unit 30 'is m ₂ clocks. Further, the block 60A portion in FIG. 6 exemplifies a range to be considered so that the calculation result of each block included in the block 60A is output at an appropriate time with respect to each other in the sense that the error determination result is not inconvenienced. is doing.

FIG. 7 shows a configuration example of the trellis variation compensating circuit 60 'of the trellis variation adjusting unit 60 according to the present invention. As shown in FIG. 7, the trellis variation adjustment unit 60 according to the present invention.
The trellis variation compensation circuit 60 ′ includes a shift register circuit 61 and a trellis variation adjustment circuit 62.

The shift register circuit 61 is for holding the feedback signal fb input from the feedback signal input terminal 300 for a necessary period, and is composed of a data register 61-xy. Here, when the position counted from the input terminal 300 of the shift register circuit 61 is z, the data register 61-xy is

[0086]

X = int ((z−1) / m ₂ ) +1 y = z−m ₂ × (x−1) (note: int (R) is the maximum number less than or equal to the real number R) Represents an operation that finds an integer.)

The trellis variation adjustment circuit 62 is a trellis calculation circuit including a 0 stack.

[0088]

[Outside 15]

[0089]

[Equation 6]

An intermediate result input terminal 65-0 for inputting the output I0 'of

[0091]

[Equation 7]

The intermediate result input terminal 65-1 for inputting the output I1 'of, the adjusted output signal terminals 67-0 and 67-1 for outputting the trellis variation-adjusted outputs I0 and I1, and the amplitude limiter 63. and it consists exchange unit 64. in response to the output fb of the shift register circuit 61 as counted from the input side of one to an integer multiple of the position of the m ₂ register _{61-x-m 2 (t} -x), the trellis strange The minute adjustment operation is executed.
here,

[0093]

[Equation 8]

The output of is adjusted with reference to fb (tk).

Amplitude limiting section 6 of trellis variation adjusting circuit 62
3 and the function of the exchanging unit 64 are the same as the amplitude limiting operation (a) and the exchanging operation (b) of the trellis variation adjusting operation described above, but more specifically, they are as shown in FIG.

The threshold control circuit 40 shown in FIG. 4 is a circuit for generating the threshold TH used in the error determining section 30 in accordance with a sequence determined with reference to the number of elapsed clocks since the start of decoding. The output processing unit 50 is a circuit that performs appropriate threshold value processing on the output of the error determination unit 30 and outputs a binary signal output to the decoding output terminal 200.

In the above-described embodiment of the present invention, the case where the β−1 registers are reset to 0 from the received word input terminal of the shift register circuit has been described. However, the shift register outputs the minimum signal of the m-bit signal. Not the value, but I _max
Compensation operation when fixed to any of the following values,
It is easy to infer from the detailed description of the compensation operation.

[0098]

As described above, according to the present invention,
Trellis soft-decision Trellis soft-decision has been realized because an effective compensating means has been realized in order to avoid a time lag between timings of data groups to be used for signal processing when the feedback path in the error correction circuit is pipelined. Type error correction circuit can be pipelined in any number of stages, and the maximum (α + 1) × m ₂ (= m ₁
There is an effect that a trellis soft-decision error correction circuit as fast as + m ₂ ) can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a conventional trellis soft decision error correction circuit.

FIG. 2 is a block diagram showing a configuration example of a trellis calculation circuit in a conventional trellis soft decision error correction circuit.

FIG. 3 is a block diagram showing a configuration example of an error decision unit in a conventional trellis soft decision error correction circuit.

FIG. 4 is a block diagram showing a basic configuration of a delay correction type trellis soft decision error correction circuit according to the present invention.

FIG. 5 is a connection diagram showing a configuration example of a shift register circuit in a delay correction type trellis soft decision error correction circuit according to the present invention.

FIG. 6 is a block diagram showing a configuration example of an error determination unit including a trellis variation adjustment unit according to the present invention.

FIG. 7 is a block diagram showing a configuration example of a trellis variation compensating circuit in a trellis variation adjusting unit according to the present invention.

FIG. 8 is a functional block diagram showing a configuration example of (a) amplitude control section and (b) exchange section of the trellis variation compensation circuit according to the present invention.

[Explanation of symbols]

10 Shift register circuit 20 Trellis calculation circuit 21 Signal input terminal 22 Square circuit 23 Difference Square Circuit 24 adder circuit 25 Minimum value circuit 26 Output decision circuit 27 arithmetic unit 30 Error determination section 30 'Error judgment basic part 31 Intermediate result input terminal 32 summing circuit 33 Last bit input terminal 34 Square circuit 35-1, 35-2 adder circuit 35-3 Subtraction circuit 36 D value calculation circuit 37 Comparison circuit 38 Judgment circuit 39 Threshold input terminal 40 threshold control circuit 50 Output processing unit 60 Trellis variation adjustment unit 60 'trellis variation compensation circuit 61 Shift register circuit 62 Trellis variation adjustment circuit 63 Amplitude limiter 64 Exchange Department 65 Intermediate result input terminal 66 Delayed feedback signal input terminal 67 Intermediate result output terminal (after adjustment) 100 Received word input terminal (m bit width) 200 Decoding output terminal 300 feedback signal (input terminal / output terminal)

Continuation of front page (72) Inventor Masayuki Takada 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Broadcasting Research Laboratories, Japan Broadcasting Corporation (56) Reference JP-A-7-162319 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H03M 13/43 H04L 1/00 G06F 11/00

Claims (6)

(57) [Claims] 1. A trellis soft-decision error correction circuit which receives a binary signal having an m (m> 1) bit width as an input and decodes a code capable of majority logic decoding having a code length n, is β-th (β A shift register having an input terminal for the judgment result fed back to the register of> 1), and a trellis calculation unit for delaying the data transfer clock from the shift register to the trellis calculation circuit by m ₁ clocks and outputting the calculation result. A trellis soft-decision error correction circuit, comprising: an error decision unit that delays m ₂ clocks in units of a data transfer clock from the shift register to the trellis calculation circuit and outputs an operation result. 2. The trellis soft-decision error correction circuit according to claim 1, wherein m ₁ , m ₂ , and β are constants, m ₂ is a positive integer, and m ₁ is a positive integer.
= Α × m ₂ , α = 0 or a positive integer, β = α + 2 or β = (α + 1) × m ₂ +1. Trellis soft decision error correction circuit. 3. The trellis soft-decision error correction circuit according to claim 1 or 2, wherein the error decision unit monitors the feedback signal to the shift register and determines the trellis soft-decision error decision in the case of β = 1. A trellis soft-decision error correction circuit having a trellis variation adjustment unit for compensating an error with the circuit. 4. The trellis soft-decision error correction circuit according to claim 3, wherein the trellis variation adjustment unit sets the i-th register output counted from the received word input terminal of the shift register to S _i , [Outer 1] Is 0 during error correction operation (minimum signal value of m-bit signal)
Set to, and monitor the feedback signal of each clock as necessary [External 2] A trellis soft-decision error correction circuit characterized by performing an amplitude limiting operation and an exchange operation. 5. The trellis soft-decision error correction circuit according to claim 4, wherein the amplitude limiting operation of the trellis variation adjustment unit is a maximum signal value I _max (2 ^m −1) of an m-bit signal, a feedback signal. When I _fb and the absolute value operation are represented by | · |, the trellis calculation circuit is characterized in that the output signal value of the trellis calculation circuit is limited to I _max × | I _max −2 × I _fb | The exchange operation of I _th = (I
A trellis soft-decision error correction circuit, characterized in that it is an operation of exchanging two outputs of the trellis calculation circuit when I _fb ≧ I _th when _max +1) / 2. 6. The trellis variation adjustment method in the trellis variation adjustment unit according to claim 3, wherein when the i-th register output counted from the received word input terminal of the shift register is S _i , Outside 3] Is 0 during error correction operation (minimum signal value of m-bit signal)
And the step of setting to, and monitoring the feedback signal of every clock, if necessary [External 4] There is a step of performing an amplitude limiting operation and an exchange operation, and in the step of performing the amplitude limiting operation, the maximum signal value I _max (2 ^m −1) of the m-bit signal, the feedback signal I _fb , and the absolute value operation are When represented by |, the output signal value of the trellis calculation circuit is limited to I _max × | I _max −2 × I _fb | or less, and in the step of performing the exchange operation, I _th = (I _max +1) /
When it is set to 2, an operation of exchanging two outputs of the trellis calculation circuit is executed when I _fb ≧ I _th .