CN117081611B - Decoding method and device based on parallel processing - Google Patents
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/091—Parallel or block-wise CRC computation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1134—Full parallel processing, i.e. all bit nodes or check nodes are processed in parallel
Abstract
The invention discloses a decoding method and device based on parallel processing, wherein the method comprises the following steps: when the decoder receives the coded data, the coded data is cached and used as initial coded data; dividing the coded data according to a preset data length based on the type of the coded data to obtain a plurality of sub-coded data; performing parallel decoding processing on the sub-coded data to obtain error positions of the sub-coded data; the initial coded data is decoded and corrected according to the error position to obtain decoded data of the coded data, and the decoded data is decoded in a parallel processing mode, so that the decoding efficiency is improved, meanwhile, the type of the coded data can be automatically identified, the full automatic decoding is realized, and the labor cost is reduced; and giving consideration to the DVB-S2 standard BCH code and the DVB-S2X standard BCH code.
Description
Technical Field
The present disclosure relates to the field of coding and decoding technologies, and in particular, to a parallel processing-based decoding method and apparatus.
Background
BCH codes are a type of linear block codes that correct multiple errors, often used as an error platform for concatenating outer codes with LDPC codes and Turbo codes to eliminate inner codes. Such concatenated coding can provide excellent error correction performance, and thus is widely used in various wireless communication standards. Such as the digital television terrestrial transmission standard of china and DVB-S2, DVB-S2X, DVB-T2 of europe, etc.
However, in the prior art, the decoding process of the BCH code has many defects, one is that the BCH has more standards, so that when decoding different BCH codes, the current BCH code type needs to be manually input, and decoding of different BCH codes cannot be achieved, and the other is that the decoding process in the prior art generally adopts a linear processing mode, so that the decoding efficiency is too low.
Therefore, how to provide a decoding method and device based on parallel processing, which gives consideration to both DVB-S2 standard BCH codes and DVB-S2X standard BCH codes, and adopts a parallel processing mode to decode at the same time, so that the decoding efficiency is improved, and the technical problem to be solved at present.
Disclosure of Invention
The invention provides a decoding method and equipment based on parallel processing, which are used for solving the technical problem that the decoding process in the prior art cannot consider different BCH code types, and meanwhile, the linear decoding mode leads to low decoding efficiency, and are applied to a decoding system comprising a plurality of decoders, wherein the method comprises the following steps:
when the decoder receives the coded data, the coded data is cached and used as initial coded data;
dividing the coded data according to a preset data length based on the type of the coded data to obtain a plurality of sub-coded data;
performing parallel decoding processing on the sub-coded data to obtain error positions of the sub-coded data;
and decoding and correcting the initial coded data according to the error position to obtain decoded data of the coded data.
In some embodiments, when the decoder receives the encoded data, the encoded data is buffered and used as initial encoded data, the method further comprises:
receiving a plurality of coded data streams input in parallel;
acquiring the data volume of coded data to be decoded;
and distributing the coded data stream to each decoder according to a preset decoding parallel width so as to enable each decoder to decode the coded data in parallel.
In some embodiments, the coding data is divided according to a preset data length based on the type of the coding data to obtain a plurality of sub-coding data, which specifically includes:
determining the data type of the coded data received by the decoder, wherein the data type comprises a DVB-S2 standard BCH code and a DVB-S2X standard BCH code;
determining a data length of the encoded data based on the data type;
dividing the coded data according to a preset data length to obtain a plurality of sub-coded data, wherein the preset data length is 18 bits.
In some embodiments, the sub-encoded data is subjected to parallel decoding processing to obtain initial encoded data, which specifically includes:
carrying out syndrome calculation on the sub-coded data to obtain a syndrome of the sub-coded data;
determining an error location polynomial for the sub-encoded data based on the syndrome;
and acquiring the error position of the sub-coded data based on the error position polynomial.
In some embodiments, decoding and correcting the initial encoded data according to the error position to obtain decoded data of the encoded data, specifically:
obtaining error positions of each piece of sub-coded data, and determining positions to be corrected corresponding to each error position in the initial coded data;
correcting the code element of each position to be corrected;
and outputting the initial coded data after error correction to obtain decoded data of the coded data.
Correspondingly, the invention also provides decoding equipment based on parallel processing, which is applied to a decoding system comprising a plurality of decoders, and comprises:
the buffer module is used for buffering the coded data when the decoder receives the coded data and taking the coded data as initial coded data;
the segmentation module is used for segmenting the coded data according to the preset data length based on the type of the coded data to obtain a plurality of sub-coded data;
the acquisition module is used for carrying out parallel decoding processing on the sub-coded data to obtain error positions of the sub-coded data;
and the error correction module is used for carrying out decoding error correction on the initial encoded data according to the error position to obtain decoded data of the encoded data.
In some specific embodiments thereof, the apparatus further comprises a parallel receiving module for:
receiving a plurality of coded data streams input in parallel;
acquiring the data volume of coded data to be decoded;
and distributing the coded data stream to each decoder according to a preset decoding parallel width so as to enable each decoder to decode the coded data in parallel.
In some embodiments, the segmentation module is specifically configured to:
determining the data type of the coded data received by the decoder, wherein the data type comprises a DVB-S2 standard BCH code and a DVB-S2X standard BCH code;
determining a data length of the encoded data based on the data type;
dividing the coded data according to a preset data length to obtain a plurality of sub-coded data, wherein the preset data length is 18 bits.
In some embodiments, the acquiring module is specifically configured to:
carrying out syndrome calculation on the sub-coded data to obtain a syndrome of the sub-coded data;
determining an error location polynomial for the sub-encoded data based on the syndrome;
and acquiring the error position of the sub-coded data based on the error position polynomial.
In some embodiments, the error correction module is specifically configured to:
obtaining error positions of each piece of sub-coded data, and determining positions to be corrected corresponding to each error position in the initial coded data;
correcting the code element of each position to be corrected;
and outputting the initial coded data after error correction to obtain decoded data of the coded data.
By applying the technical scheme, when the decoder receives the coded data, the coded data is cached and used as initial coded data; dividing the coded data according to a preset data length based on the type of the coded data to obtain a plurality of sub-coded data; performing parallel decoding processing on the sub-coded data to obtain error positions of the sub-coded data; the initial coded data is decoded and corrected according to the error position to obtain decoded data of the coded data, and the decoded data is decoded in a parallel processing mode, so that the decoding efficiency is improved, meanwhile, the type of the coded data can be automatically identified, the full automatic decoding is realized, and the labor cost is reduced; and giving consideration to the DVB-S2 standard BCH code and the DVB-S2X standard BCH code.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a flow diagram of a decoding method based on parallel processing according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a decoding method based on parallel processing implemented by an FPGA according to an embodiment of the present invention;
fig. 3 shows a schematic structural diagram of a decoding device based on parallel processing according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
As shown in fig. 1, the present application proposes a decoding method based on parallel processing, which is applied to a decoding system including a plurality of decoders, and the method includes the following steps:
step S101, when the decoder receives the encoded data, the encoded data is buffered and used as initial encoded data.
In this embodiment, when the decoder receives the encoded data, in addition to decoding the encoded data to obtain corresponding decoded data, the buffer location may be a memory, a storage unit or other separately set storage space, etc., and in order to ensure the efficiency of the decoding process, as shown in fig. 2, the buffer process and the decoding process in this scheme are processed simultaneously in parallel, that is, the encoded data received by the same decoder need to be buffered simultaneously, and besides the process, since the subsequent decoding process needs to participate in the buffered encoded data, the speed of the buffer process should be higher than or equal to the speed of the decoding process, that is, the time required for completing the buffer should not be higher than the time required for completing the decoding process, so as to ensure the processing efficiency of the decoding process.
In order to improve decoding efficiency, in some embodiments of the present application, when the decoder receives encoded data, the encoded data is buffered and used as initial encoded data, the method further includes:
receiving a plurality of coded data streams input in parallel;
acquiring the data volume of coded data to be decoded;
and distributing the coded data stream to each decoder according to a preset decoding parallel width so as to enable each decoder to decode the coded data in parallel.
In this embodiment, a plurality of decoders are provided, and decoding processes are processed in parallel between the decoders, so that the decoders do not interfere with each other.
Step S102, dividing the coded data according to a preset data length based on the type of the coded data to obtain a plurality of sub-coded data.
In this embodiment, in the same decoder, in order to further improve decoding efficiency, the encoded data is divided according to a preset data length, and is divided into a plurality of sub-encoded data, and the plurality of sub-encoded data are processed in parallel at the same time, so as to realize high-speed decoding.
In order to achieve accurate segmentation of encoded data, in a specific implementation of the present application, the encoded data is segmented according to a preset data length based on a type of the encoded data, so as to obtain a plurality of sub-encoded data, which is specifically:
determining the data type of the coded data received by the decoder, wherein the data type comprises a DVB-S2 standard BCH code and a DVB-S2X standard BCH code;
determining a data length of the encoded data based on the data type;
dividing the coded data according to a preset data length to obtain a plurality of sub-coded data, wherein the preset data length is 18 bits.
In this embodiment, the data types of the encoded data include a DVB-S2 standard BCH code and a DVB-S2X standard BCH code, and in order to compromise decoding of the encoded data of both the DVB-S2 standard BCH code and the DVB-S2X standard BCH code, the data length is determined according to the data type of the input encoded data, and the encoded data is divided into a plurality of sub-encoded data according to each 18 bits.
Step S103, carrying out parallel decoding processing on the sub-coded data to obtain error positions of the sub-coded data.
In this embodiment, the decoding process is performed in parallel, and the error position in each sub-encoded data in the decoding process is determined.
In order to obtain the error position in each piece of sub-encoded data, in some embodiments of the present application, the sub-encoded data is subjected to parallel decoding processing to obtain initial encoded data, which specifically includes:
carrying out syndrome calculation on the sub-coded data to obtain a syndrome of the sub-coded data;
determining an error location polynomial for the sub-encoded data based on the syndrome;
and acquiring the error position of the sub-coded data based on the error position polynomial.
In this embodiment, as shown in fig. 2, the determining process of the error position mainly includes calculating polynomials of each sub-encoded data, determining the error position polynomials of the sub-encoded data according to the syndromes, and finally obtaining the error position of the sub-encoded data.
In this scheme, the step principle of step S103 is specifically described in the manner of FPGA.
The main implementation steps of the parallel decoding FPGA implementation are as follows:
1. the basic multiplier is realized by a circuit.
(1) Fixed factor multiplier: realizing the function of multiplying a variable by a constant. Used in calculating syndromes and money search error locations.
(2) General multiplier: realizing the function of multiplying two variables. Used in solving the error location polynomial.
According to finite field theory, it is known that forThe addition and multiplication of the two elements adopt the addition and multiplication of a common polynomial, and the coefficient adopts the modulo two operation. For m-dimensional binary vector representation +.>The addition of the elements in (a) is the exclusive or operation of the corresponding bits of the two addends, and the multiplication of the two bits is the AND operation.
To design a decoder according to a decoding algorithm, first, a unit circuit conforming to a basic operation therein is designed. Finite field addition is an exclusive-or operation of two addend corresponding bits, so the finite field adder can be implemented by m exclusive-or gates. The design complexity and delay of finite field multipliers increases as m increases. In order to simplify the operation, two kinds of multipliers are used as basic multiplication circuits of the present design, namely a general multiplier and a fixed factor multiplier.
Based on the multiplier, a syndrome calculation circuit is provided for calculating a syndrome S from the received codeword R (x). And judges whether the reception codeword R (x) is erroneous or not (s=0, no error is generated) according to the syndrome S.
Error location polynomial computation circuitry for solving for error location polynomial σ (x) using an inverse-free based BM iterative algorithm.
And the money searching circuit is used for searching money for the error position polynomial sigma (x) to obtain an error position.
And step S104, decoding and correcting the initial encoded data according to the error position to obtain decoded data of the encoded data.
In order to implement decoding and error correction on the initial encoded data, in some embodiments of the present application, decoding and error correction are performed on the initial encoded data according to the error position, so as to obtain decoded data of the encoded data, which specifically includes:
obtaining error positions of each piece of sub-coded data, and determining positions to be corrected corresponding to each error position in the initial coded data;
correcting the code element of each position to be corrected;
and outputting the initial coded data after error correction to obtain decoded data of the coded data.
In the scheme, the corresponding position in the initial coded data is determined according to the error position of each sub-coded data, and the code element of the corresponding position is corrected, and for the binary BCH code, the code element only has two values of 0 'and 1', so that the error correction of the BCH code can be completed only by reversing the code element at the error position, and the initial coded data after the error correction is output, so that the decoded data of the coded data are obtained.
By applying the technical scheme, when the decoder receives the coded data, the coded data is cached and used as initial coded data; dividing the coded data according to a preset data length based on the type of the coded data to obtain a plurality of sub-coded data; performing parallel decoding processing on the sub-coded data to obtain error positions of the sub-coded data; the initial coded data is decoded and corrected according to the error position to obtain decoded data of the coded data, and the decoded data is decoded in a parallel processing mode, so that the decoding efficiency is improved, meanwhile, the type of the coded data can be automatically identified, the full automatic decoding is realized, and the labor cost is reduced; and giving consideration to the DVB-S2 standard BCH code and the DVB-S2X standard BCH code.
The embodiment of the application also provides a decoding device based on parallel processing, as shown in fig. 3, applied to a decoding system including a plurality of decoders, the device includes:
the buffer module 10 is configured to buffer the encoded data when the decoder receives the encoded data, and serve as initial encoded data;
the dividing module 20 is configured to divide the encoded data according to a preset data length based on the type of the encoded data, so as to obtain a plurality of sub-encoded data;
the obtaining module 30 is configured to perform parallel decoding processing on the sub-encoded data, so as to obtain an error position of each sub-encoded data;
and the error correction module 40 is configured to perform decoding error correction on the initial encoded data according to the error position, so as to obtain decoded data of the encoded data.
In a specific application scenario of the present application, the apparatus further includes a parallel receiving module, where the parallel receiving module is configured to:
receiving a plurality of coded data streams input in parallel;
acquiring the data volume of coded data to be decoded;
and distributing the coded data stream to each decoder according to a preset decoding parallel width so as to enable each decoder to decode the coded data in parallel.
In a specific application scenario of the present application, the segmentation module is specifically configured to:
determining the data type of the coded data received by the decoder, wherein the data type comprises a DVB-S2 standard BCH code and a DVB-S2X standard BCH code;
determining a data length of the encoded data based on the data type;
dividing the coded data according to a preset data length to obtain a plurality of sub-coded data, wherein the preset data length is 18 bits.
In a specific application scenario of the present application, the obtaining module is specifically configured to:
carrying out syndrome calculation on the sub-coded data to obtain a syndrome of the sub-coded data;
determining an error location polynomial for the sub-encoded data based on the syndrome;
and acquiring the error position of the sub-coded data based on the error position polynomial.
In a specific application scenario of the present application, the error correction module is specifically configured to:
obtaining error positions of each piece of sub-coded data, and determining positions to be corrected corresponding to each error position in the initial coded data;
correcting the code element of each position to be corrected;
and outputting the initial coded data after error correction to obtain decoded data of the coded data.
In summary, the scheme sets a plurality of decoders, receives a plurality of coded data streams in parallel, decodes the coded data streams in the same decoder in a parallel processing mode, realizes dual parallel processing, and simultaneously automatically divides the coded data according to the type of the coded data, thereby improving the efficiency of the coding process.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature, and in the description of the invention, "a plurality" means two or more, unless otherwise specifically and clearly defined.
In the present invention, unless explicitly specified and limited otherwise, the terms "access", "connected", and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives, and variations may be made in the above embodiments by those skilled in the art without departing from the spirit and principles of the invention.
Claims (6)
1. A decoding method based on parallel processing, characterized in that it is applied to a decoding system including a plurality of decoders, said method comprising:
when the decoder receives the coded data, the coded data is cached and used as initial coded data;
dividing the coded data according to a preset data length based on the type of the coded data to obtain a plurality of sub-coded data;
performing parallel decoding processing on the sub-coded data to obtain error positions of the sub-coded data;
decoding and correcting the initial coded data according to the error position to obtain decoded data of the coded data;
wherein when the decoder receives encoded data, the encoded data is buffered and used as initial encoded data, the method further comprising:
receiving a plurality of coded data streams input in parallel;
acquiring the data volume of coded data to be decoded;
distributing the coded data stream to each decoder according to a preset decoding parallel width so that each decoder decodes the coded data in parallel;
wherein the method further comprises:
the workload of each decoder is monitored in real time, and the coded data stream is dynamically allocated according to the data quantity waiting for decoding in each decoder;
the buffer storage process and the decoding process of the decoder are performed simultaneously, and the speed of the buffer storage process is higher than that of the decoding process;
dividing the coded data according to a preset data length based on the type of the coded data to obtain a plurality of sub-coded data, wherein the sub-coded data specifically comprises:
determining the data type of the coded data received by the decoder, wherein the data type comprises a DVB-S2 standard BCH code and a DVB-S2X standard BCH code;
determining a data length of the encoded data based on the data type;
dividing the coded data according to a preset data length to obtain a plurality of sub-coded data, wherein the preset data length is 18 bits.
2. The method according to claim 1, wherein the sub-encoded data is subjected to parallel decoding processing to obtain initial encoded data, specifically:
carrying out syndrome calculation on the sub-coded data to obtain a syndrome of the sub-coded data;
determining an error location polynomial for the sub-encoded data based on the syndrome;
and acquiring the error position of the sub-coded data based on the error position polynomial.
3. The method according to claim 2, wherein decoding and correcting the initial encoded data according to the error position results in decoded data of the encoded data, in particular:
obtaining error positions of each piece of sub-coded data, and determining positions to be corrected corresponding to each error position in the initial coded data;
correcting the code element of each position to be corrected;
and outputting the initial coded data after error correction to obtain decoded data of the coded data.
4. A decoding apparatus based on parallel processing, for use in a decoding system comprising a plurality of decoders, said apparatus comprising:
the buffer module is used for buffering the coded data when the decoder receives the coded data and taking the coded data as initial coded data;
the segmentation module is used for segmenting the coded data according to the preset data length based on the type of the coded data to obtain a plurality of sub-coded data;
the acquisition module is used for carrying out parallel decoding processing on the sub-coded data to obtain error positions of the sub-coded data;
the error correction module is used for carrying out decoding error correction on the initial coded data according to the error position to obtain decoded data of the coded data;
wherein the device further comprises a parallel receiving module for:
receiving a plurality of coded data streams input in parallel;
acquiring the data volume of coded data to be decoded;
distributing the coded data stream to each decoder according to a preset decoding parallel width so that each decoder decodes the coded data in parallel;
wherein the apparatus is further for:
the workload of each decoder is monitored in real time, and the coded data stream is dynamically allocated according to the data quantity waiting for decoding in each decoder;
the buffer storage process and the decoding process of the decoder are performed simultaneously, and the speed of the buffer storage process is higher than that of the decoding process;
the segmentation module is specifically configured to:
determining the data type of the coded data received by the decoder, wherein the data type comprises a DVB-S2 standard BCH code and a DVB-S2X standard BCH code;
determining a data length of the encoded data based on the data type;
dividing the coded data according to a preset data length to obtain a plurality of sub-coded data, wherein the preset data length is 18 bits.
5. The apparatus of claim 4, wherein the acquisition module is specifically configured to:
carrying out syndrome calculation on the sub-coded data to obtain a syndrome of the sub-coded data;
determining an error location polynomial for the sub-encoded data based on the syndrome;
and acquiring the error position of the sub-coded data based on the error position polynomial.
6. The apparatus of claim 5, wherein the error correction module is specifically configured to:
obtaining error positions of each piece of sub-coded data, and determining positions to be corrected corresponding to each error position in the initial coded data;
correcting the code element of each position to be corrected;
and outputting the initial coded data after error correction to obtain decoded data of the coded data.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004165866A (en) * | 2002-11-12 | 2004-06-10 | Sony Corp | Data processing apparatus and method, recording medium, and program |
| CN101800560A (en) * | 2010-03-17 | 2010-08-11 | 苏州国芯科技有限公司 | Method for expanding error correcting capability of BCH (Broadcast Channel) encoding and decoding in Flash controller |
| CN106549677A (en) * | 2016-08-28 | 2017-03-29 | 航天恒星科技有限公司 | High-speed parallel BCH code interpretation method and device |
| CN108462561A (en) * | 2018-03-27 | 2018-08-28 | 东南大学 | The channel decoding method and device gone here and there and combined in ultrahigh speed communication system |
| CN112099986A (en) * | 2020-08-11 | 2020-12-18 | 西安电子科技大学 | ECC decoding system and method of branch pipeline structure |
| CN112332865A (en) * | 2020-10-29 | 2021-02-05 | 深圳电器公司 | Error correction circuit and method based on BCH parallel algorithm and LDPC algorithm |
-
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004165866A (en) * | 2002-11-12 | 2004-06-10 | Sony Corp | Data processing apparatus and method, recording medium, and program |
| CN101800560A (en) * | 2010-03-17 | 2010-08-11 | 苏州国芯科技有限公司 | Method for expanding error correcting capability of BCH (Broadcast Channel) encoding and decoding in Flash controller |
| CN106549677A (en) * | 2016-08-28 | 2017-03-29 | 航天恒星科技有限公司 | High-speed parallel BCH code interpretation method and device |
| CN108462561A (en) * | 2018-03-27 | 2018-08-28 | 东南大学 | The channel decoding method and device gone here and there and combined in ultrahigh speed communication system |
| CN112099986A (en) * | 2020-08-11 | 2020-12-18 | 西安电子科技大学 | ECC decoding system and method of branch pipeline structure |
| CN112332865A (en) * | 2020-10-29 | 2021-02-05 | 深圳电器公司 | Error correction circuit and method based on BCH parallel algorithm and LDPC algorithm |
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