KR101829461B1 - Stereoscopic image display device and method for driving thereof - Google Patents

Abstract

The present invention relates to a stereoscopic image display device including a liquid crystal display panel and a driving method thereof. A stereoscopic image display apparatus of the present invention includes: a display panel for displaying a monocular image during an odd frame period and displaying a black image during an excellent frame period; A backlight unit including light sources for emitting light to the display panel; And outputs a first gate shift clock and a first gate output enable signal having a constant period during the odd frame period and outputs a second gate shift clock and a second gate output enable signal having a variable period during the odd frame period Timing controller; And sequentially outputs gate pulses generated in accordance with the first gate shift clock and the first gate output enable signal to the gate lines of the display panel during the odd frame period and outputs the second gate shift clock And a gate driver sequentially outputting gate pulses generated according to a second gate output enable signal to the gate lines sequentially; And a data driver for supplying a data voltage synchronized with the gate pulse under the control of the timing controller.

Description

TECHNICAL FIELD [0001] The present invention relates to a stereoscopic image display device,

The present invention relates to a stereoscopic image display device including a liquid crystal display panel and a driving method thereof.

The stereoscopic display device displays a stereoscopic image using a stereoscopic technique or an autostereoscopic technique. The binocular parallax method uses parallax images of right and left eyes with large stereoscopic effect, and can be divided into a spectacular method and a non-spectacular method. In the spectacle method, there is a pattern retarder method in which a polarizing direction of a left-right parallax image is displayed on a direct-view type display device or a projector, and a stereoscopic image is implemented using polarizing glasses. In the eyeglass system, there is a shutter glass system in which right and left parallax images are displayed in a time-division manner on a direct view type display device or a projector, and a stereoscopic image is implemented using liquid crystal shutter glasses. The eyeglass system has an active retarder system in which right and left parallax images are time-divisionally displayed on a direct-view type display device or a projector while changing polarizing directions and realizing a stereoscopic image using polarizing glasses. In the non-eyeglass system, an optical plate such as a parallax barrier or a lenticular lens is generally used to separate the optical axes of the left and right parallax images to realize a stereoscopic image.

FIG. 1 is a view showing response curves and backlight timing of a liquid crystal at the top, center, and bottom of a display panel in the prior art. 1, black data is inserted between a left eye image and a right eye image in order to reduce 3D crosstalk in which a left eye image and a right eye image are overlapped in a shutter eyeglass system or an active retarder system in which the left eye image and the right eye image are displayed in a time- BDI (Black Data Insertion) technology has been proposed. However, when the display panel is implemented as a liquid crystal display device, the display panel sequentially displays images from the top to the bottom, so that the difference in the response of the liquid crystal at the top (A), the center (B), and the bottom Lt; / RTI > In addition, the backlight that supplies light to the display panel may be designed to light for a predetermined period of time in an excellent frame period to reduce the 3D crosstalk. In this case, a difference occurs in the response curves of the liquid crystal at the top (A), the center (B), and the bottom (C) of the display panel during a predetermined period during which the backlight is lit. That is, the liquid crystal is polled at the upper portion A of the display panel for a predetermined period during which the backlight is turned on, the liquid crystal at the center B is polled after the completion of the rising, and the liquid crystal at the lower portion C is brightened. Therefore, when the same data voltage different from the luminance of the display luminance of the upper (A) of the panel _(A L), the center (B) of the luminance (L _B), and lower _(C) (L C). Therefore, there is a problem that luminance unevenness occurs in the upper portion (A), the middle portion (B), and the lower portion (C) of the display panel.

The present invention relates to a stereoscopic image display device capable of improving luminance unevenness at the top, center, and bottom of a display panel in consideration of backlight lighting timing and a driving method thereof.

A stereoscopic image display apparatus of the present invention includes: a display panel for displaying a monocular image during an odd frame period and displaying a black image during an excellent frame period; A backlight unit including light sources for emitting light to the display panel; And outputs a first gate shift clock and a first gate output enable signal having a constant period during the odd frame period and outputs a second gate shift clock and a second gate output enable signal having a variable period during the odd frame period Timing controller; And sequentially outputs gate pulses generated in accordance with the first gate shift clock and the first gate output enable signal to the gate lines of the display panel during the odd frame period and outputs the second gate shift clock And a gate driver sequentially outputting gate pulses generated according to a second gate output enable signal to the gate lines sequentially; And a data driver for supplying a data voltage synchronized with the gate pulse under the control of the timing controller.

A method of driving a stereoscopic image display apparatus includes a display panel displaying a monocular image during an odd frame period, displaying a black image during an excellent frame period, and a backlight unit including light sources for emitting light to the display panel A first gate shift clock and a first gate output enable signal having a constant period during the odd frame period and outputting a first gate shift clock and a first gate output enable signal, Outputting a gate output enable signal; And sequentially outputs gate pulses generated in accordance with the first gate shift clock and the first gate output enable signal to the gate lines of the display panel during the odd frame period and outputs the second gate shift clock Sequentially outputting gate pulses generated in accordance with a second gate output enable signal to the gate lines; And supplying a data voltage synchronized with the gate pulse.

According to the present invention, gate pulses are sequentially output based on a first gate shift clock and a first gate output enable signal whose cycle is constant during an odd frame period, a second gate shift clock whose cycle is variable during an even frame period, And sequentially outputs gate pulses based on the gate output enable signal. As a result, the present invention can improve the luminance unbalance due to the difference in the response curve of the liquid crystal.

FIG. 1 is a view showing response curves and backlight timing of a liquid crystal at the top, center, and bottom of a display panel in the prior art.
2 is a block diagram schematically showing a stereoscopic image display apparatus according to an embodiment of the present invention.
3 is a cross-sectional view illustrating an active retarder according to an embodiment of the present invention.
4 is a detailed block diagram of a timing controller according to an embodiment of the present invention.
5 is a detailed block diagram illustrating a gate driver according to an embodiment of the present invention.
FIG. 6 is a diagram showing response curves and backlight timing of the liquid crystal at the top, center, and bottom of the display panel in the 3D mode according to the first embodiment of the present invention.
7 is a waveform diagram showing an output of the timing controller and an output of the gate driver in the odd frame of the 2D mode and the 3D mode.
8 is a waveform diagram showing an output of the timing controller and an output of the gate driver in the 3D frame mode.
9 is a graph showing response curves and backlight timing of the liquid crystal at the top, center, and bottom of the display panel in the 3D mode according to the second embodiment of the present invention.
10 is a waveform diagram showing the output of the timing controller and the output of the gate driver in the 3D frame mode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The component name used in the following description may be selected in consideration of easiness of specification, and may be different from the actual product name.

2 is a block diagram schematically showing a stereoscopic image display apparatus according to an embodiment of the present invention. 3 is a cross-sectional view illustrating an active retarder according to an embodiment of the present invention.

The stereoscopic image display device of the present invention can be applied to a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting diode Diodes, and OLEDs). Although the present invention has been described with reference to liquid crystal display elements in the following embodiments, it should be noted that the present invention is not limited to liquid crystal display elements. In addition, the stereoscopic image display device of the present invention can be realized by a time division spectacle method such as a shutter glasses method and an active retarder method. It should be noted that although the present invention has been illustrated mainly in the active retarder mode in the following embodiments, it is not limited to the active retarder mode.

2 and 3, the stereoscopic image display apparatus of the present invention includes a display panel 10, polarizing glasses 20, an active retarder 30, a gate driver 110, a data driver 120, A driving unit 130, a timing controller 140, a host system 150, and the like.

In the display panel 10, a liquid crystal layer is formed between two substrates. The substrate of the display panel 10 may be implemented as a glass, a plastic, or a film. On the upper substrate 10a of the display panel 10, a color filter array including a black matrix, a color filter, a common electrode, and the like is formed. The data lines D and the gate lines G are formed on the lower substrate 10b of the display panel 10 such that the data lines D and the gate lines G intersect each other. A TFT array in which pixels are arranged in a matrix form is formed in the cell regions defined by the TFT array. Each of the pixels of the display panel 10 is connected to the thin film transistor and driven by an electric field between the pixel electrode and the common electrode. The common electrode is formed on the upper substrate 10a in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode is formed in the IPS (In Plane Switching) mode and the FFS And is formed on the lower substrate 10b together with the pixel electrode in the horizontal electric field driving system. The liquid crystal mode of the display panel 10 can be implemented in any liquid crystal mode as well as the TN mode, VA mode, IPS mode, and FFS mode described above.

The display panel 10 displays an image under the control of the timing controller 140. The display panel 10 displays a 2D image in the 2D mode and time-divisionally displays the left eye image and the right eye image in the 3D mode. The liquid crystal response curves of the top (A), the center (B), and the bottom (C) of the display panel 10 in the 3D mode according to the embodiment of the present invention will be described later with reference to FIGS. 5 and 8. FIG.

The display panel 10 is typically a transmissive liquid crystal display panel that modulates light from the backlight unit. The backlight unit includes a light source that is turned on in accordance with the driving current supplied from the backlight driver, a light guide plate (or diffusion plate), and a plurality of optical sheets. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit. The light sources of the backlight unit may include any one of a light source of HCFL (Cold Cathode Fluorescent Lamp), CCFL (Cold Cathode Fluorescent Lamp), EEFL (External Electrode Fluorescent Lamp), LED .

The backlight driver generates a driving current for turning on the light sources of the backlight unit. The backlight driving unit turns on / off the driving current supplied to the light sources under the control of the backlight control unit. The backlight control unit supplies backlight control data obtained by adjusting the backlight brightness and lighting timing in accordance with the global / local dimming signal (DIM) input from the host system 150 and the backlight control signal input from the timing controller 140 to the Serial Pharipheral Interface ) Data format to the backlight driver.

Referring to FIG. 3, an upper polarizer 11a is attached to the upper substrate 10a of the display panel 10, and a lower polarizer 11b is attached to the lower substrate 10b. The light transmission axis r1 of the upper polarizer plate 11a and the light transmission axis r2 of the lower polarizer plate 11b are orthogonal. An alignment film for setting a pre-tilt angle of the liquid crystal is formed on the upper substrate 10a and the lower substrate 10b. A spacer for maintaining a cell gap of the liquid crystal layer is formed between the upper substrate 10a and the lower substrate 10b of the display panel 10. [ An active retarder 30 is attached on the upper polarizing plate 11a.

The active retarder 30 may be implemented as a liquid crystal panel that includes a reference electrode and a plurality of scan electrodes facing each other with a liquid crystal layer interposed therebetween and does not include a polarizer, a color filter, and a black matrix. The active retarder 30 may be implemented in a TN (Twisted Nematic) mode. When the first driving voltage Vd1 is applied to the scan electrodes, the active retarder 30 passes the light without changing the polarization characteristic of the light incident from the display panel 10. The active retarder 30 delays the phase value of the light incident from the display panel 10 by? / 2 (? Is the wavelength of light) when the second driving voltage Vd2 is applied to the scan electrodes. Therefore, the active retarder 30 emits the first polarized light P1 when the first driving voltage Vd1 is applied to the scan electrodes, and the second driving voltage Vd2 is applied to the scan electrodes The light of the second polarized light P2 is emitted. The polarizing glasses 20 include a left eye filter F _{L for} allowing only light of the first polarized light P1 to pass and a right eye filter F _{R for} passing only the light of the second polarized light P2.

The light passing through the upper polarizer 11a of the display panel 10 has a polarization characteristic of the first polarized light P1. The active retarder 30 allows light of the first polarized light P1 incident from the display panel 10 to pass therethrough when the first driving voltage Vd1 is applied to the scan electrodes. When the second driving voltage Vd2 is applied to the scan electrodes, the active retarder 30 delays the light of the first polarized light P1 incident from the display panel 10 by? / 2, And converts it into a polarized light P2. Accordingly, the user sees only the image of the first polarized light P1 incident on the left eye filter of the polarizing glasses 20 as the left eye, and the image of the second polarized light P2 incident on the right eye of the polarized glasses 20 as the right eye . As a result, the user can feel a stereoscopic effect due to the binocular parallax.

The active retarder driver 130 supplies the reference voltage and the first or second driving voltage Vd1 / Vd2 to the active retarder 30 under the control of the timing controller 140. [ The active retreader driving unit 130 may determine whether the mode is a 2D mode or a 3D mode according to a mode signal MODE input from the timing controller 140. [ The active retarder driver 130 supplies the reference voltage to the reference electrode of the active retarder 30 in the 2D mode and supplies the first driving voltage Vd1 to the scan electrodes. The active retarder driver 130 supplies a reference voltage to the reference electrode of the active retarder 30 in the 3D mode. The active retarder driving unit 130 applies a first driving voltage Vd1 or a second driving voltage Vd1 to the scan electrodes of the active retarder 30 according to the active retarder control signal C _AR input from the timing controller 140 in the 3D mode. 2 driving voltage Vd2. In the 3D mode, the active retarder driver 130 applies a first driving voltage (e.g., a first driving voltage) to the scan electrodes of the active retarder 30 so that the rotation of the liquid crystal of the active retarder 30 occurs only during the period when the light sources of the backlight unit are turned off. (Vd1) or the second driving voltage (Vd2).

The gate driver 110 sequentially supplies gate pulses to the gate lines G of the display panel 10 under the control of the timing controller 140. The gate driver 110 includes a plurality of gate drive integrated circuits (hereinafter referred to as " TFTs ") including a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell, Quot; IC "). Alternatively, the gate driver 110 may be formed directly on the lower substrate 10b of the display panel 10 using a GIP (gate drive IC in panel) method. In the case of the GIP method, the level shifter is mounted on a PCB (Printed Circuit Board), and the shift register can be formed on the lower substrate 10b of the display panel 10. [

The data driver 120 includes a plurality of source drive ICs. The source drive ICs convert the image data (RGB) input from the timing controller 140 into a positive / negative gamma compensation voltage to generate positive / negative analog data voltages. The source driver ICs supply positive / negative polarity analog data voltages synchronized with the gate pulse to the data lines D of the display panel 10 under the control of the timing controller 140.

The timing controller 140 supplies a gate driver control signal to the gate driver 110 (110) based on the image data (RGB) and the timing signals Vsync, Hsync, DE, and CLK output from the host system 150 and the mode signal MODE. And outputs the data driver control signal to the data driver 120. [ In particular, the timing controller 140 multiplies the frame frequency by L (L is a natural number equal to or greater than 2) times, preferably four times or more, of the input frame frequency, and outputs the gate driver control signal, Signal, a backlight control signal, and an active retarder control signal C _AR . The input frame frequency is 50 Hz in the PAL (Phase Alternate Line) method and 60 Hz in the National Television Standards Committee (NTSC) method.

The gate driving unit control signal includes a gate start pulse GSP, a first gate shift clock GSC1, a second gate shift clock GSC2, a first gate output enable signal Gate Output Enable 1, GOE1, and a second gate output enable signal GOE2. The gate start pulse (GSP) controls the timing of the first gate pulse. The first and second gate shift clocks GSC1 and GSC2 are clock signals for shifting the gate start pulse GSP. The first and second gate output enable signals GOE1 and GOE2 control the output timing of the gate driver 110. [

The first gate shift clock GSC1 and the first gate output enable signal GOE1 are not periodically changed during one frame period. That is, the first gate shift clock GSC1 and the first gate output enable signal GOE1 are output at a constant period during one frame period. On the other hand, the second gate shift clock GSC2 and the second gate output enable signal GOE2 are periodically varied during one frame period. A detailed description of the gate start pulse GSP, the first and second gate shift clocks GSC1 and GSC2 and the first and second gate output enable signals GOE1 and GOE2 will be described with reference to FIGS. 7 and 8, do.

The data driver control signal includes a source start pulse (SSP), a source sampling clock (SSC), a source output enable (SOE) signal, a polarity control signal (POL) . The source start pulse SSP controls the data sampling start timing of the data driver 120. The source sampling clock is a clock signal that controls the sampling operation of the data driver 120 based on the rising or falling edge. The source start pulse SSP and the source sampling clock SSC may be omitted if the digital video data to be input to the data driver 120 is transmitted in accordance with the mini LVDS (Low Voltage Differential Signaling) interface standard. The polarity control signal POL inverts the polarity of the data voltage output from the data driver 120 to L (L is a natural number) horizontal period period. The source output enable signal SOE controls the output timing of the data driver 120.

The host system 150 supplies the image data RGB to the timing controller 140 through an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (TMDS) interface. The host system 150 also supplies timing signals (Vsync, Hsync, DE, CLK), a mode signal (MODE), and the like to the timing controller 140. It should be noted that the mode signal MODE may occur at the high logic level in the 2D mode and may occur at the low logic level in the 3D mode, but is not limited thereto.

4 is a detailed block diagram of a timing controller according to an embodiment of the present invention. 4, the timing controller 140 includes a first gate control signal output section 141, a second gate control signal output section 142, a frame counter 143, a first multiplexer 144, And a multiplexer 145. A memory 160 storing waveform information of signals outputted through the first and second gate control signal output units 141 and 142 is located outside the timing controller 140. [

The memory 160 includes a gate start pulse GSP, a first gate shift clock GSC1, a second gate shift clock GSC2, a first gate output enable signal GOE1, and a second gate output enable signal GOE2), that is, information such as rising timing, falling timing, and pulse width are stored. The memory 160 outputs the waveform information to the first and second gate control signal output units 141 and 142 through a serial communication scheme such as I ² C (Inter-Integrated Circuit, I Square C) And outputs them to the gate control signal output units 141 and 142. The memory 160 may be implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory).

The first gate control signal output section 141 receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE and the dot clock CLK. The vertical synchronization signal Vsync is a signal indicating one vertical period. One vertical period means an n-line scanning time at which data is written to the pixels of the line of the display panel 10 (n is the number of gate lines of the display panel 10). The horizontal synchronization signal Hsync is a signal indicating one horizontal period. One horizontal period means one line scanning time at which data is written to one line of pixels in the display panel 10. [ The dot clock (CLK) is a clock signal that is repeated in a short cycle. The data enable signal DE is a signal indicating the presence or absence of video data.

The first gate control signal output section 141 includes a counter for counting the dot clock DCLK and counts count information of the counter and the gate start pulse GSP input from the memory 160 and the first gate shift clock GSC1 The first gate shift clock GSC1 and the first gate output enable signal GOE1 according to the waveform information of the first gate output enable signal GOE1 and the first gate output enable signal GOE1 . On the other hand, the gate start pulse GSP, the first gate shift clock GSC1, and the first gate output enable signal GOE1 output from the first gate control signal output section 141 are input to the 2D gate control signal GSC _2D ). ≪ / RTI >

The second gate control signal output section 142 receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the dot clock DCLK. The second gate control signal output section 142 includes a counter for counting the dot clock DCLK and counts count information of the counter and the gate start pulse GSP input from the memory 160 and the second gate shift clock GSC2 The second gate shift clock GSC2 and the second gate output enable signal GOE2 according to the waveform information of the first gate output enable signal GOE2 and the second gate output enable signal GOE2 .

The frame counter 143 receives the vertical synchronization signal Vsync. The frame counter 143 counts the vertical synchronization signal Vsync and outputs to the first multiplexer 144 a frame division signal Fodd / even that can distinguish the odd (odd) frame from the even (odd) frame. For example, it should be noted that the frame discrimination signal Fodd / even may occur at a high logic level in the case of an odd frame and may occur at a low logic level in the case of an odd frame, but is not limited thereto.

The first multiplexer 144 receives the gate start pulse GSP, the first gate shift clock GSC1 and the first gate output enable signal GOE1 from the first gate control signal output section 141, The second gate shift clock GSC2, and the second gate output enable signal GOE2 from the two gate control signal output section 142. The gate control signal output section 142 receives the gate start pulse GSP, the second gate shift clock GSC2 and the second gate output enable signal GOE2. Also, the first multiplexer 144 receives the frame discrimination signal Fodd / even from the frame counter 144.

The first multiplexer 144 outputs the gate start pulse GSP and the first gate shift clock GOP inputted from the first gate control signal output section 141 when the frame discrimination signal Fodd / GSC1, and a first gate output enable signal GOE1. The first multiplexer 144 outputs the gate start pulse GSP and the second gate shift clock GSP inputted from the second gate control signal output section 142 when the frame discrimination signal Fodd / GSC2, and a second gate output enable signal GOE2. That is, the first multiplexer 144 outputs the gate start pulse GSP, the first gate shift clock GSC1, and the first gate output enable signal GOE1 in the odd frame, and outputs the gate start pulse GSP, a second gate shift clock GSC2, and a second gate output enable signal GOE2. On the other hand, the gate start pulse GSP, the first gate shift clock GSC1, and the first gate output enable signal GOE1 output from the first multiplexer 144 to the odd frame, The pulse GSP, the second gate shift clock GSC2, and the second gate output enable signal GOE2 may be defined as a 3D gate control signal GSC _3D .

The second multiplexer 145 receives the 2D gate control signal GSC _2D from the first gate control signal output unit 141 and receives the 3D gate control signal GSC _3D from the first multiplexer 144. Also, the second multiplexer 145 receives the mode signal MODE. The second multiplexer 145 outputs the 2D gate control signal GSC _2D when the mode signal MODE of the high logic level is inputted and outputs the 3D gate control signal GSC _{2D when} the mode signal MODE of the low logic level is inputted GSC _3D ). That is, the second multiplexer 145 outputs the gate start pulse GSP, the first gate shift clock GSC1, and the first gate output enable signal GOE1 as the 2D gate control signal GSC _2D in the 2D mode do. The second multiplexer 145 outputs the gate start pulse GSP, the first gate shift clock GSC1 and the first gate output enable signal GOE1 in the odd numbered frame as the 3D gate control signal GSC _3D in the 3D mode And outputs a gate start pulse GSP, a second gate shift clock GSC2, and a second gate output enable signal GOE2 to the odd-numbered frame. The output of the second multiplexer 145 is input to the gate driver 110.

5 is a detailed block diagram illustrating a gate driver according to an embodiment of the present invention. Referring to FIG. 5, the gate driver 110 includes a plurality of gate drive ICs. The gate drive IC includes a shift register 111, a level shifter 114, a plurality of AND gates 112 connected between a shift register 111 and a level shifter 114, And an inverter 113 for inverting the first or second gate output enable signal GOE1 / GOE2.

The shift register 111 shifts the gate start pulse GSP sequentially in accordance with the first or second gate shift clock GSC1 / GSC2 using a plurality of D flip-flops connected in a dependent manner. Each of the AND gates 112 generates an output by logically multiplying the output signal of the shift register 111 and the inverted signal of the first or second gate output enable signal GOE1 / GOE2. The inverter 113 inverts the first or second gate output enable signal GOE1 / GOE2 and supplies it to the AND gates 112. [ Thus, each of the gate drive ICs generates an output only when the enable signal GOE1 / GOE2, which is the first or second gate output, is at the low logic level.

The level shifter 114 shifts the output voltage swing width of the AND gate 112 to a swing width capable of operating the TFT formed in the TFT array of the display panel 10. [ The output signal of the level shifter 114 is sequentially supplied to the gate lines G. [

The shift register 111 may be formed directly on the lower glass substrate 10b of the display panel 10 together with the TFT array in the GIP (Gate In Panel) process. In this case, the level shifter 114 is formed on the control board or the source printed circuit board together with the timing controller 140 so as to adjust the swing width to the first or second And supplies the gate shift clock GSC1 / GSC2 to the shift register 111. [

FIG. 6 is a diagram showing response curves and backlight timing of the liquid crystal at the top, center, and bottom of the display panel in the 3D mode according to the first embodiment of the present invention. Referring to FIG. 6, the display panel 10 displays a monocular image during a radix frame period, and displays a black image during an excellent frame period. The display panel 10 alternately displays the left eye image and the right eye image during the odd frame period. That is, the display panel 10, the left-eye image data (RGB _L), the black data (Black), right eye image data (RGB _R), and the black data (Black) is addressed sequentially as shown in FIG. Since the response curves of the liquid crystal are different in the upper portion A, the middle portion B and the lower portion C of the display panel 10, the brightness L _A , the center B of the upper portion A, The luminance L _{B of the} lower portion C and the luminance L _C of the lower portion C are different. Therefore, in FIG. 6, the backlight (light source) is turned on for a predetermined period in the excellent frame period.

6, the timing controller 140 outputs black data (Black) at the center (B) and the lower portion (C) of the display panel 10 during the excellent frame period when the backlight is lit for a predetermined period in the excellent frame period. The addressing of the memory cell is controlled quickly. In this case, the response curve of the liquid crystal at the upper portion A of the display panel 10 is unchanged from that of the related art, but the response curve of the liquid crystal at the center B and the lower portion C is lower than that of the prior art ) Starts quickly. The luminance L _B of the center B of the display panel 10 and the luminance L _C of the lower portion C are lower than those of the conventional art and therefore the luminance of the upper portion A of the display panel 10 (L _a), luminance (L _C) of the luminance (L _B), and lower (C) of the central (B) becomes uniform over the prior art. That is, the present invention can quickly control the addressing of the black data (Black) at the center (B) and the bottom (C) of the display panel 10 during the excellent frame period when the backlight is lit for a predetermined period in the excellent frame period The luminance unevenness due to the difference in the response curve of the liquid crystal can be improved. Hereinafter, a method of quickly controlling the addressing of the black data (Black) at the center (B) and the bottom (C) of the display panel (10) in conjunction with FIG. 7 and FIG. 8 will be described in detail.

7 is a waveform diagram showing an output of the timing controller and an output of the gate driver in the odd frame of the 2D mode and the 3D mode. 7, the gate start pulse GSP, the first gate shift clock GSC1, and the first gate output enable signal GOE1, which are output from the timing controller 140 in the 2D and 3D mode odd frames, Respectively. Also, gate pulses GP1, GP2, GPn-1, and GPn output from the gate driver 110 in the odd frame of the 2D mode and the 3D mode are shown.

A gate start pulse (GSP) is generated to control the timing of the first gate pulse at the beginning of one frame. The period C1 of the first gate shift clock GSC1 and the period C11 of the first gate output enable signal GOE1 are constantly generated. The period C1 of the first gate shift clock GSC1 and the period C11 of the first gate output enable signal GOE1 in the odd frame of the 2D mode and the 3D mode do not change.

The first to n-th gate pulses GP1, GP2, GPn-1, and GPn output the first and second gate pulses GS1 and GS2, respectively, And the inverted signal of the gate output enable signal GOE1. Since the period C1 of the first gate shift clock GSC1 and the period C11 of the first gate output enable signal GOE1 are constant and unchanged in the odd frame of the 2D mode and the 3D mode, The pulses (GP1, GP2, GPn-1, GPn) are sequentially generated with the same pulse width. The first to n-th gate pulses GP1, GP2, GPn-1, and GPn may occur during approximately one horizontal period.

After all, first to n-th gate pulses (GP1, GP2, GPn-1, GPn) is so generated in sequence by the same pulse width, 3D mode, the left-eye image data (RGB _L) and right-eye images as shown in FIG. 7 from the odd number frame The data RGB _R are addressed at the same speed at the top A, center B and bottom C of the display panel 10.

8 is a waveform diagram showing an output of the timing controller and an output of the gate driver in the 3D frame mode. Referring to FIG. 8, a gate start pulse GSP, a second gate shift clock GSC2, and a second gate output enable signal GOE2 output from the timing controller 140 in the 3D frame mode are shown . In addition, there is shown the output from the gate driver 110 in the solid frame of the 3D mode, the gate pulses (GP1, GP2, GP _{2 / n,} GP _{(2 / n) +1,} 1-GPn, GPn).

A gate start pulse (GSP) is generated to control the timing of the first gate pulse at the beginning of the start of one frame. The periods C2, C3 and C4 of the second gate shift clock GSC2 and the periods C12, C13 and C14 of the second gate output enable signal GOE2 are variable. The periods C2, C3 and C4 of the second gate shift clock GSC2 and the periods C12, C13 and C14 of the second gate output enable signal GOE2 become shorter in the middle period than in the beginning of one frame period, And becomes smaller at the end of the one frame period than in the middle period. For example, at the end of one frame period, the period C4 of the second gate shift clock GSC2 is about two thirds lower than the period C2 of the second gate shift clock GSC2 at the beginning of one frame period Can be shortened. The period C14 of the second gate output enable signal GOE2 at the end of one frame period is about 2/3 of the period C12 of the second gate output enable signal GOE2 at the beginning of one frame period . ≪ / RTI >

The periods C 2, C 3 and C 4 of the second gate shift clock GSC 2 and the periods C 12, C 13 and C 14 of the second gate output enable signal GOE 2 are calculated in consideration of the data voltage charging time of the pixel , Which can be predetermined through a preliminary experiment. 8, the periods C2, C3, and C4 of the second gate shift clock GSC2 and the periods C12, C13, and C14 of the second gate output enable signal GOE2 are different from each other in the middle, But the present invention is not limited to this. The periods C 2, C 3 and C 4 of the second gate shift clock GSC 2 and the periods C 12, C 13 and C 14 of the second gate output enable signal GOE 2 may be varied P (P is a natural number) The P may be determined in advance through a preliminary experiment.

First to n-th in accordance with gate pulses _{(GP1, GP2, GP 2 /} n, GP (2 / n) +1, GPn-1, GPn) is a gate start pulse (GSP) a second gate shift clock (GSC2) And a result obtained by logically multiplying the output of the shift register 111 shifted sequentially and the inverted signal of the second gate output enable signal GOE2. Since the periods C12, C13 and C14 of the second gate shift clock GSC2 and the second gate output enable signal GOE2 of the 3D mode mode change in the cycles C2, C3 and C4, the n-th gate pulses _{(GP1, GP2, GP 2 /} n, GP (2 / n) +1, GPn-1, GPn) in the pulse width is changed. That is, the periods C2, C3, and C4 of the second gate shift clock GSC2 and the periods C12, C13, and C14 of the second gate output enable signal GOE2 are shorter in the middle period than the beginning of one frame period is therefore shorter than the middle in the end of one frame period, the first to n-th gate pulses (GP1, GP2, GP _{2 / n,} GP _{(2 / n) +1,} 1-GPn, GPn) is a pulse width of 1 Becomes smaller in the middle than the beginning of the frame period and becomes smaller in the end period than the middle period of one frame period. Since the period C2 of the second gate shift clock GSC2 and the period C12 of the second gate output enable signal GOE2 are the longest at the beginning of one frame period as shown in Fig. 8, The pulse widths W1 of the pulses GP1 and GP2 are the largest. Since the period C4 of the second gate shift clock GSC2 and the period C14 of the second gate output enable signal GOE2 are the shortest at the end of one frame period, GPn-1, GPn) is the smallest.

As a result, the gate driver 110 so that the pulse width is smaller than at the end of the beginning of one frame period, first to n-th gate pulses (GP1, GP2, GP _{2 / n,} GP _{(2 / n) +1,} GPn-1 , And GPn are sequentially generated. Therefore, in the 3D frame, the black data (Black) is addressed at a higher speed than the upper portion (A) of the display panel (10) as shown in FIG.

On the other hand, the source drive IC of the data driver 120 are the first to n-th gate pulses (GP1, GP2, GP _{2 / n,} GP _{(2 / n} that the pulse width is changed under the control of the timing controller _{140) +1} , GPn-1, and GPn) to the data lines (D) of the display panel (10). Source drive IC are the first to n-th gate pulses _{(GP1, GP2, GP 2 /} n, GP (2 / n) +1, GPn-1, GPn) , while varying the period of the data voltage according to the pulse width of the data voltage .

On the other hand, the active retarder 30 emits the light of the first polarized light P1 during the 4n-3 frame and the 4n-2 frame period, and the second polarized light P2 Is emitted to emit light. That is, the first driving voltage Vd1 is applied to the active retarder 30 during the 4n-3 frame and the 4n-2 frame period, and the second driving voltage Vd2 during the 4n-1 frame and the 4n- Is applied.

9 is a graph showing response curves and backlight timing of the liquid crystal at the top, center, and bottom of the display panel in the 3D mode according to the second embodiment of the present invention. Referring to FIG. 9, the display panel 10 displays a monocular image during a radix frame period, and displays a black image during an excellent frame period. The display panel 10 alternately displays the left eye image and the right eye image during the odd frame period. That is, the display panel 10, the left-eye image data (RGB _L), the black data (Black), right eye image data (RGB _R), and the black data (Black) is addressed sequentially as shown in FIG. Since the response curves of the liquid crystal are different in the upper portion A, the middle portion B and the lower portion C of the display panel 10, the brightness L _A , the center B of the upper portion A, The luminance L _{B of the} lower portion C and the luminance L _C of the lower portion C are different. Therefore, in FIG. 9, the backlight is mainly turned on for a predetermined period over the odd frame and the even frame period.

When the backlight is lit for a predetermined period of time in the odd frame and the even frame period as shown in Fig. 9, the timing controller 140 controls the top (A) of the display panel 10 and the black data (Black) addressing. In this case, although the response curve of the liquid crystal at the lower portion C of the display panel 10 is unchanged from that of the prior art, the response curve of the liquid crystal at the upper portion A and the center portion B is lower than that of the prior art ) Starts quickly. The luminance L _A of the upper portion A of the display panel 10, the luminance L _B of the center B and the luminance L _C of the lower portion C are more uniform than those of the conventional art. That is, in the present invention, when the backlight is lit for a predetermined period of time in the odd frame and the even frame period, the addressing of the black data (Black) at the top A of the display panel 10 and at the center B It is possible to improve the luminance unbalance due to the difference in the response curve of the liquid crystal.

Hereinafter, a method for quickly controlling the addressing of the black data (Black) at the top (A) and the center (B) of the display panel 10 in connection with FIG. 10 will be described in detail. In the second embodiment of the present invention, the output of the timing controller and the output of the gate driver in the 2D and 3D mode odd frames are as described in FIG.

10 is a waveform diagram showing the output of the timing controller and the output of the gate driver in the 3D frame mode. 10, the gate start pulse GSP, the second gate shift clock GSC2, and the second gate output enable signal GOE2 output from the timing controller 140 in the 3D frame mode are shown . In addition, there is shown the output from the gate driver 110 in the solid frame of the 3D mode, the gate pulses (GP1, GP2, GP _{2 / n,} GP _{(2 / n) +1,} 1-GPn, GPn).

A gate start pulse (GSP) is generated to control the timing of the first gate pulse at the beginning of the start of one frame. The periods C5, C6 and C7 of the second gate shift clock GSC2 and the periods C15, C16 and C17 of the second gate output enable signal GOE2 are variable. The periods C5, C6 and C7 of the second gate shift clock GSC2 and the periods C15, C16 and C17 of the second gate output enable signal GOE2 become longer in the middle period than in the beginning of one frame period, It becomes longer at the end than at the middle of one frame period. For example, at the beginning of one frame period, the period C5 of the second gate shift clock GSC2 is about two thirds lower than the period C7 of the second gate shift clock GSC2 at the end of one frame period Can be shortened. The period C15 of the second gate output enable signal GOE2 at the beginning of one frame period is about 2/3 of the period C17 of the second gate output enable signal GOE2 at the end of one frame period . ≪ / RTI >

The periods C5, C6 and C7 of the second gate shift clock GSC2 and the periods C15, C16 and C17 of the second gate output enable signal GOE2 take into account the data voltage charging time of the pixel , Which can be predetermined through a preliminary experiment. 10, the periods C5, C6 and C7 of the second gate shift clock GSC2 and the periods C15, C16 and C17 of the second gate output enable signal GOE2 correspond to the initial, But the present invention is not limited to this. The periods C5, C6 and C7 of the second gate shift clock GSC2 and the periods C15, C16 and C17 of the second gate output enable signal GOE2 may be varied P (P is a natural number) The P may be determined in advance through a preliminary experiment.

First to n-th in accordance with gate pulses _{(GP1, GP2, GP 2 /} n, GP (2 / n) +1, GPn-1, GPn) is a gate start pulse (GSP) a second gate shift clock (GSC2) And a result obtained by logically multiplying the output of the shift register 111 shifted sequentially and the inverted signal of the second gate output enable signal GOE2. Since the periods C15, C16 and C17 of the second gate shift clock signal GSC2 and the second gate output enable signal GOE2 of the 3D frame mode change in the odd frame of the 3D mode, the n-th gate pulses _{(GP1, GP2, GP 2 /} n, GP (2 / n) +1, GPn-1, GPn) in the pulse width is changed. That is, the periods C5, C6, and C7 of the second gate shift clock GSC2 and the periods C15, C16, and C17 of the second gate output enable signal GOE2 are longer in the middle than the beginning of one frame period It is therefore longer than in the end of the middle of the one frame period, first to n-th gate pulses (GP1, GP2, GP _{2 / n,} GP _{(2 / n) +1,} 1-GPn, GPn) is a pulse width of 1 Is larger in the middle than in the beginning of the frame period and becomes larger in the terminal period than in the middle period of the one frame period. Since the period C5 of the second gate shift clock GSC2 and the period C15 of the second gate output enable signal GOE2 are the shortest at the beginning of one frame period as shown in Fig. 8, The pulse widths W1 of the pulses GP1 and GP2 are the smallest. Since the period C7 of the second gate shift clock GSC2 and the period C17 of the second gate output enable signal GOE2 are the longest at the end of one frame period, GPn-1, GPn) is the largest.

As a result, the gate driver 110 includes first to n-th gate pulse to the end than in the beginning of one frame period larger the pulse width (GP1, GP2, GP _{2 / n,} GP _{(2 / n) +1,} GPn-1 And GPn are sequentially generated. Therefore, in the 3D mode, black data is addressed at a higher speed than the lower portion C of the display panel 10 at a high speed as shown in FIG.

On the other hand, the source drive IC of the data driver 120 are the first to n-th gate pulses (GP1, GP2, GP _{2 / n,} GP _{(2 / n} that the pulse width is changed under the control of the timing controller _{140) +1} , GPn-1, and GPn) to the data lines (D) of the display panel (10). The source drive ICs vary the period of the data voltage according to the pulse width of the first to n-th gate pulses GP1, GP2, GP2 _{/ n} , GP _{(2 / n) +1} , GPn- .

On the other hand, the active retarder 30 emits the light of the first polarized light P1 during the 4n-3 frame and the 4n-2 frame period, and the second polarized light P2 Is emitted to emit light. That is, the first driving voltage Vd1 is applied to the active retarder 30 during the 4n-3 frame and the 4n-2 frame period, and the second driving voltage Vd2 during the 4n-1 frame and the 4n- Is applied.

As described above, according to the present invention, gate pulses are sequentially output based on a first gate shift clock and a first gate output enable signal whose period is constant during an odd frame period, And sequentially outputs gate pulses based on the gate shift clock and the second gate output enable signal. As a result, the present invention can improve the luminance unbalance due to the difference in the response curve of the liquid crystal.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: display panel 10a: upper substrate
10b: lower substrate 11a: upper polarizer plate
11b: lower polarizer plate 20: polarizing glasses
30: active retarder 110: gate driver
111: shift register 112: AND gate
113: inverter 114: level shifter
120: Data driver 130: Active retarder driver
140: timing controller 141: first gate control signal output section
142: second gate control signal output section 143: frame counter
144: first multiplexer 145: second multiplexer
150: host system 160: memory

Claims (11)

A display panel for displaying the monocular image during the odd frame period and displaying the black image during the excellent frame period;
A backlight unit including light sources for emitting light to the display panel;
A first gate shift clock and a first gate output enable signal having a constant period are output during the odd frame period to keep the display period of the monocular image the same, and the period is gradually increased or decreased gradually A timing controller for outputting a second gate shift clock and a second gate output enable signal to vary the display period of the black image;
And sequentially outputs gate pulses generated in accordance with the first gate shift clock and the first gate output enable signal to the gate lines of the display panel during the odd frame period and outputs the second gate shift clock And a gate driver sequentially outputting gate pulses generated according to a second gate output enable signal to the gate lines sequentially; And
And a data driver for supplying a data voltage synchronized with the gate pulse under the control of the timing controller. The method according to claim 1,
The timing controller includes:
A first gate control signal output unit for outputting a gate start pulse, a first gate shift clock, and a first gate output enable signal in accordance with waveform information input from an external memory;
A second gate control signal output unit for outputting a gate start pulse, a second gate shift clock, and a second gate output enable signal in accordance with waveform information input from the external memory;
A frame counter for counting the vertical synchronizing signal and outputting a frame discrimination signal for distinguishing the odd frame from the odd frame;
And outputs the gate start pulse, the first gate shift clock, and the first gate output enable signal input from the first gate control signal output unit during the odd frame period according to the frame discrimination signal, A first multiplexer for outputting a gate start pulse, a second gate shift clock, and a second gate output enable signal input from the second gate control signal output section; And
A first multiplexer for receiving a mode signal for distinguishing between a 2D mode and a 3D mode and outputting a signal input from the first gate control signal output unit in the 2D mode according to the mode signal, And a second multiplexer for outputting a signal. The method according to claim 1,
The timing controller includes:
When the light sources of the backlight unit are turned on for a predetermined period of time in the even frame period, the period of the second gate shift clock and the period of the second gate output enable signal are controlled to be shorter than the beginning of the excellent frame period And the three-dimensional image display device. The method of claim 3,
The timing controller includes:
Wherein the period of the second gate shift clock and the period of the second gate output enable signal are varied by P (P is a natural number) times. The method of claim 3,
Wherein a pulse width of the gate pulse is smaller than an initial period of the excellent frame period. The method according to claim 1,
When the light sources of the backlight unit are lit for a predetermined period of time in the odd frame and the even frame period, the period of the second gate shift clock and the period of the second gate output enable signal are set earlier than the end of the one frame period Wherein the control unit controls the display unit to be shortened. The method according to claim 6,
The timing controller includes:
Wherein the period of the second gate shift clock and the period of the second gate output enable signal are varied by P (P is a natural number) times. The method according to claim 6,
Wherein the pulse width of the gate pulse is larger at the end than at the beginning of the excellent frame period. The method according to claim 1,
In the display panel,
And displays the left eye image and the right eye image alternately during the odd frame period. 10. The method of claim 9,
Wherein the display panel displays a left eye image on the display panel in the odd frame period and emits light of a first polarized light during a period for displaying black data on the display panel in the excellent frame period, An active retarder for displaying an image and emitting light of a second polarized light during a period of displaying black data on the display panel in the excellent frame period; And
A left eye filter for passing only light of the first polarized light and a right eye filter for passing only light of the second polarized light. A stereoscopic image display apparatus comprising: a display panel for displaying a monocular image during a radix frame period, displaying a black image during an excellent frame period, and a backlight unit including light sources for emitting light to the display panel,
A first gate shift clock and a first gate output enable signal having a constant period during the odd frame period and outputting a first gate shift clock and a first gate output enable signal and outputting a second gate shift clock and a second gate shift clock, Outputting an enable signal;
And sequentially outputs gate pulses generated in accordance with the first gate shift clock and the first gate output enable signal to the gate lines of the display panel during the odd frame period and outputs the second gate shift clock Sequentially outputting gate pulses generated in accordance with a second gate output enable signal to the gate lines; And
And displaying the black image at a variable period during the odd frame period by supplying a data voltage synchronized with the gate pulse so that the display panel displays the monocular image at a constant period during the odd frame period, A method of driving a device.

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