KR20110057535A - Stereoscopic image display and driving method thereof - Google Patents

Abstract

PURPOSE: A stereoscopic image display and a driving method thereof are provided to reduce power consumption in 3D mode by making the vertical polarity inversion period of image data longer than 2D mode. CONSTITUTION: In a stereoscopic image display and a driving method thereof, A 2D image is provided to a display panel(S1) The vertical polarity inversion period of the 2D image is controlled to a first period(S2) A 3D image is provided to a display panel(S3) The vertical polarity inversion period of the 3D image is controlled to a second period(S4) The second period is longer than the first period.

Description

Stereoscopic Display and Driving Method {STEREOSCOPIC IMAGE DISPLAY AND DRIVING METHOD THEREOF}

The present invention relates to a stereoscopic image display device and a driving method thereof.

The stereoscopic image display apparatus is divided into a binocular parallax technique and an autostereoscopic technique.

The binocular disparity method uses a parallax image of the left and right eyes with a large stereoscopic effect, and is divided into a glasses method and a glasses-free method. The spectacle method displays a polarization direction of the left and right parallax image on a direct-view display device or a projector by changing the polarization direction or time division method, and realizes a stereoscopic image using polarized glasses or shutter glasses. In the autostereoscopic method, an optical plate such as a parallax barrier and a lenticular lens is generally used to realize a stereoscopic image by separating an optical axis of a left and right parallax image.

As an example of the stereoscopic image display device of the glasses type, US Patent US 5,821,989, US Application Publication US 2007022949A1 and the like are known.

1 is a view schematically showing a three-dimensional image display device of the glasses method. The portion indicated in black in the shutter glasses ST is a shutter that blocks light traveling toward the viewer, and the portion indicated in white represents a shutter that transmits light toward the viewer.

Referring to FIG. 1, the left eye image data RGB _L is written in the display element DIS during the odd frame period, and the left eye shutter of the shutter glasses ST is opened. During the even frame period, the right eye image data RGB _R is written into the display element DIS and the right eye shutter of the shutter glasses ST is opened. Therefore, the observer sees only the left eye image during the odd frame and only the right eye image during the excellent frame period, so that the viewer can feel a three-dimensional effect.

The display device may display a two-dimensional plane image (hereinafter referred to as "2D image") in the 2D mode and a stereoscopic image (hereinafter referred to as "3D image") in the 3D mode. The 3D image includes a left eye image and a right eye image. In the 3D mode, since the left eye image data and the right eye image data are included, the 3D image has more data than the 2D image.

In order to reduce crosstalk between the left eye image and the right eye image in the 3D mode, the vertical blank time can be extended and the shutter glasses can be opened within the vertical blank period. In this case, the actual data period minus the vertical blank period within the frame period during which the 3D image is displayed becomes smaller than that of the frame period during which the 2D image is displayed. As a result, one horizontal period of the 3D image is shorter than one horizontal period of the 2D image.

The data driving circuit for supplying data to the data line of the display element DIS shortens one horizontal period of the 3D image, thereby making the data transition time shorter than that of the 2D image when outputting the data of the 3D image. As a result, power consumption of the data driving circuit can be greatly increased in the 3D image. In particular, when driving a liquid crystal display device inverting the polarity of data with a single dot inversion, the data driving circuit must invert the polarity of the data voltage every horizontal period, so that the power consumption and the amount of heat generated when the 3D image is output increase rapidly.

The present invention provides a stereoscopic image display device and a driving method thereof to reduce power consumption in a 3D mode.

The stereoscopic image display device of the present invention includes a display panel for displaying a 2D image in the 2D mode and a 3D image in the 3D mode; A data driving circuit converts digital video data into a positive gamma compensation voltage and a negative gamma compensation voltage and outputs the data to the data lines of the display panel and inverts the polarities of the data voltages to be output to the data lines in response to a polarity control signal. in; A gate driving circuit which sequentially supplies gate pulses to gate lines of the display panel; And a timing controller for generating the polarity control signal and controlling the inversion period of the polarity control signal longer in the 3D mode than in the 2D mode.

The driving method of the stereoscopic image display apparatus includes supplying a 2D image to a display panel in a 2D mode; Controlling a vertical polarity inversion period of the 2D image supplied to the display panel as a first period; Supplying a 3D image to the display panel in the 3D mode; And controlling the vertical polarity inversion period of the 3D image supplied to the display panel to a second period longer than the first period.

When the image data of the 3D mode is supplied to the display panel, the present invention can control the vertical polarity inversion period of the image data longer than the 2D mode to reduce power consumption of the 3D mode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Component names used in the following description may be selected in consideration of the ease of preparation of the specification, and may be different from the part names of actual products.

Referring to FIG. 2, a stereoscopic image display device according to an exemplary embodiment of the present invention includes a display panel 100, a timing controller 101, a data driving circuit 102, a gate driving circuit 103, a system board 104, And shutter glasses 130.

In the display panel 100, a liquid crystal layer is formed between two glass substrates. The display panel 100 includes liquid crystal cells arranged in a matrix by a cross structure of the data lines 105 and the gate lines 106.

Data lines 105, gate lines 106, thin film transistors (TFTs), and storage capacitors (Cst) are formed on the lower glass substrate of the display panel 100. The liquid crystal cells are connected to the TFT and driven by an electric field between the pixel electrodes and the common electrode. A black matrix, a color filter, and a common electrode are formed on the upper glass substrate of the display panel 100. A polarizing plate is attached to each of the upper and lower glass substrates of the display panel 100 to form an alignment layer for setting the pre-tilt angle of the liquid crystal. The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. The driving method is formed on the lower glass substrate together with the pixel electrode.

The display panel 100 applicable to the present invention may be implemented in any liquid crystal mode as well as in the TN mode, VA mode, IPS mode, FFS mode. The liquid crystal display of the present invention can be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 101 supplies digital video data RGB input from the system board 104 to the data driving circuit 102. In addition, the timing controller 101 inputs timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable, DE, and a dot clock CLK from the system board 104. In response, the control signals for controlling the operation timing of the data driving circuit 102 and the gate driving circuit 103 are generated. The control signals include a gate timing control signal for controlling the operation time of the gate driving circuit 103, and a data timing control signal for controlling the operation timing of the data driving circuit 102 and the polarity of the data voltage.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse (GSP) is applied to a gate drive integrated circuit (IC) that generates the first gate pulse to control the gate drive IC to generate the first gate pulse. The gate shift clock GSC is a clock signal commonly input to gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (Source Output Enable, SOE). And the like. The source start pulse SSP controls the data sampling start timing of the data driving circuit. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the data driving circuit 102 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltage output from the data driving circuit 102. The source output enable signal SOE controls the output timing of the data driver circuit 102. If the digital video data to be input to the data driving circuit 102 is transmitted in mini LVDS (Low Voltage Differential Signaling) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted.

The timing controller 101 extends the period of the polarity control signal POL longer in the 3D mode than in the 2D mode in order to reduce the power consumption and the amount of heat generated by the data driving circuit 102 in the 3D mode. As a result, the data driving circuit 102 reduces the number of times of polarity inversion of the data voltage when outputting the data voltage in the 3D mode. The frame frequency in the 3D mode is as high as 60 x i (i is an integer of 2 or more). Accordingly, the user hardly feels flicker even when the polarity inversion period of the data voltage supplied to the display panel 100 is long.

Each of the source drive ICs of the data driver circuit 102 includes a shift register, a latch, a digital-to-analog converter, an output buffer, and the like. The data driving circuit 102 latches the digital video data RGB under the control of the timing controller 101. The data driving circuit 102 converts the digital video data RGB into analog positive and negative gamma compensation voltages in response to the polarity control signal POL to invert the polarity of the data voltages. The data driving circuit 102 inverts the polarities of the data voltages output to the data lines 105 in response to the polarity control signal POL.

The gate driving circuit 103 sequentially supplies gate pulses to the gate lines 106 in response to gate timing control signals.

The system board 104 timings data and timing signals (Vsync, Hsync, DE, CLK) of 2D or 3D video through an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. Supply to the controller 101. The system board 104 supplies a 2D image to the timing controller 101 in the 2D mode, while supplying a 3D image including a left eye image and a right eye image in the 3D mode to the timing controller 101. As shown in FIG. 3, the system board 104 transmits data of a 2D image at a frame frequency of 60 Hz or 60 x iHz in a 2D mode. In contrast, the system board 104 transmits the data of the 3D image at a frame frequency of 60 x iHz in the 3D mode as shown in FIG.

When the user simultaneously views the left eye image (or right eye image) of the previous frame displayed on the display panel 100 and the right eye image (or left eye image) scanned on the current frame, the user may feel crosstalk of the left and right eye images. The system board 104 extends the vertical blank period VBI of the 3D mode longer than that of the 2D mode and prevents the shutter glasses 130 only within the vertical blank period VBI to prevent crosstalk of the left and right eye images. Open the left eye shutter (ST _L ) or right eye shutter (ST _R ) of the camera.

The user may select a 2D mode and a 3D mode through the user interface 110. The user interface 110 includes a touch screen attached to or embedded in the display panel 100, an on screen display (OSD), a keyboard, a mouse, a remote controller, and the like. The system board 104 switches between 2D mode operation and 3D mode operation in response to user data input through the user interface 110. The system board 104 may switch the operation of the 2D mode and the operation of the 3D mode through the 2D / 3D identification code encoded in the data of the input image.

The system board 104 opens the left eye shutter ST _L of the shutter glasses 130 to be synchronized with the vertical blank period of the left eye image frame in the 3D mode, while the shutter eyeglasses 130 are synchronized with the vertical blank period of the right eye image frame. ) Open the right eye shutter (ST _L ). To this end, the system board 104 outputs a shutter control signal to the shutter control signal transmitter 120, and the shutter control signal transmitter 120 transmits the shutter control signal to the shutter control signal receiver 121 through a wired / wireless interface. send. The shutter control signal receiver 121 may be built in the shutter glasses 130 or manufactured as a separate module and attached to the shutter glasses 130.

The shutter glasses 130 include a left eye shutter ST _L and a right eye shutter ST _R that are electrically controlled separately. Each of the left eye shutter ST _L and the right eye shutter ST _R may include a first transparent substrate, a first transparent electrode formed on the first transparent substrate, a second transparent substrate, and a second transparent electrode formed on the second transparent substrate, And a liquid crystal layer sandwiched between the first and second transparent substrates. The reference voltage is supplied to the first transparent electrode and the ON / OFF voltage is supplied to the second transparent electrode. Each of the left eye shutter ST _L and the right eye shutter ST _R transmits light from the display panel 100 when the ON voltage is supplied to the second transparent electrode, while the OFF voltage is supplied to the second transparent electrode. Light from the display panel 100 is blocked.

The shutter control signal receiver 121 is installed in the shutter glasses 130 to receive a shutter control signal through a wired / wireless interface, and according to the shutter control signal, the left eye shutter ST _L and the right eye shutter ( Open and close ST _R ) alternately. When the shutter control signal is input to the shutter control signal receiver 121 as the first logic value, the ON voltage is supplied to the second transparent electrode of the left eye shutter ST _L , while the second of the right eye shutter ST _R is supplied. OFF voltage is supplied to the transparent electrode. When the shutter control signal is input to the shutter control signal receiver 121 as the second logic value, the OFF voltage is supplied to the second transparent electrode of the left eye shutter ST _L , while the second of the right eye shutter ST _R is supplied. The ON voltage is supplied to the transparent electrode. Accordingly, the left eye shutter ST _L of the shutter eyeglasses 130 is opened when the shutter control signal is generated as the first logic value, and the right eye shutter ST _R of the shutter eyeglasses 130 is the second logic of the shutter control signal. Open when generated by value.

4 is a diagram illustrating data polarity of a 2D image according to a first embodiment of the present invention. 5 is a diagram illustrating data polarity of a 3D image according to a first embodiment of the present invention.

Referring to FIG. 4, the data driving circuit 102 inverts the data voltage of the 2D image to horizontal 1 dot and vertical 1 dot inversion in response to the polarity control signal POL in the 2D mode. In the display panel 100, horizontally neighboring data voltages are inverted in polarity by one dot (or liquid crystal cell), and vertically neighboring data voltages are inverted in polarity by one dot. To this end, the logic control signal POL generated in the 2D mode is inverted in units of one horizontal period (1H) and inverted every frame period.

Referring to FIG. 5, the data driving circuit 102 inverts the data voltage of the 3D image to column inversion in response to the polarity control signal POL in the 3D mode. In the display panel 100, horizontally neighboring data voltages are inverted in polarity by one dot (or liquid crystal cell), and vertically neighboring data voltages are the same. For this purpose, the polarity control signal POL generated in the 3D mode is kept in the same logic within one frame period and inverted every frame period. Therefore, the data driving circuit 102 does not invert the polarity of the data voltage output in the 3D mode within one frame period, thereby reducing power consumption.

6 is a diagram illustrating data polarity of a 2D image according to a second embodiment of the present invention. 7 is a diagram illustrating data polarity of a 3D image according to a second embodiment of the present invention.

Referring to FIG. 6, the data driving circuit 102 inverts the data voltage of the 2D image to horizontal 1 dot and vertical 2 dot inversion in response to the polarity control signal POL in the 2D mode. In the display panel 100, horizontally neighboring data voltages are inverted in polarity in units of 1 dot, and vertically neighboring data voltages are inverted in polarities in units of 2 dots. For this purpose, the logic control signal POL generated in the 2D mode is inverted in units of two horizontal periods 2H and inverted every frame period.

Referring to FIG. 7, the data driving circuit 102 inverts the data voltage of the 3D image to horizontal 1 dot and vertical 4 dot inversion in response to the polarity control signal POL in the 3D mode. In the display panel 100, horizontally neighboring data voltages are inverted in polarity by 1 dot unit, and vertically neighboring data voltages are inverted in polarity by 4 dot unit. To this end, the polarity control signal POL generated in the 3D mode is inverted in units of 4 horizontal periods 4H within one frame period and inverted every frame period. Therefore, the data driving circuit 102 can reduce power consumption by lengthening the polarity inversion period of the data voltage output in the 3D mode to be equal to or greater than the polarity inversion period of the data voltage output in the 2D mode. The data driving circuit 102 inverts the vertical polarity of the data voltage output in the 2D mode in units of j (j is a positive integer) horizontal period, while k (k is j). Greater positive integer).

8 is a flowchart illustrating a method of driving a stereoscopic image display device according to an exemplary embodiment of the present invention.

Referring to FIG. 8, the driving method of the stereoscopic image display device inputs a 2D image to the display device in 2D mode and controls the polarity of the data voltage supplied to the display device by dot inversion (S1 and S2). The data voltage of the 2D image supplied to the apparatus is not limited to dot inversion. For example, the data voltage of the 2D image supplied to the display device may be inverted by line inversion.

In the driving method of the stereoscopic image display device, the 3D image is input to the display device in 3D mode and the polarity of the data voltage supplied to the display device is controlled by column inversion (S3 and S4). The data voltage of is not limited to column inversion. For example, the data voltage of the 3D image supplied to the display device may be inverted to a dot inversion having a longer vertical polarity reversal period than the dot inversion of the 2D image as described above.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the present invention should not be limited to the details described in the detailed description but should be defined by the claims.

1 is a view illustrating a time division operation of left and right images in a stereoscopic image display device using glasses.

2 is a block diagram illustrating a stereoscopic image display device according to an exemplary embodiment of the present invention.

3 is a waveform diagram illustrating a frame frequency of a 2D image and a frame frequency of a 3D image.

4 is a diagram illustrating data polarity of a 2D image according to a first embodiment of the present invention.

5 is a diagram illustrating data polarity of a 3D image according to a first embodiment of the present invention.

6 is a diagram illustrating data polarity of a 2D image according to a second embodiment of the present invention.

7 is a diagram illustrating data polarity of a 3D image according to a second embodiment of the present invention.

8 is a flowchart illustrating a method of driving a stereoscopic image display device according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

100: display panel 101: timing controller

102: data driving circuit 103: gate driving circuit

104: system board 130: shutter glasses

Claims (9)

A display panel displaying a 2D image in a 2D mode and a 3D image in a 3D mode; A data driving circuit converts digital video data into a positive gamma compensation voltage and a negative gamma compensation voltage and outputs the data to the data lines of the display panel and inverts the polarities of the data voltages to be output to the data lines in response to a polarity control signal. in; A gate driving circuit which sequentially supplies gate pulses to gate lines of the display panel; And And a timing controller for generating the polarity control signal and controlling the inversion period of the polarity control signal longer in the 3D mode than in the 2D mode. The method of claim 1, And shutter glasses in which the left eye shutter and the right eye shutter are alternately turned on / off in synchronization with the 3D image displayed on the display panel in the 3D mode. And the timing controller supplies the digital video data to the data driving circuit, and controls an operation timing of the data driving circuit, the gate driving circuit, and the shutter glasses. The method of claim 1, The polarity of the data voltages charged in the liquid crystal cells of the display panel is inverted to dot inversion in the 2D mode, and inverted to column inversion in the 3D mode. The method of claim 1, The polarity of the data voltages charged in the liquid crystal cells of the display panel is inverted to the line inversion in the 2D mode, and inverted to the column inversion in the 3D mode. The method of claim 1, Polarities of the data voltages charged in the liquid crystal cells of the display panel are inverted to a vertical j (j is a positive integer) dot inversion in the 2D mode, and k (k is a positive integer greater than j) in the 3D mode. And a stereoscopic image display device which is inverted to dot inversion. Supplying a 2D image to a display panel in a 2D mode; Controlling a vertical polarity inversion period of the 2D image supplied to the display panel as a first period; Supplying a 3D image to the display panel in the 3D mode; And And controlling a vertical polarity inversion period of the 3D image supplied to the display panel to a second period longer than the first period. The method of claim 6, And controlling the on / off control of the left eye shutter and the right eye shutter of the shutter glasses alternately in synchronization with the 3D image displayed on the display panel in the 3D mode. The method of claim 1, And generating a polarity control signal for controlling the polarity of the data voltages to be supplied to the data lines of the display panel. The method of claim 8, The controlling of the vertical polarity inversion period of the 3D image supplied to the display panel to a second period longer than the first period may include: And controlling the inversion period of the polarity control signal longer in the 3D mode than in the 2D mode.

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