KR101356248B1 - Image display device - Google Patents

Abstract

The present invention relates to an image display apparatus capable of selectively implementing a two-dimensional plane image (hereinafter, referred to as a '2D image') and a three-dimensional stereoscopic image (hereinafter, referred to as a '3D image').
The image display device includes a liquid crystal display panel in which a 2D image and a 3D image are selectively implemented; A panel driving circuit for driving the liquid crystal display panel; A backlight for irradiating light onto the liquid crystal display panel including a plurality of light sources; And modulating the input data to generate frame data synchronized with N (N is a positive integer of 4 or more) double frame frequency, and then controlling the panel driving circuit so that the same frame data is displayed on the liquid crystal display panel for two consecutive frame periods. And a control circuit for extinguishing the backlight during the first half of the two frame periods assigned to the same frame data display, and controlling the backlight to turn on within the second half of the two frame periods.

Description

IMAGE DISPLAY DEVICE [0002]

The present invention relates to an image display apparatus capable of selectively implementing a two-dimensional plane image (hereinafter, referred to as a '2D image') and a three-dimensional stereoscopic image (hereinafter, referred to as a '3D image').

The image display device implements a 3D image using a binocular stereoscopic technique or an autostereoscopic technique.

The binocular parallax method uses parallax images of right and left eyes with large stereoscopic effect, and both glasses and non-glasses are used, and both methods are practically used. In the non-eyeglass system, an optical plate such as a parallax barrier for separating the optical axis of left and right parallax images is installed in front of or behind the display screen. The spectacle method displays left and right parallax images having different polarization directions on a liquid crystal display panel, and realizes a stereoscopic image using polarized glasses or liquid crystal shutter glasses.

The spectacle method is largely divided into a first polarization filter method using a pattern retarder film and polarizing glasses, a second polarization filter method using a switching liquid crystal layer and polarizing glasses, and a liquid crystal shutter eyeglass method. In the first and second polarization filter methods, the transmittance of the 3D image is low due to the pattern retarder film or the switching liquid crystal layer disposed on the liquid crystal display panel to serve as a polarization filter.

In the liquid crystal shutter glasses system, a left-eye image and a right-eye image are alternately displayed on a display unit in frame units, and a left-eye and right-eye shutter of the liquid crystal shutter glasses is opened and closed in synchronization with the display timing. The liquid crystal shutter eyeglasses create binocular parallax in a time division manner by opening only his left eye shutter during the nth frame period during which the left eye image is displayed, and opening only his right eye shutter during the n + 1 frame period during which the right eye image is displayed.

Recent image display apparatuses mainly use a hold type display element such as a liquid crystal display (LCD) to selectively implement 3D images and 2D images. In view of the response time of the relatively slow liquid crystal, the liquid crystal display maintains the data charged in the previous frame until just before new data is written.

Due to the response time delay characteristic of the liquid crystal, a ghost type 3D crosstalk may be visualized at a time of changing from a left eye image to a right eye image or a time of changing from a right eye image to a left eye image when the 3D image is implemented through the image display device. . Briefly explaining the principle of 3D crosstalk is as follows.

Assuming that the left eye shutter of the liquid crystal shutter eyeglasses is opened in the nth frame period and the right eye shutter of the liquid crystal shutter eyeglasses is opened in the n + 1th frame period, the liquid crystal display device sequentially addresses left eye image data for the nth frame period. The right eye image data is sequentially addressed during the n + 1th frame period. While the left eye shutter of the liquid crystal shutter glasses is open, some pixels for which the left eye image data of the nth frame has not yet been written (pixels under the lower addressing panel) are already filled in the nth frame. Keep your data. Therefore, not only the left eye image of the nth frame but also some right eye images of the n−1th frame are superimposed on the left eye of the observer. In addition, while the right eye shutter of the liquid crystal shutter glasses is open, some pixels (pixels under the slow addressing panel) in which the right eye image data of the n + 1th frame has not been written yet are already filled in the nth frame. Maintain left eye image data. Therefore, not only the right eye image of the n + 1th frame but also some left eye image of the nth frame are superimposed on the observer's right eye.

On the other hand, due to the retention characteristics of the liquid crystal, when the 2D video is implemented through the image display device, motion blurring may appear that the screen is not clear and blurry. In order to eliminate motion blur, the moving picture response time (hereinafter referred to as "MPRT") must be improved.

Accordingly, an object of the present invention is to provide an image display device capable of improving the display quality.

In order to achieve the above object, an image display apparatus according to an embodiment of the present invention comprises a liquid crystal display panel that is selectively implemented 2D image and 3D image; A panel driving circuit for driving the liquid crystal display panel; A backlight for irradiating light onto the liquid crystal display panel including a plurality of light sources; And modulating the input data to generate frame data synchronized with N (N is a positive integer of 4 or more) double frame frequency, and then controlling the panel driving circuit so that the same frame data is displayed on the liquid crystal display panel for two consecutive frame periods. And a control circuit for extinguishing the backlight during the first half of the two frame periods assigned to the same frame data display, and controlling the backlight to turn on within the second half of the two frame periods.

The image display device according to the present invention can greatly improve the display quality by improving MPRT when implementing 2D images and preventing 3D crosstalk generation when implementing 3D images.

1 is a block diagram illustrating an image display device according to an embodiment of the present invention.
2 is a block diagram showing an example of a control circuit.
3 to 8 illustrate various embodiments of driving timings of a light source control signal and a liquid crystal shutter control signal corresponding to an addressing timing of frame data;
9 is a block diagram showing another example of a control circuit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 9.

1 shows an image display apparatus according to an embodiment of the present invention.

Referring to FIG. 1, an image display device according to an exemplary embodiment of the present invention may include a liquid crystal display panel 10, a control circuit 11, a data driving circuit 12, a gate driving circuit 13, and a light source driving circuit 14. , A backlight unit 15, and liquid crystal shutter glasses 16. The data driving circuit 12 and the gate driving circuit 13 constitute a panel driving circuit.

The liquid crystal display panel 10 includes two glass substrates and a liquid crystal layer formed therebetween. A plurality of data lines DL and a plurality of gate lines GL are intersected with each other on a lower glass substrate of the liquid crystal display panel 10. [ The liquid crystal cells Clc are arranged in a matrix form in the liquid crystal display panel 10 by the intersection structure of the data lines DL and the gate lines GL. In the lower glass substrate of the liquid crystal display panel 10, TFTs, pixel electrodes 1 of liquid crystal cells Clc connected to TFTs, storage capacitors Cst, and the like are formed. On the upper glass substrate of the liquid crystal display panel 10, a black matrix, a color filter, and a common electrode 2 are formed. The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, a polarizing plate is attached and an alignment film for forming a pre-tilt angle of the liquid crystal is formed on the inner surface in contact with the liquid crystal.

The data driver circuit 12 includes a plurality of data drive integrated circuits. The data drive integrated circuit includes a shift register for sampling a clock signal, a register for temporarily storing digital data input from the control circuit 11, and one line for storing data one line in response to a clock signal from the shift register. A latch for simultaneously outputting minute data, a digital / analog converter for selecting a positive / negative gamma voltage under reference to a gamma reference voltage corresponding to a digital data value from the latch, and a positive / negative gamma voltage And a multiplexer for selecting a data line DL to which analog data converted by the same is supplied, and an output buffer connected between the multiplexer and the data line DL. The data driving circuit 12 converts 2D / 3D data synchronized with a frame frequency of f (input frame frequency) × N (N is a positive integer of 4 or more) to analog data voltages and supplies them to the data lines DL. do.

The gate driving circuit 13 includes a plurality of gate drive integrated circuits. The gate drive integrated circuit includes a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for driving a TFT of a liquid crystal cell, an output buffer, and the like. The gate driving circuit 13 sequentially outputs scan pulses (or gate pulses) synchronized with a frame frequency of f × N Hz and supplies them to the gate lines GL.

The light source driving circuit 14 generates driving power for turning on the light sources. The light source driving circuit 14 supplies the driving power to the light sources at predetermined time periods under the control of the control circuit 11.

The backlight unit 15 is turned on for a predetermined time, irradiates light to the liquid crystal display panel 10, and turns off for other periods, and periodically turns on / off the light. The backlight unit 15 includes a plurality of light sources, a light guide plate (or a diffusion plate), a plurality of optical sheets, and the like, which light up according to the driving power supplied from the light source driving circuit 14. The backlight unit 15 may be implemented in a direct type or an edge type. The light sources may include any one type of hot cathode fluorescent lamp (HCFL), cold cathode fluorescent lamp (CCFL), external electrode fluorescent lamp (EEFL), or light emitting diode (LED).

The liquid crystal shutter glasses 16 includes a left eye shutter STL and a right eye shutter STR that are electrically controlled individually. Each of the left eye shutter STL and the right eye shutter STR includes a first transparent substrate, a first transparent electrode formed on the first transparent substrate, a second transparent substrate, a second transparent electrode formed on the second transparent substrate, and a first transparent substrate. And a liquid crystal layer sandwiched on the second transparent substrate. A reference voltage is supplied to the first transparent electrode and an ON / OFF voltage is supplied to the second transparent electrode. Each of the left eye shutter STL and the right eye shutter STR transmits light from the display panel 15 when the ON voltage is supplied to the second transparent electrode under the control of the control circuit 11. When the OFF voltage is supplied, it blocks the light from the display panel.

The control circuit 11 receives timing signals and 2D / 3D data from a video source (not shown). The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a dot clock DCLK, and the like.

The control circuit 11 multiplies the frame frequency by N times the input frame frequency f and displays the display panel control signals DDC and GDC on the basis of the multiplied frame frequency (hereinafter referred to as "N double frame frequency") Nf, The light source control signal CBL and the liquid crystal shutter control signal CST are generated.

The display panel control signals DDC and GDC are data control signals DDC for controlling the operation timing of the data driving circuit 12 and gate control signals GDC for controlling the operation timing of the gate driving circuit 13. It includes. The data control signal DDc includes a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE), a polarity control signal (POL), and the like. It includes. The gate control signal GDC includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The light source control signal CBL controls the light source driving circuit 14 to periodically turn on and off the light sources of the backlight unit 15. The liquid crystal shutter control signal CST alternately opens and closes the left eye shutter STL and the right eye shutter STR of the liquid crystal shutter glasses 16 at predetermined intervals.

The control circuit 11 selects any one of the 2D / 3D data input from the video source according to the first selection signal SEL1 and modulates the data so as to be synchronized with the N times frame frequency Nf. When 2D data is selected, the control circuit 11 may modulate the data through data interpolation and data doubling. In addition, when 2D data is selected, the control circuit 11 selects one of the first modulation path including data interpolation and data doubling and the second modulation path including only data interpolation according to the second selection signal SEL2. After selection, data can be modulated via the selected modulation path. When 3D data is selected, the control circuit 11 may modulate the data through data separation and data doubling. The control circuit 11 may control the driving circuits 12 and 13 so that the same data is displayed every two consecutive frame periods. To this end, the control circuit 11 may control the driving circuits 12 and 13 to repeatedly write the same frame data to the display panel 10 for two frame periods or to write only once for two frame periods. . The control circuit 11 modulates the vertical blank section and increases the transmission frequency of the data, thereby reducing the time required for writing the frame data.

Hereinafter, various embodiments of the image display device of the present invention will be described in detail with reference to FIGS. 2 to 9. In the embodiment, the case where "N" is 4, that is, 240 Hz corresponding to an input frame frequency of 60 Hz will be described as an example. "A", "B", and "C" shown in FIGS. 3 to 8 mean 2D data, and "L" and "R" mean 3D data.

2 shows an example of the control circuit 11.

Referring to FIG. 2, the control circuit 11 includes a data processor 111, a timing controller 112, and a light source controller 113.

The data processing unit 111 performs data modulation so that the input 2D / 3D data is synchronized with the 4x frame frequency 4f. To this end, the data processing unit 111 includes a data selection unit 111A, a first 2D data interpolation unit 111C, a 2D data distribution unit 111D, and a 3D data distribution unit 111F.

The data selector 111A bypasses the input 2D data in response to the first logic value of the first selection signal SEL1 while blocking 3D data, and responds to the second logic value of the first selection signal SEL1. Block 2D data and process and output the input 3D data. In processing the input 3D data, the data selector 111A includes the 3D formatter 111A 'to separate the input 3D data into left eye data and right eye data so that the double speed 3D data is synchronized to the double frame frequency 2f. Occurs. Further, in processing the input 3D data, the data selector 111A judges a frame based on a count value for a timing signal such as a vertical synchronization signal Vsync, and the liquid crystal shutter glasses 16 at intervals of two frame periods. A liquid crystal shutter control signal CST capable of simultaneously opening and closing the left eye shutter STL and the right eye shutter STR in turn is generated. In particular, the data selector 111A refers to the logic value of the light source control signal CBL, so that the opening and closing points of the shutters STL and STR can be simultaneously determined within the light-out period of the light sources. To control.

The first 2D data interpolator 111C interpolates the input 2D data bypassed by the data selector 111A to generate double speed 2D data synchronized with the double frame frequency 2f. For data interpolation, the first 2D data interpolator 111C inserts interpolation frame data between adjacent input frame data with reference to a memory (not shown).

The 2D data double speed unit 111D doubling the double speed 2D data from the first 2D data interpolation unit 111C to generate quadruple speed 2D data, and then supply it to the timing controller 112. For data doubling, the 2D data double speed 111D inserts doubling frame data every adjacent double double speed frame data with reference to a memory. Here, the doubling frame data refers to frame data having the same value as any one frame data among neighboring double speed frame data.

The 3D data double speed 111F doubling the double speed 3D data from the data selector 111A to generate quadruple speed 3D data, and then supply it to the timing controller 112. For data doubling, the 3D data double speed 111F inserts doubling frame data every adjacent double double speed frame data with reference to the memory.

The data processor 111 may further include a modulation path selector 111B and a second 2D data interpolator 111E. The second 2D data interpolator 111E interpolates the input 2D data bypassed by the data selector 111A to generate quadruple speed 2D data synchronized with the quadruple frame frequency 4f. For data interpolation, the second 2D data interpolator 111E inserts three interpolation frame data for each adjacent input frame data with reference to the memory. The modulation path selector 111B includes a first modulation path passing through the first 2D data interpolation unit 111C and the 2D data double speed unit 111D and the second 2D data interpolation unit according to the second selection signal SEL2. Any one of the second modulation paths via 111E can be selected.

The timing controller 112 rearranges 4X speed 2D data and 4X speed 3D data selectively input from the data processor 111 to match the resolution of the liquid crystal display panel 10. The same frame data is repeatedly supplied to the data driving circuit 12 for two frame periods, or only once for two frame periods. The timing controller 112 generates the display panel control signals DDC and GDC in synchronization with the 4x frame frequency 4f based on the timing signals Vsync, Hsync, DE, and DCLK. Control the operation of The timing controller 112 may control the driving circuits 12 and 13 such that the odd-numbered frames or the even-numbered frames are selectively idle-driven. In addition, the timing controller 112 modulates the data enable signal DE to widen the vertical blank period and modulate the dot clock DCLK to increase the transmission frequency of data. Modulation of the data enable signal DE and the dot clock DCLK may be performed by an external system board (not shown).

The light source controller 113 generates a light source control signal CBL for controlling the on / off of the light sources. The light source controller 113 inverts the logic value of the light source control signal CBL based on the timing signals Vsync, Hsync, DE, and DCLK. The light source control unit 113 generates a light source control signal CBL with low logic during the first half frame period of two frame periods allocated to the same frame data display to turn off the light sources, and the light source within the second half frame period during the two frame periods. The control signal CBL is generated with high logic to control lighting of the light sources. In particular, in order to control the lighting period of the light sources, the light source control unit 113 generates the light source control signal CBL in high logic at least one frame period after the initial data addressing point of the first half frame period, and then generates this logic value in the second half. It can be maintained until the end of the frame period. The light source controller 113 may be built in the data processor 111 or the timing controller 112.

FIG. 3 shows a first embodiment of driving timing of a light source control signal CBL and a liquid crystal shutter control signal CST corresponding to an addressing timing of frame data.

When the 2D image is implemented as shown in FIG. 3, the control circuit 11 controls the driving circuits 12 and 13 so that the same over the n + 1 to n + 2 frame periods (Fn + 1 to Fn + 2). The 4x 2D data A is repeatedly addressed to the liquid crystal display panel 10, and the same 4x 2D data B is applied over the n + 3 to n + 4 frame periods (Fn + 3 to Fn + 4). Is repeatedly addressed to the liquid crystal display panel 10, and the same quadruple speed 2D data C is applied over the n + 5 to n + 6 frame periods (Fn + 5 to Fn + 6). Address repeatedly. Data addressing for the liquid crystal response is completed in the n + 1, n + 3, and n + 5 frame periods (Fn + 1, Fn + 3, Fn + 5) (hereinafter, the "full frame period"). . Although the liquid crystal response may be completed within the first half frame period in the upper portion of the liquid crystal display panel 10 having a relatively rapid data addressing order, the completion point of the liquid crystal response may be observed in the lower portion of the liquid crystal display panel 10 having a relatively late data addressing order. It can extend to the n + 2, n + 4, n + 6th frame periods (Fn + 2, Fn + 4, Fn + 6) (hereinafter referred to as the "second half frame period"). The reason for repeatedly addressing the same data (A, B, C) as the previous frame in the second half frame period is to compensate for the posture holding power of the liquid crystal. The control circuit 11 takes into account the time taken for the liquid crystals of the liquid crystal display panel 10 to complete response by the data A, B, and C addressed in the first half frame period, and thus the first data addressing in the first half frame period. The light sources are turned on only after 1.5 frame periods have elapsed from the time points St1, St2, and St3 until the second half frame period ends. As a result, the MPRT is greatly improved when the 2D image is implemented, and in particular, the uniformity of the MPRT is excellent in the entire area of the liquid crystal display panel 10.

In realizing the 3D image, the control circuit 11 controls the driving circuits 12 and 13 so that the same over the n + 1 to n + 2 frame periods (Fn + 1 to Fn + 2, the left eye frame period). The 4x 3D data L is repeatedly addressed to the liquid crystal display panel 10, and the same 4x 3D data is applied over the n + 3 to n + 4 frame periods (Fn + 3 to Fn + 4, the right eye frame period). The data R is repeatedly addressed to the liquid crystal display panel 10, and the same quadruple speed 3D data L is applied over the n + 5 to n + 6 frame periods (Fn + 5 to Fn + 6, the left eye frame period). ) Is repeatedly addressed to the liquid crystal display panel 10. Data addressing for the liquid crystal response is completed within the first half frame period. Although the liquid crystal response may be completed within the first half frame period in the upper portion of the liquid crystal display panel 10 having a relatively rapid data addressing order, the completion point of the liquid crystal response may be observed in the lower portion of the liquid crystal display panel 10 having a relatively late data addressing order. It can be extended to the second half frame period. The reason for repeatedly addressing the same data (L, R, L) as the previous frame in the second half frame period is to compensate for the posture holding power of the liquid crystal. The control circuit 11 takes into account the time taken for the liquid crystals of the liquid crystal display panel 10 to complete response by the data L, R, and L addressed in the first half frame period, and thus the first data addressing in the first half frame period. The light sources are turned on only after 1.5 frame periods have elapsed from the time points St1, St2, and St3 until the second half frame period ends. Then, the control circuit 11 has a left eye shutter STL of the liquid crystal shutter glasses 16 so as to overlap with the lighting period of the light sources within the left eye frame periods Fn + 1 to Fn + 2 and Fn + 5 to Fn + 6. While controlling the opening and closing the right eye shutter (STR). The control circuit 11 controls the opening of the right eye shutter STR of the liquid crystal shutter glasses 16 so as to overlap with the lighting period of the light sources within the right eye frame periods Fn + 3 to Fn + 4, and at the same time the left eye shutter STL. Control closed. At this time, the opening and closing time point Ct1 of the shutters STL and STR is made within the light-out period of the light sources. In this way, when the lighting timing of the light sources is adjusted together with the shutter opening timing adjustment, 3D crosstalk is drastically reduced. In addition, since the opening / closing time point Ct1 of the shutters STL and STR may be determined at any point within the light-out period of the light sources, the timing margin when designing the opening / closing time point Ct1 in consideration of the liquid crystal response of the liquid crystal shutter glasses 16 is increased. Remarkably good.

FIG. 4 shows a second embodiment of driving timing of the light source control signal CBL and the liquid crystal shutter control signal CST corresponding to the addressing timing of the frame data.

Referring to FIG. 4, the technique disclosed through the second embodiment has substantially the same functions and effects as the first embodiment except for driving the second half frame periods Fn + 2, Fn + 4, Fn + 6 in the idle mode. . For the idle driving, the control circuit 11 may selectively stop or stop both the operation of the data driving circuit 12 and the operation of the gate driving circuit 13 during the second half frame period. Such alternating idle driving is effective in reducing heat generation of the driving circuits 12 and 13 and reducing power consumption.

FIG. 5 shows a third embodiment of driving timing of the light source control signal CBL and the liquid crystal shutter control signal CST corresponding to the addressing timing of the frame data.

Referring to FIG. 5, the technique disclosed through the third embodiment shows that the addressing timing of the frame data and the driving timing of the light source control signal CBL and the liquid crystal shutter control signal CST are shifted to the right by one frame period as a whole. Except for the second embodiment, the action and effect are substantially the same.

FIG. 6 shows a fourth embodiment of driving timing of the light source control signal CBL and the liquid crystal shutter control signal CST corresponding to the addressing timing of the frame data.

Referring to FIG. 6, the technique disclosed through the fourth embodiment is substantially similar to the first embodiment except that the front porch (FP) included in the vertical blank section is extended. The front porch FP is defined as a period from the extinction point of the data enable signal DE indicating the end of data addressing within one frame period until the end point of the one frame period. The control circuit 11 extends the front porch FP to advance the end of the data enable signal DE and increases the transmission frequency of the data, thereby reducing the time required for addressing the frame data. As a result, the time devoted to the liquid crystal response in the two frame periods for the same frame data display is increased by that much. Accordingly, the technique of the fourth embodiment can increase the lighting period of the light sources compared to the first embodiment, which is effective in improving the luminance when implementing 2D / 3D images. According to the fourth embodiment, the lighting of the light sources is after 1.2 to 1.3 frame periods have elapsed from the initial data addressing points St1, St2, and St3 of the first half frame periods Fn + 1, Fn + 3, Fn + 5, respectively. Until the end of the last frame period.

FIG. 7 illustrates a fifth embodiment of driving timings of the light source control signal CBL and the liquid crystal shutter control signal CST corresponding to the addressing timing of the frame data.

Referring to FIG. 7, the technique disclosed through the fifth embodiment has substantially the same functions and effects as the fourth embodiment except that the back porch (BP) included in the vertical blank section is extended. The back porch BP is defined as a period from the start time of one frame period (time of occurrence of the vertical synchronization signal Vsync) to the time of generation of the data enable signal DE indicating the start of data addressing. The control circuit 11 extends the back porch BP by delaying the start time of the data enable signal DE and increases the transmission frequency of the data, thereby reducing the time required for addressing the frame data. As a result, the time devoted to the liquid crystal response in the two frame periods for the same frame data display is increased by that much. Accordingly, the technique of the fifth embodiment can increase the lighting period of the light sources compared to the first embodiment, which is effective in improving the luminance when implementing 2D / 3D images.

FIG. 8 shows a sixth embodiment of driving timing of the light source control signal CBL and the liquid crystal shutter control signal CST corresponding to the addressing timing of the frame data.

Referring to FIG. 8, the technology disclosed through the sixth embodiment is substantially the same as the fourth and fifth embodiments except that the front porch FP and the back porch BP included in the vertical blank section are simultaneously extended. Have the same action and effect.

9 shows another example of the control circuit 11.

Referring to FIG. 9, the control circuit 11 includes a data processor 111, a timing controller 112, and a light source controller 113.

The data processor 111 modulates the data so that the input 2D / 3D data is selectively synchronized with the 2x frame frequency 2f. To this end, the data processor 111 includes a data selector 111A and a 2D data interpolator 111C. The configuration and operation of the data selector 111A are substantially the same as described in FIG. The configuration and operation of the 2D data interpolator 111C are substantially the same as the first 2D data interpolator of FIG. 2.

The timing controller 112 functions substantially the same as that described with reference to FIG. 2 except that the 2D data distribution unit 111D and the 3D data distribution unit 111F are incorporated. The configuration and operation of the 2D data distribution section 111D and the 3D data distribution section 111F are substantially the same as those described with reference to FIG. 2.

The configuration and operation of the light source controller 113 are substantially the same as those described with reference to FIG. 2.

As described above, the image display apparatus according to the present invention can greatly improve the display quality by improving MPRT when implementing 2D images and preventing 3D crosstalk generation when implementing 3D images.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

11: control circuit 12: data drive circuit
13 gate driving circuit 14 light source driving circuit
15: backlight unit 16: liquid crystal shutter glasses
111: data processor 112: timing controller
113: light source control unit

Claims (10)

A liquid crystal display panel selectively implementing 2D and 3D images;
A panel driving circuit for driving the liquid crystal display panel;
A backlight for irradiating light onto the liquid crystal display panel including a plurality of light sources; And
One of the 2D / 3D input data is selected and modulated according to the first selection signal to generate frame data synchronized with N (N is a positive integer of 4 or more) double frame frequency, and the same frame data for two consecutive frame periods. Controls the panel driving circuit so that the LCD is displayed on the liquid crystal display panel, controls the backlight to be turned off during the first half of the two frame periods allocated to the same frame data display, and the second half of the two frame periods. A control circuit for controlling lighting of the backlight in the
When the 2D input data is selected according to the first selection signal, the control circuit modulates the 2D input data through first data interpolation and data doubling according to a second selection signal, or the second data through the second data interpolation. Modulate 2D input data,
When the 2D input data is modulated through the first data interpolation and data doubling, the control circuit interpolates the 2D input data to generate N / 2 times 2D data synchronized to an N / 2 times frame frequency, and then Double N / 2 times 2D data to generate frame data synchronized with the N times frame frequency,
And when the 2D input data is modulated through the second data interpolation, the control circuit interpolates the 2D input data to generate frame data synchronized with the N-fold frame frequency. The method of claim 1,
And the backlight is turned on at least one frame period after the first data addressing point of the first half frame period, and maintains this lighting state until the end of the second half frame period. delete The method of claim 1,
When the 3D image is implemented by selecting the 3D input data according to the first selection signal, the control circuit separates the 3D input data into left and right eye data and synchronizes N / 2 times frame frequency with N / 2 times frame frequency. And generating frame data synchronized with the N double frame frequency by doubling the N / 2x 3D data after generating the data. 5. The method of claim 4,
And the liquid crystal shutter glasses having left eye shutters and right eye shutters simultaneously opened and closed within an unlit period of the backlight for realizing the 3D image. The method of claim 1,
And the control circuit repeatedly supplies the same frame data to the panel driving circuit during the first half frame period and the second half frame period. The method of claim 1,
And the control circuit idlely drives any one of the first half frame period and the second half frame period. The method according to claim 6,
The control circuit expands the front porch by advancing the time of disappearing of the data enable signal instructing the end of the addressing of the frame data within one frame period, and increases the transmission frequency of the frame data. Device. The method according to claim 6,
The control circuit extends the back porch by delaying the generation time of the data enable signal instructing the start of addressing the frame data within one frame period, and increases the transmission frequency of the frame data. Device. The method according to claim 6,
The control circuit expands the front porch by advancing the expiration time of the data enable signal instructing the end of the addressing of the frame data within one frame period, and expands the front porch in the one frame period. And a back porch to be extended by delaying generation of an enable signal, and a transmission frequency of the frame data is increased.

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