KR101825577B1 - Programming method of nonvolatile memory device - Google Patents

Abstract

 A method of programming a non-volatile memory device is provided. A programming method of a nonvolatile memory device according to an embodiment of the present invention is a programming method of a nonvolatile memory device including a string in which a first selection transistor, a plurality of memory cells and a second selection transistor are connected in series, Applying a program voltage to the gates of the remaining memory cells, except for the memory cell closest to the select transistor; And applying a program voltage to a gate of a memory cell closest to the first select transistor.

Description

[0001] PROGRAMMING METHOD OF NONVOLATILE MEMORY DEVICE [0002]

The present invention relates to a method of operating a non-volatile memory device, and more particularly to a method of programming a non-volatile memory device.

There is an increasing demand for a nonvolatile memory device that can electrically program and erase data and does not require a refresh function to rewrite data at regular intervals.

In a NAND type flash memory device of a nonvolatile memory device, a plurality of memory cells are connected in series to form a single string by sharing drains or sources between adjacent memory cells, There is an advantage to storing information. Specifically, the string is configured by serially connecting a drain select transistor, a plurality of memory cells, and a source select transistor between a bit line and a common source line. The drain select transistor, the memory cells, and the source select transistor are gated and controlled by the drain select line, the word lines, and the source select line, respectively. In particular, memory cells whose control gates are connected to each other and share one word line are controlled by the word line and constitute one page.

In order to program such memory cells, an erase operation is first performed on the memory cells such that the memory cells have a negative threshold voltage. Then, the threshold voltage of the selected memory cell is increased by applying a high voltage, which is a program voltage, to the word line to which the program target memory cell is connected (hereinafter, selected word line). At this time, it goes without saying that the threshold voltages of memory cells that are not programmed (hereinafter referred to as program inhibited memory cells) should not be changed.

By the way, when a program voltage is applied to a selected word line in a program operation, the program voltage is also applied to the program inhibited memory cells sharing the word line with the program target memory cell, whereby the intention of the program inhibited memory cells connected to the selected word line A program phenomenon, i.e., a program disturb may occur.

As a technique for preventing such program disturb, there is a program inhibition method using a self-boosting method. In this method, the channel of the memory cell is floated by substantially turning off the source select transistor and the drain select transistor of the string connected to the unselected bit line. In this state, application of the program voltage to the selected word line can prevent programming of the program inhibited memory cells because the channel voltage of the program inhibited memory cells connected to the selected word line is boosted and the voltage difference with the word line is lowered.

However, as the degree of integration of nonvolatile memory devices increases, program disturb frequently occurs even if a program inhibition method using a self-boosting method is used.

Generally, a program for a memory cell is performed in the order of a memory cell closer to the source select transistor to a memory cell farther from the source select transistor. As the degree of integration increases, the distance between memory cells decreases. There is a phenomenon that the most interference occurs in programming of other memory cells and the threshold voltage is increased accordingly.

In addition, as the degree of integration increases, the gap between the source select transistor and the adjacent memory cell is also reduced, and when a program voltage is applied to the gate of the memory cell closest to the source select transistor in the non-selected string, A gate induced drain leakage (GIDL) current is generated due to the difference between the boosted voltage (0 V) and the boosted channel voltage, and electrons generated by the GIDL current are injected into the floating gate of the memory cell closest to the source selection transistor .

As a result, the program inhibited memory cell closest to the source select transistor may be programmed first, subject to the greatest amount of interference during programming of other memory cells, and further affected by the GIDL current generated from the source select transistor, resulting in a programmed problem .

A problem to be solved by the present invention is to provide a programming method of a nonvolatile memory device capable of minimizing a program disturb phenomenon.

According to an aspect of the present invention, there is provided a method of programming a nonvolatile memory device including a first selection transistor, a plurality of memory cells, and a second selection transistor, The method further comprising: applying a program voltage to the gates of the remaining memory cells except the memory cell closest to the first select transistor; And applying a program voltage to a gate of a memory cell closest to the first select transistor.

According to the program method of the nonvolatile memory device of the present invention, the program disturb phenomenon can be minimized.

1 is a circuit diagram showing a nonvolatile memory device according to an embodiment of the present invention.
Figure 2 is a cross-sectional view of the non-selected string of Figure 1;
3 is a flowchart illustrating a method of programming a nonvolatile memory device according to an embodiment of the present invention.

Hereinafter, the most preferred embodiment of the present invention will be described. In the drawings, the thickness and the spacing are expressed for convenience of explanation, and can be exaggerated relative to the actual physical thickness. In describing the present invention, known configurations irrespective of the gist of the present invention may be omitted. It should be noted that, in the case of adding the reference numerals to the constituent elements of the drawings, the same constituent elements have the same number as much as possible even if they are displayed on different drawings.

FIG. 1 is a circuit diagram illustrating a nonvolatile memory device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the non-selected string of FIG.

Referring to FIGS. 1 and 2, a cell array of a nonvolatile memory device according to an embodiment of the present invention includes a plurality of strings ST1 and ST2, a plurality of strings ST1 and ST2 And a common source line CSL connected in common to the other ends of the bit strings BL1 and BL2 and the plurality of strings ST1 and ST2. In the present embodiment, two strings ST1 and ST2 and two bit lines BL1 and BL2 are shown. However, the present invention is not limited thereto, and the number of the strings and the bit lines May be varied in various ways.

Each of the strings ST1 and ST2 includes a source selection transistor SST connected in series, a plurality of memory cells MC0 through MC63, and a drain selection transistor DST.

Here, each of the plurality of memory cells MC0 to MC63 includes a laminated structure of a floating gate FG and a control gate CG. The memory cells MC whose control gates CG are connected to each other and share one word line WL are controlled by the word line WL and constitute one page. In this embodiment, there are 64 pages to 64 word lines (WL0 to WL63), but the present invention is not limited thereto, and the number of word lines may be variously modified.

In addition, the gates of the drain select transistors DST are connected to each other to share one drain select line DSL, and the gates of the source select transistors SST are connected to each other to share one source select line SSL.

The bit lines BL1 and BL2 may be respectively connected to the drains of the drain selection transistors DST included in the strings ST1 and ST2, respectively. In this embodiment, a string including a program target memory cell (hereinafter referred to as a selected string) and bit lines (hereinafter, selected bit lines) connected to the selected string are ST2 and BL2, respectively, and are connected to a non- And non-selected bit lines are assumed to be ST1 and BL1, respectively.

The common source line CSL may be connected in common with the source of the source select transistor SST included in each of the strings ST1 and ST2.

Hereinafter, a programming method of the above-described nonvolatile memory device will be described with reference to FIGS. 1 and 2 and FIG. 3 below.

3 is a flowchart illustrating a method of programming a nonvolatile memory device according to an embodiment of the present invention.

First, an erase operation is performed to erase data from all the memory cells MC0 to MC63 included in the cell array (S30). The erase operation can be performed by applying a high positive voltage to the substrate bulk (refer to reference numeral 10 in FIG. 2) to inject holes into the floating gate FG of the memory cell MC in an F-N tunneling manner.

Subsequently, a predetermined voltage necessary for programming is applied to the source select line SSL, the drain select line DSL and the bit lines BL1 and BL2 before the program voltage is applied (S31). Specifically, a ground voltage (0 V) is applied to the source selection line SSL corresponding to the gate of the source selection transistor SST and a power supply voltage of, for example, 3 V to 5 V A ground voltage 0V is applied to the selected bit line BL2 and a power supply voltage VCC is applied to a drain select line DSL corresponding to the gate of the drain select transistor DST.

In this case, the source selection transistor SST is turned off, and the ground path is cut off. The source of the drain selection transistor DST of the non-selected string ST1 is charged to VCC-Vth (where VCC is the power supply voltage described above and Vth is the threshold voltage of the drain selection transistor DST) The drain selection transistor DST of the string ST1 is substantially cut off.

Next, a program operation is performed to apply the program voltage to the selected word line WL connected to the memory cell to be programmed and apply the pass voltage to the remaining word line WL, and the word line WL closest to the source selection transistor SST The program voltage is sequentially applied to the remaining word lines WL1 to WL63 from the word line WL1 close to the source select transistor SST to the source select transistor SST and the word line WL63 farthest to the word line WL63, (S32).

That is, a program voltage of about 18 to 20 V, for example, is first applied to the word line WL1 and a pass voltage of about 10 V is applied to the remaining word lines WL0 and WL2 to WL63, for example. Next, a program voltage is applied to the word line WL2 and a pass voltage is applied to the remaining word lines WL0, WL1, WL3 to WL63. Next, a program voltage is applied to the word line WL3, and a pass voltage is applied to the remaining word lines WL0 to WL2 and WL4 to WL63. This process is repeated until the program voltage is applied to the word line WL63.

When the program voltage is applied to one of the word lines WL1 to WL63 as described above, the channel voltage of the memory cells MC0 to MC63 of the selected string ST2 is set to the ground voltage 0V applied to the selected bit line BL2. Electrons are injected into the floating gate FG of the memory cell MC connected to the word line WL to which the program voltage is applied, so that the program can be performed. On the other hand, the source selection transistor SST and the drain selection transistor DST of the non-selected string ST1 are substantially cut off as described in step S31 so that the channel of the memory cells MC0 to MC63 is in a floating state The channel voltage of the memory cells MC0 to MC63 is boosted when a program voltage is applied to one of the word lines WL1 to WL63. At this time, the memory cell MC1 of the non-selected string ST1 connected to the word line WL1 to which the program voltage is first applied is spaced apart from the source select transistor SST by the presence of the memory cell MC0 Therefore, a program by the generation of the GIDL current from the source selection transistor SST can be prevented. This is more so from the word line WL2 to the word line WL63.

In step S32, a program voltage is applied to the word line WL0 to which the program voltage is not applied and a pass voltage is applied to the remaining word lines WL1 to WL63 in step S33.

When the program voltage is applied to the word line WL0, the channel voltage of the memory cell MC0 of the non-selected string ST1 is boosted to prevent the program. At this time, since the program voltage is applied last to the word line WL0, the memory cell MC0 of the non-selected string ST1 can be prevented from being programmed by the interference of the remaining memory cells MC2 to MC63.

The contents of the present embodiment described above can be summarized as follows.

The memory cell MC0 closest to the source select transistor SST in the non-selected string ST1 is most likely to be programmed due to the GIDL current of the source select transistor SST. If this memory cell MC0 is first programmed, it is more likely to be programmed because it receives the most interference in the subsequent program operation. Therefore, in the present embodiment, it is proposed to program the memory cell MC0 closest to the source selection transistor SST to lower the programmability last.

However, the present invention is not limited to the above-described embodiments. For example, assuming that programming is performed in the order from the memory cell MC63 closest to the drain select transistor DST to the memory cell MC0 farthest from the drain select transistor DST, The near memory cell MC63 may likewise be highly likely to be programmed due to the GIDL current of the drain select transistor DST and interference in subsequent program operation. In this case, by programming the memory cell MC63 closest to the drain select transistor DST at the end, it is possible to lower the program possibility due to interference, thereby reducing the possibility of program disturb as a whole.

It is to be noted that the technical spirit of the present invention has been specifically described in accordance with the above-described preferred embodiments, but it is to be understood that the above-described embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

CSL: common source line SST: source select transistor
DST: drain select transistor MC: memory cell
BL: bit line

Claims (4)

A programming method of a non-volatile memory device including a string in which a first selection transistor, a plurality of memory cells and a second selection transistor are connected in series,
Applying a program voltage to the gates of the remaining memory cells except the memory cell closest to the first select transistor; And
Applying a program voltage to a gate of a memory cell closest to the first select transistor
Program method of nonvolatile memory device
The method according to claim 1,
Wherein applying a program voltage to a gate of the remaining memory cell comprises:
The program voltage is applied to the gate of the memory cell in the order of the memory cells far from the memory cell closer to the first selection transistor
A method of programming a nonvolatile memory device.
3. The method according to claim 1 or 2,
The first select transistor is a source select transistor whose one end is connected to a source line,
The second selection transistor is a drain selection transistor whose one end is connected to the bit line
A method of programming a nonvolatile memory device.
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