KR101810644B1 - Method of manufacturing an epitaxial wafer - Google Patents

Method of manufacturing an epitaxial wafer Download PDF

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KR101810644B1
KR101810644B1 KR1020160003464A KR20160003464A KR101810644B1 KR 101810644 B1 KR101810644 B1 KR 101810644B1 KR 1020160003464 A KR1020160003464 A KR 1020160003464A KR 20160003464 A KR20160003464 A KR 20160003464A KR 101810644 B1 KR101810644 B1 KR 101810644B1
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chamber
gas
flow rate
inert gas
hydrogen gas
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KR1020160003464A
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KR20170084429A (en
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장규일
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에스케이실트론 주식회사
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Priority to KR1020160003464A priority Critical patent/KR101810644B1/en
Priority to PCT/KR2017/000090 priority patent/WO2017122963A2/en
Priority to TW106100888A priority patent/TWI626730B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046—Dry cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/08—Preparation of the foundation plate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2015—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate the substrate being of crystalline semiconductor material, e.g. lattice adaptation, heteroepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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Abstract

An embodiment is directed to an epitaxial wafer fabrication method using an epitaxial reactor including a chamber having a gas inlet and a gas outlet, comprising a cleaning step of removing contaminants in the chamber, a step of stopping power supply to the epitaxial reactor And a dummy run step of depositing an epitaxial layer on at least one of the dummy wafers, wherein the rinsing step comprises: a baking step of maintaining the temperature inside the chamber at 1150 ° C to 1200 ° C; An etching step of supplying etching gas into the chamber and discharging the etching gas into the chamber; And a final discharge step of supplying a hydrogen gas or an inert gas into the chamber while discharging the gas to the gas outlet while maintaining the temperature of the chamber at 700 ° C to 800 ° C.

Description

≪ Desc / Clms Page number 1 > METHOD OF MANUFACTURING AN EPITAXIAL WAFER &

An embodiment relates to a method of manufacturing an epitaxial wafer.

A silicon wafer widely used as a material for manufacturing semiconductor devices refers to a crystalline silicon thin plate made of polycrystalline silicon as a raw material.

Silicon wafers are divided into polished wafers, epitaxial wafers, silicon on insulator wafers, diffused wafers, and hydrogen annealed wafers depending on the processing method. .

An epitaxial wafer is a wafer on which another monocrystalline layer is grown on the surface of a conventional silicon wafer. The epitaxial wafer has fewer surface defects than conventional silicon wafers and has the property of controlling the concentration and type of impurities.

The embodiment provides a method of manufacturing an epitaxial wafer capable of suppressing the occurrence of defects.

An embodiment relates to a method of manufacturing an epitaxial wafer using an epitaxial reactor including a chamber having a gas inlet and a gas outlet, the method comprising: a cleaning step of removing contaminants in the chamber; A deactivation step of stopping power supply to the epitaxial reactor; And a dummy run step of depositing an epitaxial layer on at least one dummy wafer, the rinsing step comprising: a bake step of maintaining the temperature inside the chamber at 1150 ° C to 1200 ° C; An etching step of supplying etching gas into the chamber and discharging the etching gas into the chamber; And a final discharge step of supplying an inert gas or hydrogen gas into the chamber while discharging the gas to the gas outlet while maintaining the temperature of the chamber at 700 to 800 ° C.

The internal temperature of the chamber in the etching step may be maintained at an internal temperature of the chamber in the baking step.

In each of the baking step and the etching step, inert gas or hydrogen gas may be supplied into the chamber and discharged to the gas outlet.

The discharge flow rate of the inert gas or the hydrogen gas may be highest in the final discharge step among the bake step, the etching step and the final discharge step.

The ratio of the flow rate of the inert gas or the hydrogen gas in the etching step to the flow rate of the inert gas or the hydrogen gas in the baking step is 1: 7 to 1: 8, the flow rate of the inert gas or hydrogen gas in the baking step, The ratio of the flow rate of the inert gas or the hydrogen gas in the final discharge step may be 1: 1.5 to 1: 2.

The execution time of the final discharge step may be longer than the execution time of the baking step and the execution time of the etching step.

Wherein in the deactivation step, an inactive gas is supplied into the chamber and discharged through the gas outlet, and the flow rate of the inactive gas in the inactivation step is lower than the flow rate of the inert gas or hydrogen gas in the bake step and the final discharge step Can be low

The dummy run step includes an activation step of depositing an epitaxial layer on the dummy wafer according to a predetermined recipe; Determining whether the number of times the dummy run is performed is the same as the predetermined number of times; And increasing the number of dummy runs by one if the number of times the dummy run is not equal to the predetermined number, and depositing an epitaxial layer on the new dummy wafer.

Wherein the cleaning step comprises: an initial discharge step of maintaining an internal temperature of the interior of the chamber at 700 캜 to 800 캜 before the bake step, supplying an inert gas or hydrogen gas into the chamber and discharging the gas into the chamber; And a temperature raising step of gradually increasing the internal temperature of the chamber to the internal temperature of the chamber in the baking step.

In the cleaning step, the wafer in the chamber can be rotated at a constant speed.

The embodiment can suppress the occurrence of bonding of the epitaxial wafer.

1 shows a flowchart of an epitaxial manufacturing method according to an embodiment.
Figure 2 shows an epitaxial reactor for producing epitaxial wafers according to an embodiment.
3 is a flow chart showing one embodiment of the cleaning step shown in Fig.
4 is a flow chart showing another embodiment of the cleaning step shown in Fig.
5A is a graph showing the moisture state in the chamber of the epitaxial reactor.
5B shows the pulsation of the discharge flow rate at the gas discharge port and the gas discharge line.
6A shows the degree of defects of the wafer before and after the deactivation step performed according to the embodiment.
FIG. 6B shows the number, average, and standard deviation of the LLS shown in FIG. 6A.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. In the description of the embodiments, it is to be understood that each layer (film), region, pattern or structure may be referred to as being "on" or "under" a substrate, each layer It is to be understood that the terms " on "and " under" include both " directly "or" indirectly " do. In addition, the criteria for the top / bottom or bottom / bottom of each layer are described with reference to the drawings. The same reference numerals denote the same elements throughout the description of the drawings.

FIG. 1 shows a flow chart of an epitaxial manufacturing method according to an embodiment, and FIG. 2 shows an epitaxial reactor 100 for manufacturing an epitaxial wafer according to an embodiment.

1 and 2, the epitaxial reactor 100 is a single wafer processing apparatus for processing wafers one at a time, and includes a chamber 105, a gas supply line 110, a gas discharge line 115, a susceptor 120, A lower ring 125, an upper ring 127, a preheating ring 129, and a susceptor support 130.

The chamber 105 is a space in which the epitaxial reaction takes place and can be made of quartz glass. The chamber 105 may have a gas inlet 108 connected to the gas supply line 110 at one side and a gas outlet 109 connected to the gas discharge line 115 at the other side, And may include a lower dome 103 and an upper dome 104. The source gas supplied from the gas supply line 110 is introduced into the chamber 105 through the gas inlet 108 and the source gas introduced into the chamber 105 is supplied to the wafer 101 For example, a silicon wafer), and then discharged to the gas discharge line 115 through the gas discharge port 109. [

Although only one gas supply line 110, a gas discharge line 115, a gas inlet 108, and a gas discharge port 109 are shown in FIG. 1, each of the gas supply lines 110, the gas discharge line 108, and the gas discharge port 109 may be one or more.

The lower ring 125 is disposed in the chamber 105 to surround the susceptor 120 and the upper ring 127 is disposed in the chamber 105 on the lower ring 125 to face the lower ring 125 . The material of the lower ring 125 and the upper ring 127 may be quartz (SiO 2 ) or silicon carbide (SiC). The preheating ring 129 is formed along the inner surface of the lower ring 125 adjacent to the susceptor 120 and is disposed adjacent to the susceptor 120 to surround the susceptor 120 to make the heat uniform.

The susceptor 120 is a portion where the wafer 101 is mounted during the epitaxial reaction. The susceptor 120 may be formed by coating silicon carbide on carbon graphite, silicon carbide, or carbon graphite. The susceptor 120 is disposed inside the chamber 105 and can seat the wafer 101 on its upper surface.

First, a run waiting step is performed (S110).

A run waiting process is performed to stabilize the inside of the chamber 105 before the step of growing the epitaxial layer on the wafer 101 after the wafer 101 is loaded on the susceptor 120 do.

In the run waiting process, the wafer loaded on the susceptor 120 is rotated at a constant speed, and the internal temperature of the chamber 105 is maintained at 700 ° C. to 780 ° C. (eg, 760 ° C.) An inert gas supplied from the inert gas supply source 108 or a hydrogen gas (H 2 Gas is introduced into the chamber 105 through the gas inlet 108 and discharged to the gas discharge line 115 through the gas outlet 109. [

At this time, an inert gas or hydrogen gas (H 2 Gas) can be between 45 slm and 55 slm. For example, hydrogen gas (H 2 Gas) flow rate may be 50 slm. Slm may be abbreviated as Standard Litters per Minute.

Next, a cleaning step is performed (S120).

In the cleaning step S120, the internal contaminants in the chamber 105 are discharged through the gas outlet 109 and the gas outlet line 115 to the outside of the chamber 105.

FIG. 3 is a flow chart illustrating one embodiment of the cleaning step (S120) shown in FIG.

Referring to FIG. 3, the cleaning step S120 may include a bake step 210, an etching step S220, and a final discharge step S230.

In the baking step S210, the wafer loaded on the susceptor 120 is kept rotated at a constant speed, and the temperature inside the chamber 105 is maintained at 1150 ° C to 1200 ° C.

In the bake step S210, an inert gas or a hydrogen gas (H 2 Gas) is injected into the chamber 105 and discharged to the gas outlet, and the discharge flow rate may be lower than the run-waiting process, but is not limited thereto.

For example, in the baking step S210, the temperature inside the chamber 105 may be 1180 ° C to 1190 ° C. Further, for example, in the bake step S210, the temperature inside the chamber 105 may be 1185 캜.

Since the temperature inside the chamber 105 in the baking step S210 is high, contaminants such as powders or particles adhering to or adsorbed to the inner surface of the chamber 105 or the wafer surface, Or lift up from the inner surface of the chamber 105 or the wafer surface.

That is, the contaminants attached to the inner surface of the chamber 105 or the wafer surface in the baking step S210 may be separated or lifted up to be easily discharged out of the chamber 105.

In the bake step S210, hydrogen gas (H 2 Gas) flow rate may be the same as the run standby process. The execution time of the bake step S210 may be longer than the execution time of the run standby process.

Next, in the etching step S220, the wafer loaded on the susceptor 120 is rotated at a constant speed, and the etching gas is supplied into the chamber 105 to separate the contaminants from the inner surface of the chamber 105 or the wafer surface Remove.

Further, in the etching step (S220), the pollutants separated in the baking step can be further separated or lifted up.

In the etching step S220, an etching gas such as HCL gas is supplied into the chamber 105 through the gas inlet 108 while maintaining the temperature inside the chamber 105 in the baking step S210, And discharged to the gas outlet 109. At this time, the flow rate of the etching gas introduced into the chamber 105 and discharged to the gas outlet 109 may be 20 slm to 30 slm. The discharge flow rate of the etching gas may be 25 slm.

In the etching step S220, the inert gas or the hydrogen gas is injected and discharged to the gas outlet 109, but the discharge flow rate of the inert gas or the hydrogen gas may be lower than the baking step S210.

For example, the ratio of the flow rate of the inert gas or hydrogen gas in the etching step S220 to the flow rate of the inert gas or hydrogen gas in the baking step S210 may be 1: 7 to 1: 8.

The execution time of the etching step S220 may be longer than or equal to the execution time of the baking step S210. For example, the ratio of the execution time of the bake step S210 to the execution time of the etching step S220 may be 1: 1 to 1.5.

Next, a final discharge step for discharging the pollutants is performed (S230).

Such as powder or particles, separated or raised up by the bake step S210 and the etching step S220 to the gas discharge line 115 through the gas outlet 109. [

The inert gas or the hydrogen gas is injected into the chamber 105 while the wafer loaded on the susceptor 120 is rotated at a constant speed and the contaminant lifted up by the injected inert gas or hydrogen gas is supplied to the gas outlet 109. [ .

In the final discharge step (S230), the temperature inside the chamber 105 may be 700 [deg.] C to 800 [deg.] C. For example, the temperature inside the chamber 105 in the final discharge step (S230) may be 750 ° C.

The flow rate of the inert gas or hydrogen gas in the final discharge step S230 is higher than the flow rate of the inert gas or hydrogen gas in each of the baking step S210 and the etching step S220.

For example, the ratio of the flow rate of the inert gas or hydrogen gas in the baking step S210 to the flow rate of the inert gas or hydrogen gas in the final discharge step S230 may be 1: 1.5 to 1: 2.

The execution time of the final discharge step (S230) may be longer than the bake step (S20), and the execution time of the etching step.

For example, the execution time of the etching step S220 and the execution time of the final discharge step S230 may be 1: 8 to 1:10.

The wafers loaded on the susceptor 120 in each of the baking step S210, the etching step S220 and the final discharging step S230 can rotate at a constant speed (for example, 40 RPM to 45 RPM).

By performing the highest discharge flow rate and the discharge step for the longest time, contaminants in the chamber 105 can be stably discharged, thereby reducing the damage or defects of the epitaxial wafer.

4 is a flow chart showing another embodiment (S120-1) of the cleaning step shown in Fig.

The same reference numerals as those in FIG. 3 denote the same components or steps, and the description of the same components or steps will be simplified or omitted.

Referring to FIG. 4, the cleaning step S120-1 includes an initial discharging step S201, a temperature raising step S202, a bake step 210, an etching step S220, a susceptor coating step S225, , And a final discharge step (S230).

3, the cleaning step S120-1 includes an initial discharge step S201 and a temperature raising step S202 performed between the waiting for run step S110 and the baking step S210, (S226) performed between the final discharge step (S220) and the final discharge step (S230).

The initial discharge step S201 is performed immediately after the run waiting step S110.

In the initial discharge step S201, the loaded wafer is rotated at a constant speed, the internal temperature of the chamber 105 is maintained at 700 to 800 DEG C, the inert gas or hydrogen gas is supplied into the chamber 105, (109).

For example, in the initial discharge step S201, the flow rate of the inert gas or hydrogen gas may be higher than the run standby state.

For example, the flow rate of the inert gas or hydrogen gas in the initial discharge step S201 may be the same as the flow rate of the inert gas or hydrogen gas in the bake step S210. The initial discharge step S201 is a period for stabilizing the flow rate of the inert gas or the hydrogen gas to be equal to the flow rate of the bake step, and may be a stabilization period of the inert gas or the hydrogen gas flow rate.

The execution time of the initial discharge step S201 may be shorter than the execution time of the bake step S210.

The temperature raising step S202 may be performed immediately after the initial discharging step S201.

The temperature raising step S202 is a period of gradually raising the temperature of the chamber from the temperature of the chamber of the initial discharging step S201 to the temperature of the chamber of the bake step S210.

The execution time of the temperature rising step S202 may be longer than the execution time of the etching step S220 and may be shorter than the execution time of the final discharge step S230.

The flow rate of the inert gas or hydrogen gas in the temperature raising step S202 may be equal to the flow rate of the inert gas or hydrogen gas in the baking step S210

The susceptor coating step (S225) is performed immediately after the etching step (S220).

The inner temperature of the chamber 105 is lowered by a predetermined temperature (for example, 20 ° C to 40 ° C) in the chamber temperature of the etching step S220 before the susceptor 120 is coated, and the susceptor is coated The susceptor surface is TCS-coated by injecting a gas such as TCS gas and discharging it to the gas outlet 109. [ This is to prevent defects (e.g., slip) caused by the etching step S220.

Next, an Inert Idle step is performed (S130).

In the deactivation step, the run is stopped and the power supply to the epitaxial reactor 110 is stopped.

In the deactivation step, the total supply power or the total supply power of the epitaxial reactor 100 is zero, the temperature inside the chamber may be 0 ° C to 20 ° C (for example, room temperature), and an inert gas such as , Nitrogen (N 2 ) gas is injected into the chamber 105 and exhausted to the gas outlet 109.

At this time, the discharge flow rate of the inert gas (for example, nitrogen gas) in the inactive step S130 is equal to the flow rate of the inert gas or hydrogen gas in the run standby step S110, the baking step S210, and the final discharge step S230 ≪ / RTI > For example, the discharge flow rate of the nitrogen gas in the deactivation step may be 15 slm to 25 slm. For example, the discharge flow rate of the nitrogen gas may be 20 slm.

The deactivation step S130 is performed in a state in which the chamber 105 is not opened, for the purpose of maintenance of the epitaxial reactor such as scrubber cleaning, blade teaching, and inspection of the susceptor condition due to the quality of the epitaxial wafer or the like .

Next, a dummy run step is performed (S135).

In the dummy run step S135, an epitaxial layer is deposited on at least one dummy wafer.

For example, the reactants generated due to the moisture produced in the chamber 110 after the deactivation step by depositing an epitaxial layer on a predetermined number of wafers sequentially, and the reactants generated at the gas outlet 109 and the gas outlet line 115 Thereby removing contaminants in the chamber 105 due to pulsation of the discharge flow rate of the exhaust gas.

The dummy run step S135 may include the following steps S140, S150, S160.

First, an activation step for dummy run is performed (S140).

Depositing an epitaxial layer on a dummy wafer loaded on the susceptor 120 according to a predetermined recipe.

A selective epitaxial growth process may be performed to deposit an epitaxial layer on the dummy wafer.

For example, the selective epitaxial growth process may be a chemical vapor deposition (CVD) process, a reduced pressure chemical vapor deposition (RPCVD) process, a high vacuum chemical vapor deposition (UHVCVD) process, But it is not limited thereto.

For example, the selective epitaxial growth can be performed by supplying a source gas such as SiH4, dichlorosilane (SiH2Cl2; DCS), trichlorosilane (SiH2Cl3; TCS) or the like into the chamber at a temperature of 1000 ° C to 1200 ° C.

Next, it is determined whether the number of dummy wafers having the epitaxial layer deposited, that is, the number of dummy runs, is equal to a predetermined number (N, e.g., N = 5) (S150). Wherein the number of dummy runs may be equal to the number of dummy wafers on which the epitaxial layer is deposited.

If the number of dummy runs is equal to the preset number of times, a production progress step of producing an epitaxial wafer according to a predetermined recipe is performed (S170).

On the other hand, if the number of dummy runs performed is not equal to the preset number of times, the number of dummy runs is increased by one, the epitaxial layer is deposited on the new dummy wafer, and steps S140 to S150 are repeated.

The dummy run step S135 serves to remove the contamination source remaining in the chamber 105. [

In the deactivation step S130, moisture can be generated by a low chamber temperature (for example, room temperature), and oxygen (O 2 ) provided in the generated moisture and the residual gas in the chamber 105 (for example, Si x Cl y H z may react to form a reactant, which can be a source of contamination to the epitaxial wafer.

5A is a graph showing the moisture state in the chamber of the epitaxial reactor 100. Fig.

Referring to FIG. 5A, the amount of water (H2O) in the chamber 105 of the epitaxial reactor 100 gradually increases after the point in time at which the deactivation step starts (501).

The gas discharge port 109 and the gas discharge line 115 of the epitaxial reactor 100 are controlled by the flow rate difference of the gas discharged to the gas discharge port 109 between the inactivation step S130 and the activation step S140 The pulsation occurs.

Fig. 5B shows the pulsation of the discharge flow rate at the gas outlet 109 and the gas discharge line 115. Fig. Referring to FIG. 5B, pulsation of the discharge flow rate may occur immediately after the deactivation step (S130). Due to the pulsation of the discharge flow rate, the powder or particles generated in the deactivation step S130 may be supplied into the chamber 105 to contaminate the chamber, which may cause defects in the epitaxial wafer.

The contamination source in the chamber 105 is removed through the cleaning step S120 performed before the deactivation step and the reactant generated in the deactivation step S130 through the dummy run step S135 and the discharge flow rate By removing the contaminants introduced into the chamber 105 by pulsation, it is possible to suppress the occurrence of defects in the epitaxial wafer.

FIG. 6A shows the degree of defects of the wafer before and after the deactivation step performed according to the embodiment, and FIG. 6B shows the number (N), the average (Avg) and the standard deviation (StDev) of the LLS shown in FIG. 6A.

FIG. 6A shows LLS (Localized Light Scatter) having a size of 200 nm, case 1 shows the measured LLS before the deactivation step, and case 2 shows the measured LLS after the deactivation step. N is the total number of defects, Avg represents the average of LLS per wafer, and StDev represents the standard deviation of LLS.

6A and 6B, the average of the case 2 is smaller than the average of the case 1, and there is no rise of the LLS after the deactivation step. Therefore, the epitaxial wafer produced according to the epitaxial manufacturing method according to the embodiment has defects Can be improved.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment of the present invention and are not necessarily limited to one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments can be combined and modified by other persons having ordinary skill in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

105: chamber 110: gas supply line
115: gas discharge line 120: susceptor
125: lower ring 127: upper ring
129: Preheating ring.

Claims (10)

A method of manufacturing an epitaxial wafer using an epitaxial reactor including a chamber having a gas inlet and a gas outlet,
A cleaning step of removing contaminants in the chamber;
A deactivation step of stopping power supply to the epitaxial reactor; And
A dummy run step of depositing an epitaxial layer on at least one dummy wafer,
The cleaning step may include:
A bake step of supplying an inert gas or hydrogen gas into the chamber through the gas inlet while discharging the inert gas or hydrogen gas into the chamber while maintaining the temperature inside the chamber at 1150 ° C to 1200 ° C;
An etching step of supplying an etching gas into the chamber and introducing an inert gas or hydrogen gas into the chamber through the gas inlet and discharging the inert gas or hydrogen gas into the chamber; And
And a final discharging step of supplying hydrogen gas or an inert gas into the chamber through the gas inlet while discharging the gas into the chamber while maintaining the temperature of the chamber at 700 ° C to 800 ° C,
The discharge flow rate of the hydrogen gas or the inert gas is the highest among the bake step, the etching step and the final discharge step,
Wherein the execution time of the final discharge step is longer than the execution time of the bake step and the execution time of the etching step. The method according to claim 1,
Wherein the internal temperature of the chamber in the etching step is maintained at an internal temperature of the chamber in the baking step. delete The method according to claim 1,
Wherein the ratio of the flow rate of the inert gas or the hydrogen gas in the etching step to the flow rate of the inert gas or hydrogen gas in the baking step is 1: 7 to 1: 8. The method according to claim 1,
Wherein the ratio of the flow rate of the inert gas or hydrogen gas in the baking step to the flow rate of the inert gas or hydrogen gas in the final discharge step is 1: 1.5 to 1: 2. delete The method according to claim 1,
Wherein in the deactivation step, an inactive gas is supplied into the chamber through the gas inlet and discharged through the gas outlet, and the flow rate of the deactivating gas in the deactivation step is controlled by the inert gas in the bake step and the final discharge step Wherein the flow rate of the hydrogen gas is lower than the flow rate of the hydrogen gas. The method of claim 1, wherein the dummy run comprises:
An activation step of depositing an epitaxial layer on the dummy wafer according to a predetermined recipe;
Determining whether the number of times the dummy run is performed is the same as the predetermined number of times; And
Increasing the number of dummy runs by one if the number of times the dummy run is not the same as the predetermined number, and depositing an epitaxial layer on a new dummy wafer. The method according to claim 1,
An initial discharging step of maintaining an internal temperature of the inside of the chamber at 700 캜 to 800 캜 before the baking step and supplying an inert gas or hydrogen gas into the chamber and discharging the gas into the chamber; And
Further comprising a temperature raising step of gradually increasing an internal temperature of the chamber to an internal temperature of the chamber in the baking step. The method according to any one of claims 1, 2, 4, 5, and 7 to 9,
And the wafer in the chamber is rotated at a constant speed in the cleaning step.
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