CN112201568A - Method and equipment for epitaxial growth of silicon wafer - Google Patents

Method and equipment for epitaxial growth of silicon wafer Download PDF

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Publication number
CN112201568A
CN112201568A CN202011173810.9A CN202011173810A CN112201568A CN 112201568 A CN112201568 A CN 112201568A CN 202011173810 A CN202011173810 A CN 202011173810A CN 112201568 A CN112201568 A CN 112201568A
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silicon wafer
reaction chamber
susceptor
gas
gas inlet
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王力
金柱炫
俎世琦
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Xian Eswin Silicon Wafer Technology Co Ltd
Xian Eswin Material Technology Co Ltd
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Xian Eswin Silicon Wafer Technology Co Ltd
Xian Eswin Material Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02658Pretreatments
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • H01L21/67069Apparatus for fluid treatment for etching for drying etching

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The embodiment of the invention discloses a method and equipment for epitaxial growth of a silicon wafer, wherein the method comprises the following steps: a first step of placing the silicon wafer on a disk-shaped susceptor inside a reaction chamber; a second step of delivering an etching gas into the reaction chamber via a gas inlet to etch the silicon wafer, wherein the gas inlet is located radially outside the susceptor and the susceptor is at a first height level with the gas inlet; a third step of delivering a silicon source gas into the reaction chamber via the gas inlet to grow an epitaxial layer on the surface of the silicon wafer.

Description

Method and equipment for epitaxial growth of silicon wafer
Technical Field
The invention relates to a silicon wafer epitaxial growth technology in the field of semiconductors, in particular to a method and equipment for epitaxial growth of a silicon wafer.
Background
The epitaxial growth process of silicon wafer is an important process in the manufacturing process of semiconductor chip, and the process is that under a certain condition, a layer of monocrystalline silicon film with the same crystal orientation, namely an epitaxial layer, is grown on the polished silicon wafer, so as to obtain the epitaxial silicon wafer. Epitaxial silicon wafers are widely used for the production and manufacture of high-performance semiconductor devices due to good crystal structures, lower defect densities and excellent conductivity. The epitaxial growth of silicon wafers mainly comprises growth methods such as vacuum epitaxial deposition, vapor phase epitaxial deposition, liquid phase epitaxial deposition and the like, wherein the vapor phase epitaxial deposition is most widely applied. The term epitaxial growth as used herein refers to epitaxial growth by means of chemical vapor deposition, unless otherwise specified.
In a conventional epitaxial growth process, a silicon source gas capable of epitaxially growing a silicon wafer usually contacts a radial edge region of the silicon wafer first or earliest, so that the thickness of an epitaxial layer grown on the radial edge region is large, and the thickness uniformity of the epitaxial layer is affected, thereby affecting the surface flatness of the finally obtained epitaxial silicon wafer.
With the continuous development of semiconductor process, the requirements on the thickness uniformity of the epitaxial layer of the epitaxial silicon wafer and the surface flatness of the epitaxial silicon wafer are higher and higher, and the epitaxial silicon wafer obtained by the conventional epitaxial growth method cannot meet the higher requirements.
Disclosure of Invention
In order to solve the above technical problems, embodiments of the present invention are directed to providing a method and an apparatus for epitaxial growth of a silicon wafer, which can improve the flatness of an epitaxial silicon wafer with an epitaxial layer obtained after the silicon wafer is subjected to epitaxial growth.
The technical scheme of the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a method for epitaxial growth of a silicon wafer, where the method includes:
a first step of placing the silicon wafer on a disk-shaped susceptor inside a reaction chamber;
a second step of delivering an etching gas into the reaction chamber via a gas inlet to etch the silicon wafer, wherein the gas inlet is located radially outside the susceptor and the susceptor is at a first height level with the gas inlet;
a third step of delivering a silicon source gas into the reaction chamber via the gas inlet to grow an epitaxial layer on the surface of the silicon wafer.
In a second aspect, an embodiment of the present invention provides an apparatus for epitaxial growth of a silicon wafer, where the apparatus includes:
an epitaxial reaction apparatus, comprising: a bell jar enclosing the reaction chamber; a disk-shaped susceptor inside the reaction chamber, the susceptor configured to carry the silicon wafer; a gas inlet configured to deliver a reactant gas into the reaction chamber, wherein the gas inlet is located radially outward of the susceptor and the susceptor is at a first height level with the gas inlet;
an etching gas supply configured to deliver an etching gas into the reaction chamber via the gas inlet to etch the silicon wafer;
a silicon source gas supply configured to deliver a silicon source gas into the reaction chamber via the gas inlet to grow an epitaxial layer on the surface of the silicon wafer after the etching gas supply delivers an etching gas into the reaction chamber.
The embodiment of the invention provides a method and equipment for epitaxial growth of a silicon wafer.
Drawings
FIG. 1 is a schematic view of a conventional epitaxial reactor;
FIG. 2 is a schematic diagram showing the relationship between the thickness of the epitaxial layer and different positions of the silicon wafer in the diameter direction in the conventional method;
FIG. 3 is a schematic view showing the surface flatness of an epitaxial silicon wafer in a conventional method;
FIG. 4 is a schematic diagram of a method for epitaxial growth of a silicon wafer according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of etching gas flowing across the surface of a silicon wafer in a method according to an embodiment of the present invention;
FIG. 6 is a schematic view showing the relationship between the different positions in the diameter direction of the silicon wafer and the removal thickness in the case where the etching gas is supplied in the manner shown in FIG. 5;
FIG. 7 is a schematic view of a silicon source gas flowing across the surface of a silicon wafer after a pedestal is lowered in a method according to an embodiment of the present invention;
FIG. 8 is a graph comparing the thickness of the epitaxial layers before and after the susceptor is lowered;
FIG. 9 is a schematic illustration of the reproducibility effectiveness of a method provided by an embodiment of the invention;
fig. 10 is a schematic diagram of an apparatus for epitaxial growth of a silicon wafer according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
Referring to fig. 1, a schematic diagram of a conventional epitaxial reactor 110A is shown. The apparatus 110A may include:
a bell jar 111A enclosing the reaction chamber RC, wherein an upper bell jar 111A-1 and a lower bell jar 111A-2 are shown in FIG. 1;
a disk-shaped susceptor 112A inside the reaction chamber RC, the susceptor 112A being configured to carry the polished silicon wafer W;
a susceptor support 114A for supporting the susceptor 112A and driving the susceptor 112A to rotate around a central axis XA of the apparatus 110A at a speed during epitaxial growth, the wafer W rotating around the central axis XA together with the susceptor 112A as the wafer W is carried on the susceptor 112A;
a gas inlet 113A, the gas inlet 113A being configured to deliver a reaction gas, such as a silicon source gas and a carrier gas, into the reaction chamber RC, as shown by an arrow at the gas inlet 113A in fig. 1, wherein the gas inlet 113A is located radially outside the susceptor 112A and the susceptor 112A is at a level flush with the gas inlet 113A;
an exhaust port 115A for exhausting the reaction off-gas out of the reaction chamber RC, as shown by an arrow at the exhaust port 115A in fig. 1;
a plurality of heating bulbs 116A disposed at the peripheries of the upper and lower bell jars 111A-1 and 111A-2 and for providing a high temperature environment in the reaction chamber RC through the upper and lower bell jars 111A-1 and 111A-2.
In the conventional epitaxial growth process, due to the above-described positional relationship of the gas inlet 113A and the susceptor 112A, the silicon source gas supplied into the reaction chamber RC via the gas inlet 113A initially contacts the radial edge region of the polished wafer W, resulting in a large thickness of the epitaxial layer grown on the region. Specifically, referring to fig. 2, fig. 2 illustrates the thickness of the epitaxial layer at 35 points in the diameter direction of the silicon wafer in the conventional epitaxial growth method, taking an epitaxial layer grown to 3 μm on a silicon wafer having a diameter of 300mm as an example, wherein the abscissa represents the diameter of the silicon wafer and the ordinate represents the thickness of the epitaxial layer. As can be seen from fig. 2, the thickness of the epitaxial layer in the central region of the silicon wafer is kept around 3 μm, while the thickness of the epitaxial layer in the edge region, for example, at a position 148mm away from the center of the silicon wafer reaches 3.096 μm, and the thicker epitaxial layer grown in the edge region affects the flatness of the epitaxial silicon wafer. Referring also to fig. 3, fig. 3 illustrates the flatness of the surface of an epitaxial silicon wafer in a conventional epitaxial growth method by taking a silicon wafer with a diameter of 300mm as an example, through the local flatness (SFQR) values of different regions of the silicon wafer, wherein the silicon wafer is divided into 324 Site regions by local sites of 26mm × 8mm and the SFQR value of each Site region is obtained, and a larger value indicates a poorer flatness of the Site region. As can be seen from fig. 3, the larger value site regions are mainly concentrated in the edge regions of the wafer, or for the epitaxial wafer, the less planar regions are mainly concentrated in the radial edge regions of the wafer.
In order to improve the flatness of an epitaxial silicon wafer with an epitaxial layer obtained after the silicon wafer is subjected to epitaxial growth, referring to fig. 4, an embodiment of the present invention provides a method for epitaxial growth of a silicon wafer, where the method may include:
a first step S101 of placing the silicon wafer on a disk-shaped susceptor inside a reaction chamber;
a second step S102 of delivering an etching gas into the reaction chamber via a gas inlet to etch the silicon wafer, wherein the gas inlet is located radially outside the susceptor and the susceptor is at a first height level with the gas inlet;
a third step S103 of delivering a silicon source gas into the reaction chamber via the gas inlet to grow an epitaxial layer on the surface of the silicon wafer.
The above method provided by the embodiment of the present invention may be implemented by using the epitaxial growth apparatus 100A shown in fig. 1, or the reaction chamber, the susceptor, and the gas inlet involved in the method may be the reaction chamber RC, the susceptor 112A, and the gas inlet 113A in the epitaxial growth apparatus 100A shown in fig. 1. This can be achieved, for example, using an epitaxial reactor model 300mm Epi Centura from Applied Materials.
For etching the surface of the silicon wafer in the step S102, referring to fig. 5, it is shown that the etching gas flows through the surface of the silicon wafer after being delivered to the reaction chamber, as shown in fig. 5, the etching gas has a stronger etching effect on the edge portion of the silicon wafer due to the gas flow direction and the cavity structure. Referring also to fig. 6, fig. 6 also shows the removal thickness at 35 points in the diameter direction of the silicon wafer in the case where the etching gas is supplied in the manner shown in fig. 5, taking a silicon wafer having a diameter of 300mm as an example, wherein the abscissa represents the diameter of the silicon wafer and the ordinate represents the removal thickness. As can be seen from FIG. 6, the thickness of the silicon wafer etched is the greatest in the radial edge region of the silicon wafer, i.e., the region from 145mm to 148mm from the radial center of the silicon wafer and the region from-145 mm to-148 mm from the radial center of the silicon wafer, in other words, the amount of silicon wafer etched is the greatest in the radial edge region. On the other hand, as introduced in the foregoing, the thickness of the epitaxial layer grown on the radial edge of the silicon wafer is large during the epitaxial growth. Therefore, a thicker epitaxial layer grows on a thinner area of the silicon wafer, or the thicker epitaxial layer outside the radial edge of the silicon wafer is compensated by reducing the thickness of the silicon wafer at the radial edge, so that the flatness of the surface of the finally formed epitaxial wafer comprising the silicon wafer and the epitaxial layer can be improved.
Preferably, the etching gas may be Hydrogen Chloride (HCL) gas.
Preferably, the flow rate of the hydrogen chloride gas may be 0.5slm to 2slm, where slm is a flow unit meaning a volume value in cubic centimeters circulated per minute under the condition of 1 atmosphere and 25 degrees celsius, and the delivery time may be 10s to 30 s.
Preferably, the silicon source gas may be Trichlorosilane (TCS) gas, or gases such as silicon, dichlorosilane, tetrachlorosilane, and the like, and preferably, the flow rate of trichlorosilane may be 10slm to 20 slm.
In a preferred embodiment of the present invention, the method further comprises a fourth step of lowering the base between the second step and the third step to bring the base at a second height lower than the first height. For this fourth step, the aim is to improve the thickness uniformity of the epitaxial layer grown on the silicon wafer. Specifically, referring to FIG. 7, FIG. 7 illustrates the flow of the silicon source gas over the surface of the silicon wafer after the susceptor has been lowered a distance from the position shown in FIG. 5 and the silicon source gas has been delivered to the reaction chamber. As shown in fig. 7, when the susceptor is lowered a certain distance, which prevents the silicon source gas supplied into the reaction chamber from contacting the edge region of the wafer to some extent, the thickness of the epitaxial layer grown at the radial edge region of the wafer is reduced as compared to the conventional growth method. Specifically, referring to fig. 8, fig. 8 shows a comparison of epitaxial layer thicknesses before and after susceptor lowering, where the abscissa and ordinate have the same meaning as in fig. 2, and curve C8-1 is the curve shown in fig. 2 for comparison, and curve C8-2 shows the thickness of the grown epitaxial layer with the susceptor at a second height lower than the first height in the method provided by an embodiment of the present invention. As can be seen from fig. 8, by first lowering the susceptor a distance from being flush with the gas inlet and then feeding the silicon source gas into the reaction chamber, the epitaxial layer thickness at the edge of the wafer is dramatically improved, specifically, for example, at a position 148mm from the center of the wafer, the thickness of the grown epitaxial layer is lowered from 3.096 μm to 3.027 μm, or the difference between the thickness of the epitaxial layer grown in the edge region and the thickness of the epitaxial layer grown in the center region is reduced, and it can be calculated from the data shown in fig. 8 that the uniformity of the epitaxial layer thickness is optimized from 1.72% to 0.74%, thereby improving the thickness uniformity of the epitaxial layer.
The etching of the silicon wafer and the growth of the epitaxial layer on the surface of the silicon wafer are both carried out in a high-temperature environment and the silicon wafer itself needs to reach a certain temperature, so in a preferred embodiment of the invention, the method may further include a fifth step of performing a preheating treatment on the silicon wafer between the first step and the second step. Preferably, the silicon wafer may be subjected to a preheating treatment in a hydrogen atmosphere, and preferably, the temperature increase rate of the silicon wafer may be maintained at 6.5 to 8.5 ℃/s in order to satisfy a certain production efficiency while ensuring that the silicon wafer does not suffer from deformation of the silicon wafer due to rapid temperature increase and preventing generation of crystal defects such as slip lines, and preferably, the temperature of the silicon wafer may be increased to 1050 ℃ to 1150 ℃.
Since natural oxides and organic substances exist on the polished surface of the silicon wafer, which affect the growth of the subsequent epitaxial layer or degrade the quality of the grown epitaxial layer, in a preferred embodiment of the present invention, the method may further include a sixth step of baking the silicon wafer in a hydrogen atmosphere between the fifth step and the second step. In one example, hydrogen gas may be input into the reaction chamber through the gas inlet so as to react with natural oxides and organic matters on the surface of the silicon wafer in a high-temperature environment, so as to remove the impurities on the surface of the silicon wafer and avoid affecting the subsequent epitaxial growth process. Preferably, the temperature for baking the silicon wafer can be 950 ℃ -1250 ℃, and the time for baking the silicon wafer can be 10s-30 s.
In a preferred embodiment of the present invention, the method may further include a seventh step of purging the reaction chamber with hydrogen gas via the gas inlet to purge the etching gas in the reaction chamber between the second step and the third step.
For the distance between the first height and the second height of the susceptor, or the distance that the susceptor needs to be lowered, if the lowering distance of the susceptor is too large, the silicon source gas conveyed into the reaction chamber is not easy to contact with the surface of the silicon wafer, the epitaxial growth rate of the silicon wafer is reduced, and the waste of the silicon source gas is caused. Therefore, in a preferred embodiment of the present invention, the distance between the first height and the second height is 0.5mm to 2mm, or the susceptor is lowered by 0.5mm to 2mm compared to the silicon wafer etching to perform the epitaxial growth of the silicon wafer, and such a lowering distance can ensure both the epitaxial growth rate of the silicon wafer and the thickness uniformity of the grown epitaxial layer.
In one example, the method for epitaxial growth of a silicon wafer according to the embodiment of the present invention may be performed according to various parameters shown in table 1 shown below.
Step (I) Step two Step three Step four Step five Step (ii)
Name (R) Silicon wafer loading Temperature rise H2 baking HCL surface etch Purging Thin film deposition
H2 flow (slm) 50 50 50 50 50 50
HCL flow (slm) 0 0 0 1 0 0
TCS flow (slm) 0 0 0 0 0 15
Reaction Chamber temperature (. degree. C.) 750 7.5℃/s 1130 1130 1130 1130
Height of base (mm) 0 0 0 0 -1 -1
TABLE 1
To verify the reproducibility effectiveness or reproducibility of the method provided by the embodiment of the present invention, refer to the graph shown in fig. 9, wherein the abscissa represents the number of silicon wafers continuously produced, the ordinate represents the difference of the local flatness maximum SFQRmax, i.e., Delta SFQR, the curve C9-1 represents the curve corresponding to the conventional method, and the curve C9-2 represents the curve corresponding to the method provided by the embodiment of the present invention. As can be seen from fig. 9, with the continuous production of the silicon wafer, in the case of using the conventional method, the Delta SFQR is continuously increased, and the local flatness is deteriorated, and in the case of using the method provided by the embodiment of the present invention, the Delta SFQR value is always stabilized at about 0, which indicates that the method provided by the embodiment of the present invention is effective and has good repeatability.
Referring to fig. 10, an embodiment of the present invention further provides an apparatus 100 for epitaxial growth of a silicon wafer W, where the apparatus 100 may include:
as shown in fig. 10, the epitaxial reactor 110 is outlined by a dashed square, and the epitaxial reactor 110 includes: a bell jar 111 enclosing the reaction chamber RC, wherein an upper bell jar 111-1 and a lower bell jar 111-2 are shown in fig. 10; a disk-shaped susceptor 112 inside the reaction chamber RC, the susceptor 112 being configured to carry the silicon wafer W; a gas inlet 113, the gas inlet 113 being configured to deliver a reaction gas into the reaction chamber RC, as shown by an arrow at the gas inlet 113 in fig. 10, wherein the gas inlet 113 is located radially outside the susceptor 112 and the susceptor 112 is at a first height level with the gas inlet 113;
an etching gas supply device 120 configured to supply an etching gas into the reaction chamber RC via the gas inlet 113 to etch the silicon wafer W;
a silicon source gas supply assembly 130, the silicon source gas supply assembly 130 being configured to deliver a silicon source gas into the reaction chamber RC via the gas inlet 113 to grow an epitaxial layer on the surface of the silicon wafer W after the etching gas is delivered into the reaction chamber RC by the etching gas supply assembly 120.
As shown in fig. 10, the above-described epitaxial reaction apparatus 110 may further include, as in the conventional epitaxial reaction apparatus 110A shown in fig. 1:
a susceptor support 114, the susceptor support 114 being configured to support the susceptor 112 and to drive the susceptor 112 to rotate around a central axis X of the apparatus 110 at a certain speed during the epitaxial growth, the wafer W being rotated around the central axis X together with the susceptor 10 as the wafer W is carried on the susceptor 112;
an exhaust port 115 for exhausting the reaction off-gas out of the reaction chamber RC, as shown by an arrow at the exhaust port 115 in fig. 10;
a plurality of heating bulbs 116 disposed at the peripheries of the upper and lower bells 111-1 and 111-2 and for providing a high temperature environment in the reaction chamber RC through the upper and lower bells 111-1 and 111-2.
In a preferred embodiment of the present invention, referring to fig. 10, the epitaxial reactor 110 may further comprise a drive mechanism 117, the drive mechanism 117 being configured to lower the susceptor 112 (as shown by the downward arrow at the susceptor 112 in fig. 10) to bring the susceptor 112 at a second height lower than the first height to make the thickness of the epitaxial layer grown on the wafer W more uniform, as described in detail above.
As shown in fig. 10, a drive mechanism 117 may be provided on the base support 114 to lower the base 112 carried by the base support 114 by lowering the base support 114. In this case, in particular, although not shown in the drawings, it is understood that the drive mechanism 117 may comprise, for example, a motor, a lead screw fixedly connected to the base support frame 114, and a lead screw nut cooperating with the lead screw, configured to remain fixed in the vertical direction, with the motor causing a relative rotational movement between the lead screw and the lead screw nut, which may be converted into a movement of the lead screw in the downward direction, thereby effecting the lowering of the base 112.
It should be noted that: the technical schemes described in the embodiments of the present invention can be combined arbitrarily without conflict.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (10)

1. A method for epitaxial growth of a silicon wafer, comprising:
a first step of placing the silicon wafer on a disk-shaped susceptor inside a reaction chamber;
a second step of delivering an etching gas into the reaction chamber via a gas inlet to etch the silicon wafer, wherein the gas inlet is located radially outside the susceptor and the susceptor is at a first height level with the gas inlet;
a third step of delivering a silicon source gas into the reaction chamber via the gas inlet to grow an epitaxial layer on the surface of the silicon wafer.
2. The method of claim 1, further comprising a fourth step between the second step and the third step of lowering the base to bring the base at a second height lower than the first height.
3. The method according to claim 1, further comprising a fifth step of performing a pre-heating process on the silicon wafer between the first step and the second step.
4. The method according to claim 3, further comprising a sixth step of baking the silicon wafer under a hydrogen atmosphere between the fifth step and the second step.
5. The method according to claim 1, further comprising a seventh step of purging the reaction chamber with hydrogen gas via the gas inlet to purge the etching gas in the reaction chamber between the second step and the third step.
6. The method of claim 2, wherein the spacing between the first height and the second height is 0.5mm to 2 mm.
7. The method of claim 1, wherein the etching gas is hydrogen chloride gas.
8. The method of claim 7, wherein the flow rate of the hydrogen chloride gas is 0.5slm to 2slm, and the delivery time is 10s to 30 s.
9. An apparatus for epitaxial growth of a silicon wafer, comprising:
an epitaxial reaction apparatus, comprising: a bell jar enclosing the reaction chamber; a disk-shaped susceptor inside the reaction chamber, the susceptor configured to carry the silicon wafer; a gas inlet configured to deliver a reactant gas into the reaction chamber, wherein the gas inlet is located radially outward of the susceptor and the susceptor is at a first height level with the gas inlet;
an etching gas supply configured to deliver an etching gas into the reaction chamber via the gas inlet to etch the silicon wafer;
a silicon source gas supply configured to deliver a silicon source gas into the reaction chamber via the gas inlet to grow an epitaxial layer on the surface of the silicon wafer after the etching gas supply delivers an etching gas into the reaction chamber.
10. The apparatus of claim 9, wherein the epitaxial reactor further comprises a drive mechanism configured to lower the susceptor to bring the susceptor at a second height lower than the first height.
CN202011173810.9A 2020-10-28 2020-10-28 Method and equipment for epitaxial growth of silicon wafer Pending CN112201568A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114108081A (en) * 2021-11-23 2022-03-01 西安奕斯伟材料科技有限公司 Component for guiding gas circulation in silicon wafer epitaxial process and epitaxial growth device
CN114188258A (en) * 2022-02-17 2022-03-15 西安奕斯伟材料科技有限公司 Silicon wafer substrate conveying device and method for improving flatness of epitaxial wafer
CN116072524A (en) * 2023-02-17 2023-05-05 浙江求是创芯半导体设备有限公司 Method for improving slip line of silicon epitaxial wafer

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1936109A (en) * 2005-09-22 2007-03-28 硅电子股份公司 Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers
CN101783288A (en) * 2009-01-14 2010-07-21 硅电子股份公司 Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers
CN101814428A (en) * 2009-02-25 2010-08-25 硅电子股份公司 The manufacture method of the silicon wafer that applies through extension
CN101894743A (en) * 2009-05-20 2010-11-24 硅电子股份公司 The manufacture method of the silicon wafer that applies through extension
CN104576307A (en) * 2013-10-10 2015-04-29 有研新材料股份有限公司 Method for eliminating micro particle aggregation on surface of 12-inch monocrystalline silicon epitaxial wafer
CN106128938A (en) * 2016-08-01 2016-11-16 中国电子科技集团公司第四十六研究所 A kind of VDMOS device method preparing thick-layer extension on thin Sb substrate
CN110578166A (en) * 2019-10-15 2019-12-17 上海新昇半导体科技有限公司 Epitaxial growth apparatus and epitaxial growth method
CN110592665A (en) * 2019-08-09 2019-12-20 上海新昇半导体科技有限公司 Method for improving flatness of semiconductor film

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1936109A (en) * 2005-09-22 2007-03-28 硅电子股份公司 Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers
CN101783288A (en) * 2009-01-14 2010-07-21 硅电子股份公司 Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers
CN101814428A (en) * 2009-02-25 2010-08-25 硅电子股份公司 The manufacture method of the silicon wafer that applies through extension
CN101894743A (en) * 2009-05-20 2010-11-24 硅电子股份公司 The manufacture method of the silicon wafer that applies through extension
CN104576307A (en) * 2013-10-10 2015-04-29 有研新材料股份有限公司 Method for eliminating micro particle aggregation on surface of 12-inch monocrystalline silicon epitaxial wafer
CN106128938A (en) * 2016-08-01 2016-11-16 中国电子科技集团公司第四十六研究所 A kind of VDMOS device method preparing thick-layer extension on thin Sb substrate
CN110592665A (en) * 2019-08-09 2019-12-20 上海新昇半导体科技有限公司 Method for improving flatness of semiconductor film
CN110578166A (en) * 2019-10-15 2019-12-17 上海新昇半导体科技有限公司 Epitaxial growth apparatus and epitaxial growth method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114108081A (en) * 2021-11-23 2022-03-01 西安奕斯伟材料科技有限公司 Component for guiding gas circulation in silicon wafer epitaxial process and epitaxial growth device
CN114188258A (en) * 2022-02-17 2022-03-15 西安奕斯伟材料科技有限公司 Silicon wafer substrate conveying device and method for improving flatness of epitaxial wafer
CN116072524A (en) * 2023-02-17 2023-05-05 浙江求是创芯半导体设备有限公司 Method for improving slip line of silicon epitaxial wafer

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