KR101809742B1 - Path control circuit - Google Patents

Path control circuit Download PDF

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KR101809742B1
KR101809742B1 KR1020100105465A KR20100105465A KR101809742B1 KR 101809742 B1 KR101809742 B1 KR 101809742B1 KR 1020100105465 A KR1020100105465 A KR 1020100105465A KR 20100105465 A KR20100105465 A KR 20100105465A KR 101809742 B1 KR101809742 B1 KR 101809742B1
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signal
column
enable signal
inverting
buffering
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KR20120044072A (en
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박상일
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에스케이하이닉스 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

경로제어회로는 리프레쉬동작 시 디스에이블되는 컬럼인에이블신호를 생성하는 경로활성화신호 생성부; 및 상기 컬럼인에이블신호에 응답하여 외부어드레스를 버퍼링하여 컬럼어드레스를 생성하는 내부어드레스생성부를 포함한다. The path control circuit includes: a path activation signal generation unit for generating a column enable signal that is disabled in a refresh operation; And an internal address generator for generating a column address by buffering an external address in response to the column enable signal.

Description

경로제어회로{PATH CONTROL CIRCUIT}[0001] PATH CONTROL CIRCUIT [0002]

본 발명은 전류소모를 방지할 수 있도록 하는 경로제어회로에 관한 것이다.The present invention relates to a path control circuit for preventing current consumption.

어드레스 경로에는 로우 어드레스에 의해 워드라인을 선택한 후 메모리 셀에 저장된 데이터를 센스앰프에 의해 증폭시키는 경로인 로우어드레스 경로와, 컬럼어드레스에 의해 다수의 출력인에이블신호 중 하나를 선택하는 경로인 컬럼어드레스 경로 및 입출력라인 센스앰프 및 데이터 출력 버퍼를 통해 외부로 데이터를 전송하는 경로인 데이터 경로가 있다. 이 중 컬럼어드레스 경로에 관한 동작(이하, 컬럼동작이라 지칭함)은 컬럼디코더로 구성된 컬럼 경로 회로에 의해 제어되는데, 컬럼 경로 회로는 컬럼어드레스를 디코딩하여 다수의 출력인에이블신호 중 하나를 선택적으로 인에이블시키고, 인에이블된 출력인에이블신호에 의해 선택된 비트라인에 실린 데이터를 입출력라인으로 전송하는 동작을 수행한다.The address path includes a row address path that is a path for selecting a word line by a row address and then amplifying the data stored in the memory cell by a sense amplifier and a row address path for selecting one of a plurality of output enable signals by a column address Path and input / output There is a data path which is a path for transferring data to the outside via a line sense amplifier and a data output buffer. The operation of the column address path (hereinafter referred to as a column operation) is controlled by a column path circuit composed of a column decoder, which decodes the column address and selectively outputs one of the plurality of output enable signals And transmits the data on the bit line selected by the enabled output enable signal to the input / output line.

한편, 디램의 경우 메모리 셀에서 발생되는 누설전류에 의해 시간이 지남에 따라 셀에 저장된 데이터를 잃어버리게 된다. 따라서, 일정 주기마다 셀에 저장된 데이터를 다시 기입해주는 동작을 수행해야 하는데, 이러한 동작을 리프레쉬라 한다. 리프레쉬는 메모리 셀 어레이 안의 각 셀들이 가지는 보유시간(retention time)안에 적어도 한번씩 워드라인을 띄워 해당 워드라인에 연결된 셀의 데이터를 감지 및 증폭시킨 후 셀에 재기록하는 방식으로 수행된다. On the other hand, in the case of the DRAM, the data stored in the cell is lost over time due to the leakage current generated in the memory cell. Therefore, it is necessary to perform an operation of rewriting data stored in a cell every predetermined period, and this operation is called refresh. The refresh is performed by floating a word line at least once within the retention time of each cell in the memory cell array, sensing and amplifying data of the cell connected to the corresponding word line, and rewriting the cell.

리프레쉬는 리프레쉬 커맨드를 받은 후 내부 카운터로부터 로우어드레스를 생성하여 수행되며, 요청이 들어올 때마다 로우 어드레스가 순차적으로 카운팅되게 된다. 이와 같이, 리프레쉬 동작은 로우 어드레쉬의 변경만으로 수행되므로, 컬럼경로의 동작은 불필요하다.The refresh is performed by generating a row address from the internal counter after receiving the refresh command, and the row address is sequentially counted each time a request is received. As described above, since the refresh operation is performed only by changing the row address, the operation of the column path is unnecessary.

본 발명은 리프레쉬 수행 시 컬럼 경로의 동작을 차단하여 전류소모를 방지할 수 있도록 하는 경로제어회로를 개시한다.The present invention discloses a path control circuit for preventing operation of a column path during a refresh operation to prevent current consumption.

이를 위해 본 발명은 리프레쉬동작 시 디스에이블되는 컬럼인에이블신호를 생성하는 경로활성화신호 생성부; 및 상기 컬럼인에이블신호에 응답하여 외부어드레스를 버퍼링하여 컬럼어드레스를 생성하는 내부어드레스생성부를 포함하는 경로제어회로를 제공한다. To this end, the present invention comprises a path activation signal generator for generating a column enable signal to be disabled in a refresh operation; And an internal address generator for generating a column address by buffering an external address in response to the column enable signal.

또한, 본 발명은 리프레쉬동작 시 디스에이블되는 컬럼인에이블신호를 생성하는 경로활성화신호 생성부; 및 상기 컬럼인에이블신호에 응답하여 소스전원을 구동전압에 공급하는 구동전압공급부를 포함하는 경로제어회로를 제공한다.
The present invention also provides a semiconductor memory device comprising: a path activation signal generation unit for generating a column enable signal disabled during a refresh operation; And a drive voltage supply unit for supplying a source voltage to the drive voltage in response to the column enable signal.

도 1은 본 발명의 일 실시예에 따른 경로제어회로의 구성을 도시한 블럭도이다.
도 2는 도 1에 도시된 경로제어회로에 포함된 경로활성화신호 생성부의 도면이다.
도 3은 도 1에 도시된 경로제어회로에 포함된 구동전압 공급부의 도면이다.
도 4는 도 1에 도시된 경로제어회로에 포함된 내부어드레스 생성부의 도면이다.1 is a block diagram showing a configuration of a path control circuit according to an embodiment of the present invention.
2 is a diagram of a path activation signal generator included in the path control circuit shown in FIG.
3 is a diagram of a drive voltage supply included in the path control circuit shown in Fig.
4 is a diagram of an internal address generator included in the path control circuit shown in FIG.

이하, 실시예를 통하여 본 발명을 더욱 상세히 설명하기로 한다. 이들 실시예는 단지 본 발명을 예시하기 위한 것이며, 본 발명의 권리 보호 범위가 이들 실시예에 의해 제한되는 것은 아니다.
Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

도 1은 본 발명의 일 실시예에 따른 경로제어회로의 구성을 도시한 블럭도이다.1 is a block diagram showing a configuration of a path control circuit according to an embodiment of the present invention.

도 1에 도시된 바와 같이, 본 실시예의 경로제어회로는 경로활성화신호 생성부(1), 구동전압 공급부(2) 및 내부어드레스 생성부(3)를 포함한다.1, the path control circuit of the present embodiment includes a path activation signal generation section 1, a drive voltage supply section 2, and an internal address generation section 3. [

경로활성화신호 생성부(1)는, 도 2에 도시된 바와 같이, 펄스신호 생성부(10), 버퍼부(11) 및 컬럼인에이블신호 생성부(12)를 포함한다. 펄스신호 생성부(10)는 뱅크액티브신호(BK_ACTb)를 지연시키는 제1 지연부(100) 및 제2 지연부(101)와, 제1 지연부(100) 및 제2 지연부(101)의 출력신호를 입력받아 부정논리곱 연산을 수행하여 펄스신호(PUL)를 출력하는 낸드게이트(ND10)를 포함한다. 버퍼부(11)는 펄스신호(PUL)를 버퍼링하여 로우인에이블신호(XAE_X)를 출력한다. 컬럼인에이블신호 생성부(12)는 리프레쉬 동작 시 로직하이레벨로 인가되는 리프레쉬신호(REF)를 반전지연시켜 반전리프레쉬신호(REFb)를 출력하는 반전지연부(120)와, 펄스신호(PUL) 및 반전리프레쉬신호(REFb)를 입력받아 논리곱 연산을 수행하여 컬럼인에이블신호(XAE_Y)를 출력하는 인에이블신호 출력부(121)를 포함한다. 리프레쉬 동작이 수행되면 뱅크액티브신호(BK_ACTb)가 로직로우레벨로 인가되고, 리프레쉬신호(REF)가 로직하이레벨로 인가된다.The path activation signal generation section 1 includes a pulse signal generation section 10, a buffer section 11 and a column enable signal generation section 12 as shown in Fig. The pulse signal generating unit 10 includes a first delay unit 100 and a second delay unit 101 for delaying the bank active signal BK_ACTb and a second delay unit 101 for delaying the first active signal BK_ACTb from the first delay unit 100 and the second delay unit 101 And a NAND gate ND10 that receives the output signal and performs a NAND operation to output a pulse signal PUL. The buffer unit 11 buffers the pulse signal PUL and outputs the row enable signal XAE_X. The column enable signal generating unit 12 includes an inversion delay unit 120 for inverting and delaying a refresh signal REF applied at a logic high level during a refresh operation to output an inversion refresh signal REFb, And an enable signal output unit 121 for receiving an inverted refresh signal REFb and performing an AND operation to output a column enable signal XAE_Y. When the refresh operation is performed, the bank active signal BK_ACTb is applied to the logic low level, and the refresh signal REF is applied to the logic high level.

이와 같은 구성의 경로활성화신호 생성부(1)는 리프레쉬 동작이 수행되어 로직하이레벨의 리프레쉬신호(REF)가 인가되는 경우 로우레벨로 인에이블되는 반전리프레쉬신호(REFb)에 의해 컬럼인에이블신호(XAE_Y)는 로직로우레벨로 디스에이블된다.The path activation signal generating unit 1 having such a configuration generates the column enable signal REFb by the inverted refresh signal REFb which is enabled to the low level when the refresh operation is performed and the logic high level refresh signal REF is applied. XAE_Y) is disabled to a logic low level.

구동전압공급부(2)는, 도 3에 도시된 바와 같이, 컬럼인에이블신호(XAE_Y)를 반전지연시키는 반전지연부(20)와, 반전지연부(20)의 출력신호에 응답하여 소스전원(VPERI)을 구동전압(VPERIB)에 연결하는 스위치부(21)를 포함한다. 스위치부(21)는 스위치소자로 동작하는 PMOS 트랜지스터(P21)와 퓨즈(F20)를 포함한다. 여기서, 구동전압(VPERIB)은 컬럼동작을 위한 제어회로가 구동되기 위해 사용되는 전압이다.3, the driving voltage supply unit 2 includes an inversion delay unit 20 for inverting and delaying the column enable signal XAE_Y and a source power supply (in response to the output signal of the inversion delay unit 20) (VPERI) to the driving voltage VPERIB. The switch unit 21 includes a PMOS transistor P21 that operates as a switch element and a fuse F20. Here, the driving voltage VPERIB is a voltage used for driving the control circuit for column operation.

이와 같은 구성의 구동전압공급부(2)는 리프레쉬 동작이 수행되는 경우 로직로우레벨로 디스에이블된 컬럼인에이블신호(XAE_Y)에 의해 턴오프되는 PMOS 트랜지스터(P21)에 의해 소스전원(VPERI)이 구동전압(VPERIB)에 공급되지 않도록 한다. The driving voltage supply unit 2 having such a configuration is configured such that the source power source VPERI is driven by the PMOS transistor P21 turned off by the column enable signal XAE_Y disabled to a logic low level when the refresh operation is performed Voltage VPERIB.

내부어드레스생성부(3)는, 도 4에 도시된 바와 같이, 컬럼인에이블신호(XAE_Y)를 지연시키는 지연부(30)와, 지연부(30)의 출력신호에 응답하여 제1 외부어드레스(A1D)를 반전버퍼링하여 제1 컬럼어드레스(BAYB<1>)를 생성하는 반전버퍼부(31)와, 지연부(30)의 출력신호에 응답하여 제2 외부어드레스(A2D)를 반전버퍼링하여 제2 컬럼어드레스(BAYB<2>)를 생성하는 반전버퍼부(32)를 포함한다.4, the internal address generating unit 3 includes a delay unit 30 for delaying the column enable signal XAE_Y and a second external address Inverted buffering unit 31 inverts the second external address A2D in response to the output signal of the delay unit 30 to generate a first column address BAYB < And an inverting buffer unit 32 for generating two column addresses (BAYB &lt; 2 &gt;).

이와 같은 구성의 내부어드레스생성부(3)는 리프레쉬 동작이 수행되는 경우 로직로우레벨로 디스에이블된 컬럼인에이블신호(XAE_Y)에 의해 제1 컬럼어드레스(BAYB<1>) 및 제2 컬럼어드레스(BAYB<2>)를 로직하이레벨로 고정시킨다. 즉, 리프레쉬 동작에서 제1 컬럼어드레스(BAYB<1>) 및 제2 컬럼어드레스(BAYB<2>)가 토글링되지 않도록 한다.The internal address generating unit 3 having the above-described structure generates the first column address BAYB < 1 > and the second column address BAYB < 1 > by the column enable signal XAE_Y disabled to a logic low level when the refresh operation is performed. BAYB < 2 >) to a logic high level. That is, the first column address BAYB <1> and the second column address BAYB <2> are not toggled in the refresh operation.

이상 살펴본 경로제어회로의 동작을 도 5를 참고하여 살펴보면 다음과 같다.The operation of the above-described path control circuit will be described with reference to FIG.

우선, 리프레쉬 동작이 수행되면 로직하이레벨로 인가되는 리프레쉬신호(REF)에 의해 경로활성화신호 생성부(1)는 t2 시점에서 로직로우레벨로 디스에이블된 컬럼인에이블신호(XAE_Y)를 생성한다.First, when the refresh operation is performed, the path activation signal generator 1 generates the column enable signal XAE_Y disabled at the logic low level at time t2 by the refresh signal REF applied at a logic high level.

다음으로, 구동전압공급부(2)는 로직로우레벨로 디스에이블된 컬럼인에이블신호(XAE_Y)에 의해 소스전원(VPERI)이 구동전압(VPERIB)에 공급되지 않도록 한다.Next, the driving voltage supply unit 2 prevents the source voltage VPERI from being supplied to the driving voltage VPERIB by the column enable signal XAE_Y that is disabled to a logic low level.

다음으로, 내부어드레스생성부(3)는 로직로우레벨로 디스에이블된 컬럼인에이블신호(XAE_Y)에 의해 제1 컬럼어드레스(BAYB<1>) 및 제2 컬럼어드레스(BAYB<2>)가 토글링되지 않도록 한다.Next, the internal address generator 3 generates a first column address BAYB <1> and a second column address BAYB <2> by a column enable signal XAE_Y disabled to a logic low level, Ring.

본 실시예의 경로제어회로는 컬럼동작이 불필요한 리프레쉬 동작에 있어, 컬럼인에이블신호(XAE_Y)를 디스에이블시킴으로써, 소스전원(VPERI)이 구동전압(VPERIB)에 공급되지 않도록 하고, 제1 컬럼어드레스(BAYB<1>) 및 제2 컬럼어드레스(BAYB<2>)가 토글링되지 않도록 하여 불필요한 전류가 소모되는 것을 방지한다.
The path control circuit of the present embodiment disables the column enable signal XAE_Y to prevent the source voltage VPERI from being supplied to the drive voltage VPERIB in the refresh operation in which the column operation is unnecessary, BAYB < 1 &gt;) and the second column address (BAYB < 2 &gt;) are not toggled so that unnecessary current is prevented from being consumed.

1: 경로활성화신호 생성부 10: 펄스신호 생성부
12: 컬럼인에이블신호 생성부 120: 반전지연부
121: 인에이블신호 출력부 2: 구동전압 공급부
21: 스위치부1: Path activation signal generation unit 10: Pulse signal generation unit
12: a column enable signal generating unit 120:
121: Enable signal output unit 2: Driving voltage supply unit
21: Switch section

Claims (8)

리프레쉬동작 시 디스에이블되는 컬럼인에이블신호를 생성하는 경로활성화신호 생성부; 및
상기 컬럼인에이블신호에 응답하여 외부어드레스를 버퍼링하여 컬럼어드레스를 생성하는 내부어드레스생성부를 포함하되, 상기 경로활성화신호 생성부는 뱅크액티브신호가 인에이블된 후 소정 구간이 경과된 후 펄스신호를 발생시키는 펄스발생부 및 반전리프레쉬신호에 응답하여 펄스발생부의 출력신호를 버퍼링하여 상기 컬럼인에이블신호를 생성하는 제1 버퍼부를 포함하는 경로제어회로.
A path activation signal generation unit for generating a column enable signal disabled in a refresh operation; And
And an internal address generator for generating a column address by buffering an external address in response to the column enable signal, wherein the path activation signal generator generates a pulse signal after a predetermined period elapses after the bank active signal is enabled And a first buffer unit for buffering an output signal of the pulse generator in response to the pulse generator and the inverted refresh signal to generate the column enable signal.
삭제delete [청구항 3은(는) 설정등록료 납부시 포기되었습니다.][Claim 3 is abandoned upon payment of the registration fee.] 제 1 항에 있어서,
상기 펄스발생부의 출력신호를 버퍼링하여 로우인에이블신호를 생성하는 제2 버퍼부; 및
상기 리프레쉬 동작 시 인에이블되는 리프레쉬신호를 반전지연시켜 상기 반전리프레쉬신호를 생성하는 반전지연부를 포함하는 경로제어회로.
The method according to claim 1,
A second buffer for buffering an output signal of the pulse generator to generate a row enable signal; And
And an inverting delay unit for inverting and delaying the refresh signal enabled in the refresh operation to generate the inverted refresh signal.
[청구항 4은(는) 설정등록료 납부시 포기되었습니다.][Claim 4 is abandoned upon payment of the registration fee.] 제 1 항에 있어서, 상기 내부어드레스생성부는
상기 컬럼인에이블신호에 응답하여 제1 외부어드레스를 반전버퍼링하여 제1 컬럼어드레스를 생성하는 제1 반전버퍼부; 및
상기 컬럼인에이블신호에 응답하여 제2 외부어드레스를 반전버퍼링하여 제2 컬럼어드레스를 생성하는 제2 반전버퍼부를 포함하는 경로제어회로.
2. The apparatus of claim 1, wherein the internal address generator
A first inverting buffer unit for inverting and buffering a first external address in response to the column enable signal to generate a first column address; And
And a second inverting buffer for inverting and buffering the second external address in response to the column enable signal to generate a second column address.
리프레쉬동작 시 디스에이블되는 컬럼인에이블신호를 생성하는 경로활성화신호 생성부; 및
상기 컬럼인에이블신호에 응답하여 소스전원을 구동전압에 공급하는 구동전압공급부를 포함하되, 상기 경로활성화신호 생성부는 뱅크액티브신호가 인에이블된 후 소정 구간이 경과된 후 펄스신호를 발생시키는 펄스발생부; 및 반전리프레쉬신호에 응답하여 펄스발생부의 출력신호를 버퍼링하여 상기 컬럼인에이블신호를 생성하는 제1 버퍼부를 포함하는 경로제어회로.
A path activation signal generation unit for generating a column enable signal disabled in a refresh operation; And
And a drive voltage supply unit for supplying a source voltage to the drive voltage in response to the column enable signal, wherein the path activation signal generation unit generates a pulse signal for generating a pulse signal after a predetermined period elapses after the bank active signal is enabled, part; And a first buffer unit for buffering an output signal of the pulse generator in response to an inverted refresh signal to generate the column enable signal.
삭제delete [청구항 7은(는) 설정등록료 납부시 포기되었습니다.][7] has been abandoned due to the registration fee. 제 5 항에 있어서,
상기 펄스발생부의 출력신호를 버퍼링하여 로우인에이블신호를 생성하는 제2 버퍼부; 및
상기 리프레쉬 동작 시 인에이블되는 리프레쉬신호를 반전지연시켜 상기 반전리프레쉬신호를 생성하는 반전지연부를 포함하는 경로제어회로.
6. The method of claim 5,
A second buffer for buffering an output signal of the pulse generator to generate a row enable signal; And
And an inverting delay unit for inverting and delaying the refresh signal enabled in the refresh operation to generate the inverted refresh signal.
[청구항 8은(는) 설정등록료 납부시 포기되었습니다.][8] has been abandoned due to the registration fee. 제 5 항에 있어서, 상기 구동전압공급부는
상기 컬럼인에이블신호를 반전버퍼링하는 반전버퍼부;
상기 소스전원과 상기 구동전압 사이에 직렬 연결된 스위치소자 및 퓨즈를 포함하되, 상기 스위치소자는 상기 반전버퍼부의 출력신호에 응답하여 턴온되는 경로제어회로.
The plasma display apparatus according to claim 5, wherein the driving voltage supply unit
An inverting buffer unit for inverting and buffering the column enable signal;
And a switching element and a fuse connected in series between the source power source and the driving voltage, wherein the switching element is turned on in response to an output signal of the inverting buffer part.
KR1020100105465A 2010-10-27 2010-10-27 Path control circuit KR101809742B1 (en)

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