KR101782369B1 - Method of controlling polarity of data voltage and liquid crystal display using the same - Google Patents

Abstract

The present invention relates to a polarity control method of a data voltage and a liquid crystal display device using the same. A method of controlling a polarity of a data voltage according to the present invention includes the steps of: (a) analyzing a degree of polarity balance of input image data in units of dots (I is any one of multiples of 3 between 3 and 18) Selecting a polarity pattern of a control signal and a polarity pattern of an inverted polarity control signal generated by an inverted signal of the default polarity control signal; (b) is a natural number satisfying L (L is a natural number satisfying 1? L? p, p is the number of gate lines in the display panel) The number of data lines) of the (N + 1) th pixel data is compared with the polarity of the (N + 1) th pixel data, and if the polarity of the Nth pixel data is the same as the polarity of the And converts the N-th pixel data using the second look-up table if the polarity of the N-th pixel data and the polarity of the N + 1-th pixel data are not identical step; And (c) converting the converted image data into a positive / negative polarity analog data voltage, inverting the polarity of the data voltage in the selected polarity pattern, and outputting the inverted data voltage to the data lines of the liquid crystal display panel, And the Nth pixel data converted using the first look-up table has higher luminance than the Nth pixel data converted using the second look-up table.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of controlling polarity of a data voltage and a liquid crystal display using the same,

The present invention relates to a polarity control method of a data voltage and a liquid crystal display device using the same.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is also applied to a television, thereby quickly replacing a cathode ray tube.

Liquid crystal cells of a liquid crystal display display an image by changing the transmittance according to the potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode. The liquid crystal display device is driven in an inversion mode in which the polarity of the data voltage applied to the liquid crystal is periodically inverted to reduce the afterimage and prevent deterioration of the liquid crystal.

When the liquid crystal display device is driven in the inversion mode, the image quality of the liquid crystal display device may be deteriorated according to the correlation between the polarity of the data voltage charged in the liquid crystal cells and the data pattern of the input image. If the data of the problem pattern as shown in FIG. 1 is included in the input image, the polarity of the data voltages charged in the liquid crystal display panel may not be balanced between the positive polarity and the negative polarity, and one polarity may appear as the dominant polarity. In this case, the common voltage applied to the common electrode in the dominant polarity direction is shifted. When the common voltage is shifted, since the reference potential of the liquid crystal cells is fluctuated, the observer can feel flicker or smear in the image displayed on the liquid crystal display device.

1 shows data examples of a problem pattern in which image quality may be deteriorated when a liquid crystal display is driven in a dot-in version. Referring to FIG. 1, a pattern in which pixel data (white) of white gradation and pixel data (black) of black gradation alternate in units of one pixel is referred to as a shutdown pattern. Each of the pixel data includes red subpixel data R, green subpixel data G, and blue subpixel data B, respectively. The method of detecting the shutdown pattern can count the shutdown pattern included in the input image and judge whether or not the shutdown pattern is in accordance with the count value. For example, in the method of detecting the shutdown pattern, the count value of the problem pixel counter is incremented by 1 when the N-th (N is a natural number) pixel data is white gradation pixel data and the (N + 1) th pixel data is black gradation pixel data When the count value is equal to or larger than a predetermined threshold value, the data of the input image is determined as a shutdown pattern. To recognize the shutdown pattern, a maximum of (2 ³ -1) × 2 = 14 patterns that can appear in six subpixels must be defined in advance, and a logic circuit is required to detect each of the patterns.

A pattern in which pixel data (white) of white gradation and pixel data (black) of black gradation alternate in units of two pixels is called a smear pattern. Each of the pixel data includes red subpixel data R, green subpixel data G, and blue subpixel data B, respectively. The method of detecting a squared pattern can count the squared pattern included in the input image and determine whether the squared pattern is a squared pattern according to the count value. For example, a method of detecting a squared pattern is a method of detecting a sum of a count value of a problem pixel counter when Nth and N + 1 pixel data are pixel data of white tones, and when N + 2 and N + 3 pixel data are black gradation pixel data, And the data of the input image is determined as a smear pattern when the count value is equal to or greater than a predetermined threshold value. In the case of a squared pattern, a maximum of (2 ⁶ -1) x 2 = 126 patterns that can appear in 12 subpixel data must be defined in advance, and a detection logic circuit for detecting each of the patterns is required Do.

Further, the problematic patterns causing the shift of the common voltage Vcom are not limited to the shutdown pattern or the squared pattern. The problem pattern includes one pixel of data includes white-level subpixel data (white) and black-level subpixel data.

Prior art has to predefine a large amount of basic patterns to define each of the problem patterns in order to recognize various types of problem patterns. Therefore, the conventional technique requires a large memory storage capacity for defining basic patterns, requires a logic circuit that compares the basic patterns with input patterns, and compares the results with a threshold value, resulting in high hardware complexity and high circuit cost . Further, in the related art, if the problem pattern is recognized, the polarity of the data voltage can be changed in a direction that suppresses the shift of the common voltage, and the polarity change point can not be applied to the next line data or the next frame data. The polarity conversion of the data voltage is equally applied to non-problematic patterns smaller than the threshold value.

The polarity conversion method has a method of selecting either a horizontally 1 dot inversion (horizontal 1 dot inversion) or horizontal 2 dot version depending on the problem pattern type. The horizontal one-dot version converts the polarities of the data voltages charged in the liquid crystal cells of 4k (k is a positive integer) to 4k + 4 dots arranged side by side on the same horizontal display line in the liquid crystal display panel as follows . The polarity of the data voltage charged in the liquid crystal cell of 4k (k is a positive integer) + 1 dot is positive (+) while the polarity of the data voltage charged in the liquid crystal cell of 4k (k is a positive integer) The polarity of the data voltage charged in the liquid crystal cell of 4k + 2 dots is negative (-), the polarity of the data voltage charged in the liquid crystal cell of the (4k + 3) The negative polarity of the data voltage charged in the liquid crystal cell of the liquid crystal cell is converted to negative (-). In the horizontal one-dot version, the polarity of the data voltage charged in the liquid crystal cell of the (4k + 1) th dot is negative (-) while the polarity of the data voltage charged in the liquid crystal cell of the The polarity of the data voltage charged in the liquid crystal cell of the (4k + 3) -th dot is set to the negative (-), the polarity of the data voltage charged in the liquid crystal cell of the (+), Respectively. Therefore, the version with the horizontal one dot is a circuit in which the polarities of the data voltages charged in the liquid crystal cells arranged on the same horizontal display line in the liquid crystal display panel are repeated from left to right in the order of "+ - + -" or "- + - + .

The horizontal two-dot version converts the polarities of the data voltages charged in the liquid crystal cells of the fourth to fourth (k + 4) -th dots arranged side by side on the same horizontal display line in the liquid crystal display panel as follows. In the horizontal two-dot version, the polarity of the data voltage charged in the liquid crystal cell of the (4k + 1) -th dot is positive (+) while the polarity of the data voltage charged in the liquid crystal cell of the (-), the polarity of the data voltage charged in the liquid crystal cell of the (4k + 3) th dot is negative (-), the polarity of the data voltage charged in the liquid crystal cell of the +). In the horizontal two-dot version, the polarity of the data voltage charged in the liquid crystal cell of the (4k + 1) -th dot is negative (-) while the polarity of the data voltage charged in the liquid crystal cell of the The polarity of the data voltage charged in the liquid crystal cell of the (4k + 3) th dot is set to the positive (+), and the polarity of the data voltage charged in the liquid crystal cell of the And negative polarity (-), respectively. Therefore, in the horizontal two-dot version, the polarities of the data voltages charged in the liquid crystal cells arranged in the same horizontal display line in the liquid crystal display panel are repeated from left to right in the order of "+ - - +" or "- + + - .

When the polarity pattern of the data voltages is converted from the shutdown pattern to the one-dot-horizontal version, the number of the positive polarity data voltages is about twice as large as that of the negative polarity data voltages, and the polarity of the data voltages is shifted toward the positive polarity , Whereby the common voltage Vcom is shifted toward the positive polarity data voltage. When the polarity of the data is converted to the horizontal two-dot version of the polarity of the data in the same shutdown pattern, the positive polarity data voltage and the negative polarity data voltage are balanced as shown in FIG. 3, and the common voltage Vcom is not shifted.

However, in the prior art, there is a problem pattern data in which the common voltage Vcom is shifted in both the horizontal 1-dot version and the horizontal 2-dot version. For example, both of the horizontal one-dot and horizontal two-dot versions cause polarity irregularities of data voltages on the input image data including the flicker pattern as shown in FIGS. 4 and 5, thereby improving the common voltage shift phenomenon I can not. Thus, the prior art fails to polarize the data voltages in some problematic patterns.

The present invention eliminates the need for a basic pattern necessary for problem pattern recognition and can provide a polarity balancing effect of data voltages in any type of problem pattern as well as providing data that can compensate for the difference between pixels due to the polarity balance effect A polarity control method of a voltage and a liquid crystal display using the same are provided.

A method of controlling a polarity of a data voltage according to the present invention includes the steps of: (a) analyzing a degree of polarity balance of input image data in units of dots (I is any one of multiples of 3 between 3 and 18) Selecting a polarity pattern of a control signal and a polarity pattern of an inverted polarity control signal generated by an inverted signal of the default polarity control signal; (b) is a natural number satisfying L (L is a natural number satisfying 1? L? p, p is the number of gate lines in the display panel) The number of data lines) of the (N + 1) th pixel data is compared with the polarity of the (N + 1) th pixel data, and if the polarity of the Nth pixel data is the same as the polarity of the And converts the N-th pixel data using the second look-up table if the polarity of the N-th pixel data and the polarity of the N + 1-th pixel data are not identical step; And (c) converting the converted image data into a positive / negative polarity analog data voltage, inverting the polarity of the data voltage in the selected polarity pattern, and outputting the inverted data voltage to the data lines of the liquid crystal display panel, And the Nth pixel data converted using the first look-up table has higher luminance than the Nth pixel data converted using the second look-up table.

A liquid crystal display device of the present invention includes: a liquid crystal display panel in which data lines and gate lines cross each other; The polarity pattern of the default polarity control signal and the polarity pattern of the reverse polarity control signal are selected by analyzing the degree of polarity balance of the input image in I (I is any one of multiples of 3 between 3 and 18) (N is a natural number satisfying 1? L? Q, where q is a natural number satisfying 1? L? P, p is a natural number satisfying 1? (N + 1) th pixel data and the polarity of the (N + 1) -th pixel data are the same, the first look-up table is used Up table, and converts the Nth pixel data by using the second look-up table if the polarity of the Nth pixel data and the polarity of the (N + 1) A timing controller including a compensation unit; And a source driver IC for converting the converted image data into positive / negative analog data voltages, inverting the polarity of the data voltages in the selected polarity pattern, and outputting the inverted data voltages to the data lines of the liquid crystal display panel, And the N-th pixel data converted using the look-up table has higher luminance than the N-th pixel data converted using the second look-up table.

A method of controlling a polarity of a data voltage according to the present invention includes the steps of: (a) analyzing a degree of polarity balance of input image data in units of dots (I is any one of multiples of 3 between 3 and 18) Selecting a polarity pattern of a control signal and a polarity pattern of an inverted polarity control signal generated by an inverted signal of the default polarity control signal; (b) is a natural number satisfying L (L is a natural number satisfying 1? L? p, p is the number of gate lines in the display panel) (N + 1) -th pixel data, the polarity of the (N + 1) -th pixel data is equal to the polarity of the 1 header data and adding the second header data to the Nth pixel data when the polarity of the Nth pixel data and the polarity of the (N + 1) th pixel data are not identical, and outputting the converted image data ; And (c) separating the converted image data into the first and second header data and the image data, and thereafter dividing the first and second header data into a first positive / negative polarity gamma compensation voltage and a second positive / And outputs a selection signal for selecting any one of the polarity / negative polarity gamma compensation voltage, and supplies the image data to the first polarity / negative polarity analog data voltage or the second polarity / negative polarity analog data voltage And inverting the polarity of the data voltage in the selected polarity pattern and outputting the inverted data voltage to the data lines of the liquid crystal display panel, wherein the first positive / 2 positive polarity / negative polarity analog data voltages.

A liquid crystal display device of the present invention includes: a liquid crystal display panel in which data lines and gate lines cross each other; The polarity pattern of the default polarity control signal and the polarity pattern of the reverse polarity control signal are selected by analyzing the degree of polarity balance of the input image in I (I is any one of multiples of 3 between 3 and 18) (N is a natural number satisfying 1? L? Q, where q is a natural number satisfying 1? L? P, p is a natural number satisfying 1? And the polarity of the (N + 1) th pixel data is equal to the polarity of the (N + 1) th pixel data, Adding the header data and adding the second header data to the Nth pixel data when the polarity of the Nth pixel data and the polarity of the (N + 1) th pixel data are not identical, and outputting the converted image data, A timing controller including a part; And separating the converted image data into the first and second header data and the image data, and thereafter dividing the first and second header data into a first positive / negative gamma compensation voltage and a second positive / Polarity gamma compensation voltage, and converts the image data into either the first positive / negative polarity analog data voltage or the second positive / negative polarity analog data voltage according to the selection signal And a source drive IC for inverting the polarity of the data voltage in the selected polarity pattern and outputting the data voltage to the data lines of the liquid crystal display panel, wherein the first positive / negative polarity analog data voltage is applied to the second And has a luminance higher than the positive / negative polarity analog data voltage.

The present invention analyzes the polarity balance of the input image in units of dots and selects either the polarity pattern of the default polarity control signal or the polarity pattern of the reverse polarity control signal. As a result, according to the present invention, there is no need for reference patterns for recognizing a problem pattern defined in advance in the input image, and it is possible to finely adjust the polarity of data according to the data pattern of the input image, The polarity imbalance can be finely corrected in real time even in the pattern.

Further, the present invention compares the polarity of the pixel data corrected for the polarity imbalance, and compensates the brightness of the reference pixel data when the polarity of the pixel data is the same. As a result, the present invention can compensate for the luminance difference that may occur between pixel data whose polarity imbalance is corrected.

1 is a diagram illustrating problem patterns in a liquid crystal display device in a horizontal one-dot version.
FIG. 2 is a diagram showing data polarity irregularity of a shutdown pattern in a horizontal 1-dot version. FIG.
Figure 3 is a plot showing the data polarity uniformity of the shutdown pattern in a horizontal two dot version.
4 is a diagram showing the data polarity irregularity of the flicker pattern in the horizontal 1-dot version.
5 is a diagram showing data polarity irregularity of a flicker pattern in a horizontal two-dot version.
6 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.
7 is a block diagram showing the timing controller in detail.
FIG. 8 is a block diagram showing the fly-eye polarity selector shown in FIG. 7 in detail.
9 is a flowchart showing the control procedure of the fly-eye polarity selection unit.
10 is a table for defining the first and second polarity control data.
11 is a diagram showing a problem pattern in which a luminance difference between pixel data may occur in accordance with the fly-eye polarity control procedure in driving the Z-inversion version.
12 is a detailed block diagram of a data compensator according to the first embodiment of the present invention.
13 is a flowchart showing the control procedure of the data compensating unit of FIG.
14A is a gamma curve curve of 8-bit data, FIG. 14B is a gamma curve curve of 10-bit data stored in the first look-up table, and FIG. 14C is a gamma curve curve of 10-bit data stored in the second look- FIG.
15 is a waveform diagram showing an example of a digital data stream transmitted from the timing controller to the source drive ICs.
16 is a detailed block diagram of a source drive IC according to the first embodiment of the present invention.
17 is a circuit diagram showing the gamma reference voltage generating circuit shown in FIG. 16 in detail.
FIG. 18 is a circuit diagram showing the digital-analog converter shown in FIG. 16 in detail.
19 is a detailed block diagram of a data compensator according to a second embodiment of the present invention.
FIG. 20 is a flowchart showing the control procedure of the data compensating unit of FIG. 19;
FIG. 21 is a detailed block diagram illustrating a source drive IC according to a second embodiment of the present invention.
FIG. 22 is a circuit diagram showing the gamma reference voltage generating circuit shown in FIG. 21 in detail.
23 is a detailed circuit diagram of the digital-analog converter shown in Fig.
24 is a graph showing gamma curve curves of the gamma reference voltage input to the gamma reference voltage generating circuit shown in FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

6 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention. Referring to FIG. 6, a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 101, a data driving circuit 102, and a gate driving circuit 103. The data driving circuit 102 includes a plurality of source drive ICs (Integrated Circuit). The gate drive circuit 103 includes a plurality of gate drive ICs.

In the liquid crystal display panel 100, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 100 includes liquid crystal cells Clc arranged in a matrix form by an intersection structure of the data lines 105 and the gate lines 106. [ On the lower glass substrate of the liquid crystal display panel 100, a TFT array is formed. The TFT array includes liquid crystal cells Clc formed at the intersections of the data lines 105 and the gate lines 106, TFTs connected to the pixel electrode 1 of the liquid crystal cells, and a storage capacitor Cst do. The liquid crystal cells Clc are connected to the TFT and driven by the electric field between the pixel electrodes 1 and the common electrode 2. [ On the upper glass substrate of the liquid crystal display panel 100, a color filter array including a black matrix, a color filter, and the like is formed. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system.

The liquid crystal display panel 100 applicable to the present invention can be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 101 converts 8 bits of digital video data RGB input from the system board 104 into 10 bits of digital video data RGB ' 102). Alternatively, the timing controller 101 converts the 8-bit digital video data (RGB) input from the system board 104 into 10-bit digital video data RGB 'including a header part for discriminating whether luminance compensation is required, (102).

The timing controller 101 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK from the system board 104, And generates control signals for controlling the operation timing of the driving circuit 102 and the gate driving circuit 103. [ The control signals include a gate timing control signal for controlling the operation time of the gate drive circuit 103, a data timing control signal for controlling the operation timing of the data drive circuit 102 and the vertical polarity of the data voltage.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to the gate drive IC which generates the first gate pulse to control the gate drive IC so that the first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs. The timing controller 101 transmits the gate timing control signal to the gate drive ICs via a separate control signal bus transmission line.

The data timing control signal includes first polarity control data G_POL, second polarity control data G_HINV, a source output enable signal SOE, output channel selection option data G_MODE1 and G_MODE2, . The first polarity control data G_POL includes data voltages to be charged in the liquid crystal cells Clc of I (I is any one of multiples of 3 between 3 and 18) arranged adjacent to the same horizontal line, The polarity of the first data voltage. The second polarity control data G_HINV controls the horizontal polarity pattern of the data voltages to be charged in the liquid crystal cells Clc of the I-dots arranged adjacently to the same horizontal line. In the following embodiments, the I-dot is described by taking 6 dots as an example, but 3 dots, 9 dots, 12 dots, 15 dots and 18 dots are also applicable to the polar pattern conversion unit of the present invention, Be careful. The source output enable signal SOE controls the output timing of the source drive ICs. The output channel selection option data (G_MODE1, G_MODE2) is input to the source drive ICs supporting multi-channel to select the output channel number of the source drive ICs and disable the unselected output channel. The timing controller 101 outputs a data timing control signal such as first and second polarity control data G_POL and G_HINV and output channel selection option data G_MODE1 and G_MODE2 together with 10 bits of digital video data RGB ' To the source drive ICs via bus transmission lines. The timing controller 101 transmits the source output enable signal SOE to the source drive ICs via a separate control signal bus transmission line.

The timing controller 101 internally generates a default polarity control signal POL and an inverse polarity control signal / POL. The timing controller 101 assigns weights according to the gradation levels to each of the input image data and virtually applies the default polarity control signal POL and the reverse polarity control signal / POL to generate the default polarity control signal POL and the reverse polarity control The polarity imbalance degree of the data voltages to be charged in the liquid crystal cells of the liquid crystal display panel 100 in each of the signals / POL. The timing controller 101 supplies a default polarity control signal POL and an inverse polarity control signal / POL (POL) to the liquid crystal cells of the liquid crystal display panel 100 in units of dots so as to balance the positive and negative polarities of the data voltages to be charged in the liquid crystal cells of the liquid crystal display panel 100. [ ).

The default polarity control signal POL is a horizontal polarity pattern of data voltages to be charged in the liquid crystal cells arranged on the same horizontal display line in the liquid crystal display panel and is a horizontal one dot in the timing controller 101 or a horizontal two dot Version pattern. The reversal polarity control signal / POL is generated in a version pattern whose phase is the reverse phase of the default polarity control signal POL and which is either a horizontal 1 dot version or a horizontal 2 dot. The information of the default polarity control signal POL and the reverse polarity control signal / POL is coded into the first and second polarity control data G_POL and G_HINV and transmitted to the source drive ICs, And restores the default polarity control signal POL and the reverse polarity control signal / POL in response to the second polarity control data G_POL, G_HINV.

The data driving circuit 102 latches the 10-bit digital video data RGB 'in response to the data timing control signal. The data driving circuit 102 converts the 10-bit digital video data RGB 'into analog positive / negative gamma compensation voltages PGMA and NGMA in response to the vertical polarity control signal POL, Generates a polarity data voltage, and simultaneously outputs data voltages having a polar pattern of a horizontal dot that is determined according to the horizontal polarity control signal (HINV).

The gate driving circuit 103 sequentially supplies gate pulses to the gate lines 106 in response to gate timing control signals.

7 is a block diagram showing the timing controller 101 in detail. 7, the timing controller 101 includes a data receiving unit 11, an internal algorithm processing unit 12, a fly-eye polarity selecting unit 13, a data logic processing unit 14, a data compensating unit 15, (16) and the like.

The data receiving unit 11 receives digital video data RGB, vertical / horizontal synchronizing signals Vsync and Hsync from the system board 104 through an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling ), A data enable signal (Data Enable, DE), and a dot clock (CLK).

The internal algorithm processing unit 12 processes predetermined algorithms such as FRC (Frame Rate Control), ODC (Over Driving Control) algorithm, MEMC (Motion Estimation / Motion Compensation) algorithm and BDI (Black Data Insertion). The internal algorithm processing unit 12 also counts the timing signals input from the system board 104 to generate a gate timing signal, a data timing signal, and a default polarity control signal POL.

The fly-eye polarity selection unit 13 assigns weights according to the gradation levels of the digital video data (RGB) input from the internal algorithm processing unit 12 as shown in Figs. 8 and 9, The polarity pattern of the default polarity control signal POL and the polarity of the reverse polarity control signal / POL is virtually applied. The fly-eye polarity selection section 13 counts the positive number and the negative number of the I-dot data to which the default polarity control signal POL and the reverse polarity control signal / POL are applied, To determine the degree of polarity imbalance. The fly-eye polarity selector 13 selects the polarity pattern of the I-dot data to which the polarity pattern of the default polarity control signal POL is applied and the cumulative polarity count result of the polarity pattern of the reverse polarity control signal / And generates a polarity selection control signal CTRPOL indicating a smaller one of the count results. And the fly-eye polarity selector 13 generates a fly-eye polarity select signal FEPOL for finely adjusting the polarity of data in I-dot units in response to the polarity-selection control signal CTRPOL.

The data logic processing unit 14 receives the digital video data RGB from the internal algorithm processing unit 12 and receives the fly-eye polarity selection signal FEPOL from the fly-eye polarity selection unit 13. [ The data logic processing unit 14 generates a data signal indicating the horizontal polarity inversion period of the fly-eye polarity selection signal FEPOL and the first polarity of the I-dot so that the fly-eye polarity selection signal FEPOL can be restored by the source drive ICs 1 and second polarity control data G_POL, G_HINV. The data logic processing unit 14 supplies the digital video data RGB and the first and second polarity control data G_POL and G_HINV to the data compensation unit 15. [ In addition, the data logic processing unit 14 supplies control data such as output channel selection option data (G_MODE1, G_MODE2) to the data transmission unit 16.

The data compensating unit 15 virtually applies the first and second polarity control data G_POL and G_HINV to the digital video data RGB input from the data logic processing unit 14. [ The data compensating section 15 compares the Nth (N: 1? L? Q) of the line of L (L is a natural number satisfying 1? L? P and p is the number of gate lines of the display panel 10) And q is the number of data lines of the display panel 10), and compares the polarity of the pixel data with the polarity of the (N + 1) th pixel data. The data compensating unit 15 differently converts the Nth pixel data according to the polarity of the Nth pixel data of the Lth line and the polarity of the (N + 1) th pixel data. The data compensator 15 supplies the data transmitter 16 with 10-bit digital video data RGB 'and first and second polarity control data G_POL and G_HINV.

The data transmission unit 16 includes 10-bit digital video data RGB 'input from the data logic processing unit 14 and the data compensation unit 15, first and second polarity control data G_POL and G_HINV, Data such as option data (G_MODE1, G_MODE2) is transmitted to the source drive ICs through the data bus transmission lines in the mini-LVDS interface standard as shown in FIG.

FIG. 8 is a block diagram showing the fly-eye polarity selector shown in FIG. 7 in detail. 9 is a flowchart showing the control procedure of the fly-eye polarity selection unit. 8 and 9, the fly-eye polarity selector 13 includes a weight assigning unit 31, a first polarity applying unit 32, a second polarity applying unit 33, a first counter 34, A first cumulative counter 36, a second cumulative counter 37, a polarity selector 38, a first multiplexer 39, and the like.

The weight assigning unit 31 assigns weights to the RGB digital video data of the odd pixel and the RGB digital video data of the superior pixel, respectively, according to the gradation level. (S1) The weight assigning unit 31 adds the weight '1 And gives a weight value '0' to the black gradation data. The white gradation data and the black gradation data can be determined as the most significant bit (MSB). The weighting assignment unit 31 determines data having the most significant 2 bits as " 11 ₂ "as white tone data and determines data having the highest two bits as " 00 ₂ " as black tone data.

 The first polarity applying unit 32 applies the polarity pattern of the default polarity control signal POL to the weight W6RGB assigned for each data. (S2) The second polarity applying unit 33 applies a weight value The first and second polarity applying units 32 and 33 apply a polarity pattern of the inversion polarity control signal / POL to the weight given to the black level data W6RGB. The polarity pattern of the polarity control signal (POL or / POL) is applied only to the white gradation data. The reverse polarity control signal / POL is output through an inverter which inverts the default polarity control signal POL.

The first counter 34 counts the number of positive polarity and the number of negative polarity of the white gradation data in units of I dots for the polarity application results input from the first polarity applying section 32, And the first negative polarity count result to the first cumulative counter 36. (S4) The second counter 35 counts the polarity applying results input from the second polarity applying unit 33 The second positive polarity count result and the second negative polarity count result, which are the results of counting the number of positive polarity and the number of negative polarity of the white tone data, are supplied to the second cumulative counter 37. (S5)

The first cumulative counter 36 counts the first positive count result input from the first counter 34 and the first negative count result input from the first counter 34 in the first previous count result to which the polarity pattern of the default polarity control signal POL is applied (S6) The second cumulative counter 37 adds the difference to the second counter 35 in the second previous count result to which the polarity pattern of the reverse polarity control signal / POL is applied. (S7) The first positive polarity count result for the nth I dot data is added to the P-count negative count result by adding the difference between the second positive polarity count result and the second negative polarity count result, (N), the first negative polarity count result is N-count # 1 (n), the second positive polarity count result is P-count # 2 (n), the second negative polarity count result is N-count # 2 count # 2 (n), the first cumulative count result is Accum-count # 1 (n), the second cumulative count result is Accum-count # 2 Count # 1 (n) = Accum-count (n-1) + P-count # 1 (n) - N-count # 1 (n) and Accum-count # 2 (n) = Accum-count (n-1) + P-count # 2 (n) -N-count # 2 (n).

The polarity selector 38 inputs the previous cumulative count result to the first and second cumulative counters 36 and 37. The polarity selector 38 selects the minimum value among the first cumulative count result and the second cumulative count result and generates the polarity selection control signal CTRPOL indicating the polarity pattern applied to the minimum value. (S8) The first multiplexer 39 selects the default polarity control signal POL and the reverse polarity control signal / POL in response to the polarity selection control signal CTRPOL input from the polarity selection unit 38 and outputs the flywheel polarity selection signal FEPOL Occurs. The fly-eye polarity selection signal FEPOL is a final polarity control signal for finely controlling the polarity of the data voltage in units of dots for the liquid crystal cells disposed adjacent to the same horizontal line in the liquid crystal display panel 100, (14).

10 is a table for defining the first and second polarity control data. 10, if the first polarity control data G_POL is logic high, the source driver IC generates the first polarity of the I dot in the polarity control signal POL or / POL at negative polarity. The source drive IC generates the positive polarity (+) of the first polarity of the I-dot in the polarity control signal POL or / POL if the first polarity control data G_POL is low logic. The source drive IC generates the horizontal polarity control signal HINV in the form of a horizontal 2 dot version if the second polarity control data G_HINV is high logic and the horizontal polarity control signal HINV in the horizontal direction if the second polarity control data G_HINV is low logic. The polarity control signal HINV is generated in the form of a horizontal one-dot version (H1Dot). The source drive IC converts the polarities of the data voltages output to the data lines in response to the first and second polarity control data (G_POL, G_HINV) input from the timing controller 101 based on the tables of FIG. 10 .

For example, when the first polarity control data G_POL is a high logic and the second polarity control data G_HINV is a high logic, the source driver IC charges six neighboring liquid crystal cells horizontally when the I dot is 6 dots. (+ - - + + -) which is the horizontal two-dot starting from the positive polarity. The source drive IC is configured such that when the first polarity control data G_POL is high logic and the second polarity control data G_HINV is low logic, when the I dot is 6 dots, The polarity is converted to a horizontal one-dot version (+ - + - + -) starting at positive polarity. The source drive IC may be configured such that when the first polarity control data G_POL is low logic and the second polarity control data G_HINV is high logic, when the I dot is 6 dots, (- + + - - +) which is a horizontal two-dot starting from negative polarity. The source drive IC is configured such that when the first polarity control data G_POL is low logic and the second polarity control data G_HINV is low logic, when the I dot is 6 dots, (- + - + - +) which is a horizontal one dot starting from negative polarity.

11 is a diagram showing a problem pattern in which a luminance difference between pixel data may occur in accordance with the fly-eye polarity control procedure in driving the Z-inversion version. 11, in the case of the Z-inversion mode, the source driver IC is driven in a version scheme, which is a column for inverting the polarity of the data voltage for each column line, but the pixels of the display panel 10 are set to have the polarity of the data voltage per dot It is characterized by being driven by a version-in-version scheme. Therefore, the Z-inversion method has an advantage that the power consumption can be reduced even though it is driven by the dot-inversion method.

11 shows a polarity control method of a fly's-eye polarity according to the present invention. When polarity of data voltages supplied to the first to twelfth data lines DL1 to DL12 in the Z-inversion method is 6 dots, 10) are shown. In FIG. 11, the source driver IC supplies a data voltage in a horizontal one-dot version to the first to sixth data lines DL1 to DL6 and a horizontal two-dot data line in the seventh to twelfth data lines DL7 to DL12. And the data voltage is supplied in the inversion mode. At this time, the polarity of the pixels C8 of the eighth column among the pixels C7 to C12 of the seventh to twelfth columns supplied with the data voltage of the horizontal two-dot version is the same as that of the ninth data line And the polarity of the pixels C10 in the tenth column is the same as the polarity of the adjacent eleventh data line DL11. However, the pixels C8 and C10 of the eighth and tenth columns before the gate pulse is supplied from the gate line GL in the next frame maintain the polarity of the data voltage of the previous frame, but the ninth and eleventh data lines The polarities of the data lines DL9 and DL11 are inverted so that the pixels C8 and C10 of the eighth and tenth columns are affected by the ninth and eleventh data lines DL9 and DL11 whose polarity is inverted. Thus, even if the same-sized positive / negative polarity data voltages are supplied to the pixels C1 to C12 of the first to twelfth columns, the brightness of the pixels C8 and C10 of the eighth and tenth columns The luminance of the pixels C 1 to C 7, C 9, C 11, and C 12 of the first to seventh, ninth, eleventh, and twelfth columns is lowered. Therefore, it is necessary to compensate for the brightness of the pixels whose brightness has been lowered by the fly-eye polarity selecting unit 13. Hereinafter, a method of compensating the inter-pixel luminance difference according to the first embodiment of the present invention will be described with reference to FIGS. 12 to 18, A method of compensating for the difference in luminance between adjacent pixels will be described.

12 is a detailed block diagram of a data compensator according to the first embodiment of the present invention. 13 is a flowchart showing the control procedure of the data compensating unit of FIG. 12 and 13, the data compensating unit 15 includes a third polarity applying unit 41, a data comparing unit 42, first and second look-up tables 43a and 43b, Section 44 and the like.

The third polarity applying section 41 applies the first polarity control data G_POL and the second polarity control data G_HINV to the digital video data RGB inputted from the data logic processing section 14. For example, the third polarity applying unit 41 may add 1-bit data to the header portion of the N-th pixel data according to the polarity / negative polarity. That is, when the Nth pixel data is positive, the third polarity applying unit 41 may add '1' (or '0') to the header portion of the Nth pixel data. In addition, when the Nth pixel data is negative, the third polarity applying unit 41 may add '0' (or '1') to the header portion of the Nth pixel data. (S11)

The data comparing unit 42 compares the polarity of the Nth pixel data on the Lth line with the polarity of the (N + 1) th pixel data. The data comparing unit 42 converts the Nth pixel data using the first look-up table 43a when the polarity of the Nth pixel data is the same as the polarity of the N + 1 pixel data. The first look-up table 43a receives the 8th-bit Nth pixel data as an input address, and outputs 10-bit Nth pixel data stored in the input address. When the polarity of the Nth pixel data is different from the polarity of the N + 1 pixel data, the data comparator 42 converts the Nth pixel data using the second look-up table 43b. The second look-up table 43b receives 8th-bit Nth pixel data as an input address, and outputs 10-bit Nth pixel data stored in the input address. The present invention converts the gamma curve of the Nth pixel data from nonlinear to linear by converting the Nth pixel data from 8 bits to 10 bits using the first look-up table 43a. The present invention uses the second look-up table 43b to convert the Nth pixel data from 8 bits to 10 bits, but in this case the gamma curve of the Nth pixel data remains unchanged. Details of the first and second look-up tables 43a and 43b will be described later in conjunction with FIGS. 14A to 14C. (S12 to S15)

The data comparing unit 42 performs steps S12 to S15 for all pixel data of one frame period. (S16 to S19)

The data output unit 44 outputs the digital video data RGB 'converted to 10 bits by using the first look-up table 43a or the second look-up table 43b according to the selection of the data comparing unit 42, To the data transmission unit (16). (S20)

14A is a gamma curve curve of 8-bit data, FIG. 14B is a gamma curve curve of 10-bit data stored in the first look-up table, and FIG. 14C is a gamma curve curve of 10-bit data stored in the second look- FIG. 14A to 14C, the x-axis shows the gray level and the y-axis shows the gamma reference voltage (GMA). In FIG. 14A, the gray level is represented by 0 to 255, but in FIG. 14B and FIG. 14C, the gray level is represented by 0 to 1023. 14A, the gamma curve curve of the 8-bit data input to the timing controller 101 and the gamma curve curve of the 10-bit data stored as the output value corresponding to the input address of the second look-up table, as shown in FIG. 14C, Can be set the same.

The first look-up table 43a stores 8-bit Nth pixel data whose gamma curve is non-linearly represented as an input address, as shown in FIG. 14A. The first look-up table 43a stores 10-bit Nth pixel data whose gamma curve is linear, as an output value corresponding to an input address, as shown in FIG. 14B.

The second look-up table 43b stores 8-bit Nth pixel data in which the gamma curve is non-linearly represented as an input address, as shown in FIG. 14A. The second look-up table 43b stores 10-bit Nth pixel data whose gamma curve is non-linear, as an output value corresponding to an input address, as shown in FIG. 14C.

The linear gamma curve of FIG. 14B has a lower data voltage at the same gradation in the low gradation region than the non-linear gamma curve of FIGS. 14A and 14C, but a higher data voltage at the same gradation in the high gradation region Data voltage. However, there is an effect that the luminance is higher in the linear gamma curve of FIG. 14B than the non-linear gamma curve of FIGS. 14A and 14C. This is because the linear gamma curve of FIG. 14B has a higher data voltage at the same gradation in the high gradation region than the non-linear gamma curve of FIGS. 14A and 14C, Because it has a lower data voltage at the same gray level of the region than the effect of lowering the brightness.

On the other hand, the low gradation region means the gradation region having the fifth to the fourteenth gamma reference voltages, and the high gradation region means the gradation region having the first to fourth gamma reference voltages and the fifteenth to eighteenth gamma reference voltages . The gamma curve curves of Figs. 14A to 14C can be determined by a preliminary experiment.

As a result, when the polarity of the Nth pixel data is the same as the polarity of the N + 1 pixel data, the Nth pixel data is converted using the first look-up table 43a. In this case, the Nth pixel data is converted to a higher data value than the input data value, so that the luminance is increased. Accordingly, the present invention can solve the problem that the luminance of the Nth pixel data is lowered due to the influence of the (N + 1) th data line when the polarity of the Nth pixel data is the same as the polarity of the (N + 1) th pixel data.

15 is a waveform diagram showing an example of a digital data stream transmitted from the timing controller to the source drive ICs. 15 shows an example in which a digital data stream is transmitted between the timing controller 101 and the source drive ICs in a mini LVDS (Low Voltage Differential Signaling) interface standard.

15, the timing controller 101 receives the clock signal CLK +, R, G, and B digital video data, polarity control data G_POL, and G_HINV as a differential signal pair of the mini LVDS interface specification, , And output channel selection option data (G_MODE1, G_MODE2) to the source drive ICs through the data bus transmission lines. 15 shows only the positive polarity data among the differential signal pairs. CLK + is a clock bus transmission line through which a positive clock signal is transmitted, and LV1 + to LV7 + are data bus transmission lines through which a positive polarity data stream is transmitted. D00 to D29 are 10-bit odd digital video data (RGB '). D30 to D59 are 10-bit superior digital video data (RGB ').

16 is a detailed block diagram of a source drive IC according to the first embodiment of the present invention. 17 is a circuit diagram showing the gamma reference voltage generating circuit shown in FIG. 16 in detail. FIG. 18 is a circuit diagram showing the digital-analog converter shown in FIG. 16 in detail. Referring to Figs. 16 to 18, each of the source drive ICs supplies data voltages to data lines D1 to Dj (j is a positive integer smaller than the number of data lines). Each of the source drive ICs includes a data receiver 201, an internal control signal generator 202, a shift register 203, a latch 204, a digital-to-analog converter (hereinafter referred to as DAC) 205, A circuit 206, a voltage dividing circuit 207, and a gamma reference voltage generating circuit 208.

The data receiving unit 201 receives the clock signal, the digital video data, the polarity control data G_POL, G_HINV, and the output channel selection option through the data bus transmission lines LVO + to LV7-, CLK +, and CLK- And receives differential signal pairs including data (G_MODE1, G_MODE2). The data receiving unit 201 samples the polarity control data G_POL and G_HINV and the output channel selection option data G_MODE1 and G_MODE2 in the differential signal pair based on the clock signal and supplies the sampled digital data to the internal control signal generator 202 Supply. The data receiving unit 201 samples the RGB digital video data in the differential signal pair on the basis of the clock signal, and transmits the digital video data to the latch 204. The SB inputted to the data receiving unit 201 is an option signal for changing the data sorting order. EIO1 and EIO2 input to the data receiving unit 201 are start pulses of the shift register 203. [ The data receiving unit 201 is synchronized with the shift register 203 in response to EI01 and EI02.

The internal control signal generating unit 202 restores the default polarity control signal POL and the reverse polarity control signal / POL according to the polarity control data G_POL and G_HINV and generates the horizontal polarity control signal HINV. The default polarity control signal POL, the reverse polarity control signal / POL and the horizontal polarity control signal HINV are supplied to the DAC 205. The internal control signal generation unit 202 generates a channel enable / disable signal (not shown) according to the output channel selection option data (G_MODE1, G_MODE2) and supplies the signal to the output unit 206.

The shift register 203 shifts EI01 and EIO2 to generate an internal clock signal and supplies the internal clock signal to the latch 204. [ L / R is an option signal for changing the shift direction of the shift register 203. The latch 204 sequentially latches RGB digital video data from the data receiving unit 201 in response to an internal clock signal sequentially input from the shift register 203 and sequentially outputs the data to a source output enable signal SOE And outputs them at the same time.

The gamma reference voltage generating circuit 208 includes a positive gamma reference voltage generating circuit and a negative gamma reference voltage generating circuit. The gamma reference voltage generating circuit 208 generates the first to ninth gamma reference voltages GMA1 to GMA9 of positive polarity and the tenth to eighteenth (GMA1 to GMA9) of the negative polarity by using a resistor connection circuit (R-String) To GMA18). The first to eighteenth gamma reference voltages GMA1 to GMA18 generated from the gamma reference voltage generating circuit 208 have a gamma curve curve as shown in FIG. 14C.

The voltage dividing circuit 209 divides the positive gamma reference voltages and the negative gamma reference voltages inputted from the gamma reference voltage generating circuit 208. The voltage divider circuit 209 generates positive gamma compensation voltages (PGMA) and negative gamma compensation voltages (NGMA) corresponding to the respective gradations of the 10-bit digital video data RGB '. The voltage divider circuit 209 supplies the positive gamma compensation voltages (PGMA) and the negative gamma compensation voltages (NGMA) to the DAC 205.

The DAC 205 includes a P-decoder 21A to which positive polarity gamma compensation voltages PGMA are supplied, an N-decoder 21B to which negative polarity gamma compensation voltages NGMA are supplied, The multiplexers 22 # 1 to # 6 for selecting the output of the P-decoder 21A and the output of the N-decoder 21B in response to any one of the POL and / POL signals, the horizontal polarity control signal HINV And a horizontal polarity control circuit 23 for inverting the polarity control signal POL or / POL in response to the polarity control signal POL or / POL. The P-decoder 21A decodes the digital video data input from the latch 204 and outputs a positive gamma compensation voltage corresponding to the tone value of the data. The N-decoder 21B decodes the digital video data input from the latch 204 and outputs a negative gamma compensation voltage corresponding to the tone value of the data.

The multiplexers 22 # 1 to # 6 are divided into I and select one of the positive gamma compensation voltage and the negative gamma compensation voltage in response to the default polarity control signal POL or the reverse polarity control signal / POL . The default polarity control signal POL is input to the control terminals of the first to sixth multiplexers 22 # 1 to # 6 by fly-eye polarity selection (FEPOL) when I is 6, The inverted polarity control signal / POL may be input to the control terminals of the seventh to twelfth multiplexers (not shown). The horizontal polarity control circuit 23 outputs a polarity control signal POL or (j) to the control terminals of the 4j + 3 and 4j + 4 multiplexers 22 # 3 and 22 # 4 in response to the horizontal polarity control signal HINV / POL) to switch between a horizontal one-dot version and a horizontal two-dot version.

The first multiplexer 22 # 1 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its non-inverted control terminal, And outputs the polarity / negative polarity gamma compensation voltage as the analog data voltage OUT1. The second multiplexer 22 # 2 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its inverting control terminal and outputs the selected positive / And outputs the negative gamma compensation voltage as the analog data voltage OUT2. The third multiplexer 22 # 3 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its non-inverted control terminal, / Negative polarity gamma compensation voltage as the analog data voltage OUT3. The fourth multiplexer 22 # 4 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its inversion control terminal, And outputs the negative gamma compensation voltage as the analog data voltage OUT # 4. The fifth multiplexer 22 # 5 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its non-inverted control terminal, And outputs the polarity / negative polarity gamma compensation voltage as the analog data voltage OUT5. The sixth multiplexer 22 # 2 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its inverting control terminal and outputs the selected positive / And outputs the negative gamma compensation voltage as the analog data voltage OUT6.

The horizontal polarity control circuit 23 includes switch elements S1 and S2, and an inverter INV. The horizontal polarity control circuit 23 outputs the polarity control signals POL and / or POL to the control terminals of the 4j + 3 and 4j + 4 multiplexers 22 # 3 and 22 # 4 in response to the horizontal polarity control signal HINV. POL). The first switch element S1 directly outputs the polarity control signal POL or / POL to the 4j + 3 and 4j + 4 multiplexers 22 # 3 and 22 # 3 in response to the horizontal polarity control signal HINV of the low logic value, 4). The second switch device S2 inverts the logical value of the polarity control signal POL or / POL in response to the horizontal polarity control signal HINV of the high logic value to generate the fourth j + 3 and fourth j + 4 multiplexers 22 # 3, 22 # 4). Therefore, if the horizontal polarity control signal HINV is a high logic value, the polarity of the first to fourth data voltages OUT1 to OUT4 is a horizontal two-dot version pattern, that is, "+ - ". On the other hand, if the horizontal polarity control signal HINV is a low logical value, the polarity of the first to fourth data voltages OUT1 to OUT4 is a version pattern of horizontal one dot, that is, "+ - + - + ".

The output section 206 outputs the data voltage from the DAC 205 to the data lines through the output buffer. The output unit 206 disables the output channel in which the data voltage is not output in response to the channel enable / disable signal input from the internal control signal generating unit 202.

19 is a detailed block diagram of a data compensator according to a second embodiment of the present invention. FIG. 20 is a flowchart showing the control procedure of the data compensating unit of FIG. 19; 19 and 20, the data compensating unit 15 includes a third polarity applying unit 41, a data comparing unit 42, a data converting unit 45, and a data output unit 46 .

The third polarity applying section 41 applies the first polarity control data G_POL and the second polarity control data G_HINV to the digital video data RGB inputted from the data logic processing section 14. For example, the third polarity applying unit 41 may add 1 bit (or 2 bits) of data to the header portion of the Nth pixel data according to the polarity / negative polarity. That is, when the Nth pixel data is positive, the third polarity applying unit 41 may add '1' (or '0') to the header portion of the Nth pixel data. In addition, when the Nth pixel data is negative, the third polarity applying unit 41 may add '0' (or '1') to the header portion of the Nth pixel data. (S101)

The data comparing unit 42 compares the polarity of the Nth pixel data on the Lth line with the polarity of the (N + 1) th pixel data. The data conversion unit 45 adds header data of the first logical value to the header portion of the N-th pixel data when the polarity of the N-th pixel data is the same as the polarity of the N + 1-th pixel data, And the polarity of the (N + 1) -th pixel data is not the same, header data of the second logical value is added to the header portion of the N-th pixel data. For example, when the polarity of the N-th pixel data is the same as the polarity of the N + 1-th pixel data, the data conversion unit 45 may add 2-bit data '00' to the header part of the N-th pixel data. The data converting unit 45 may add 2-bit data '11' to the header portion of the N-th pixel data when the polarity of the N-th pixel data is different from the polarity of the N + 1-th pixel data. It should be noted that '00' and '11' are merely one embodiment, and thus the present invention is not limited thereto. The data conversion unit 45 adds the header data to the header portion of the N-th pixel data to distinguish whether the N-th pixel data is positive / negative in the third polarity applying unit 41 One bit (or two bits) of data can be deleted. (S102 to S105)

The data comparing unit 42 and the data converting unit 45 perform steps S102 to S105 for all pixel data of one frame period. (S106 to S109)

The data output unit 46 outputs the 10-bit digital video data RGB 'converted by the data conversion unit 45 to the data transmission unit 16. (S110)

FIG. 21 is a detailed block diagram illustrating a source drive IC according to a second embodiment of the present invention. FIG. 22 is a circuit diagram showing the gamma reference voltage generating circuit shown in FIG. 21 in detail. 23 is a detailed circuit diagram of the digital-analog converter shown in Fig.

Referring to Figs. 21 to 23, each of the source drive ICs supplies data voltages to data lines D1 to Dj (j is a positive integer smaller than the number of data lines). Each of the source drive ICs includes a data receiver 201, an internal control signal generator 202, a shift register 203, a latch 204, a digital-to-analog converter (hereinafter referred to as DAC) 205, A circuit 206, a voltage dividing circuit 207, and a gamma reference voltage generating circuit 208.

The data receiving unit 201 receives the clock signal, the digital video data, the polarity control data G_POL, G_HINV, and the output channel selection option through the data bus transmission lines LVO + to LV7-, CLK +, and CLK- And receives differential signal pairs including data (G_MODE1, G_MODE2). The data receiving unit 201 samples the polarity control data G_POL and G_HINV and the output channel selection option data G_MODE1 and G_MODE2 in the differential signal pair based on the clock signal and supplies the sampled digital data to the internal control signal generator 202 Supply.

The data receiving unit 201 separates 10-bit digital video data RGB 'into 2-bit header data and 8-bit digital video data. The data receiving unit 201 samples the first to jth header data Hd1 to Hdj in the differential signal pair on the basis of the clock signal and supplies the digital data to the internal control signal generating unit 202. [ The data receiving unit 201 samples the 8-bit digital video data in the differential signal pair based on the clock signal, and transmits the sampled 8-bit digital video data to the latch 204. The SB inputted to the data receiving unit 201 is an option signal for changing the data sorting order. EIO1 and EIO2 input to the data receiving unit 201 are start pulses of the shift register 203. [ The data receiving unit 201 is synchronized with the shift register 203 in response to EI01 and EI02.

The internal control signal generating unit 202 restores the default polarity control signal POL and the reverse polarity control signal / POL according to the polarity control data G_POL and G_HINV and generates the horizontal polarity control signal HINV. The internal control signal generator 202 supplies the DAC 205 with a default polarity control signal POL, an inverted polarity control signal / POL and a horizontal polarity control signal HINV. The internal control signal generation unit 202 generates a channel enable / disable signal (not shown) according to the output channel selection option data (G_MODE1, G_MODE2) and supplies the signal to the output unit 206. The internal control signal generator 202 generates first to jth selection signals S1 to Sj according to the first to jth header data Hd1 to Hdj. The internal control signal generator 202 supplies the first to j-th selection signals S1 to Sj to the DAC 205. [

The shift register 203 shifts EI01 and EIO2 to generate an internal clock signal and supplies the internal clock signal to the latch 204. [ L / R is an option signal for changing the shift direction of the shift register 203. The latch 204 sequentially latches RGB digital video data from the data receiving unit 201 in response to an internal clock signal sequentially input from the shift register 203 and sequentially outputs the data to a source output enable signal SOE And outputs them at the same time.

The gamma reference voltage generating circuit 208 includes a positive gamma reference voltage generating circuit and a negative gamma reference voltage generating circuit. The gamma reference voltage generating circuit 208 generates the first positive / negative polarity gamma reference voltages GMA1 (GMA1) by using a first resistor connection circuit (R-String1) and a second resistor connection circuit To GMA18 and second positive / negative gamma reference voltages GMA1 'to GMA18'. The first positive gamma reference voltages GMA1 to GMA9 and the first negative gamma reference voltages GMA10 to GMA18 generated from the gamma reference voltage generating circuit 208 are input to the first gamma curve C1 of FIG. , The second positive polarity gamma reference voltages GMA1 'to GMA9' and the second negative polarity gamma reference voltages GMA10 'to GMA18' have the second gamma curve C2 of FIG. A detailed description thereof will be given later with reference to FIG.

The voltage divider circuit 209 divides the first positive polarity gamma reference voltages GMA1 to GMA9 and the first negative polarity gamma reference voltages GMA10 to GMA18 inputted from the gamma reference voltage generating circuit 208. [ The voltage dividing circuit 209 generates the first positive gamma compensation voltages PGMA1 and the first negative gamma compensation voltages NGMA1 corresponding to the respective gradations of the 8-bit digital video data. The voltage dividing circuit 209 divides the second positive polarity gamma reference voltages GMA1 'to GMA9' and the second negative polarity gamma reference voltages GMA10 'to GMA18' input from the gamma reference voltage generating circuit 208 do. The voltage dividing circuit 209 generates second positive polarity gamma compensation voltages PGMA2 and second negative polarity gamma compensation voltages NGMA2 corresponding to each of the gradations of 8-bit digital video data. The voltage divider circuit 209 supplies the first and second positive gamma compensation voltages PGMA1 and PGMA2 and the first and second negative gamma compensation voltages NGMA1 and NGMA2 to the DAC 205. [

The DAC 205 generates the first and second positive gamma compensation voltages PGMA1 and PGMA2, the first and second negative gamma compensation voltages NGMA1 and NGMA2, and the first to j < th > A decoder 21 to which one of the selection signals S1 to Sj is supplied and multiplexers 21 to 23 which select any one of the outputs of the decoder 21 in response to any one of the polarity control signals POL and / And a horizontal polarity control circuit 23 for inverting the polarity control signal POL or / POL in response to the horizontal polarity control signal HINV.

The decoder 21 includes a first P-decoder 201A to which first positive gamma compensation voltages PGMA1 are supplied, a second P-decoder 202A to which second positive gamma compensation voltages PGMA2 are supplied, A first N-decoder 201B to which first negative polarity gamma compensation voltages NGMA1 are supplied, a second N-decoder 202B to which negative polarity gamma compensation voltages NGMA2 are supplied, a second multiplexer 203 for selecting the output of the first P-decoder 201A and the output of the second P-decoder 202A in response to the selection signal Sk, where k is a natural number satisfying 1? k? And a third multiplexer 204 for selecting the output of the first N-decoder 201B and the output of the second N-decoder 202B in response to the kth select signal Sk.

The first P-decoder 201A decodes the digital video data input from the latch 204 and outputs a first positive gamma compensation voltage corresponding to the tone value of the data. The second P-decoder 202A decodes the digital video data input from the latch 204 and outputs a second positive gamma compensation voltage corresponding to the tone value of the data. The first N-decoder 201B decodes the digital video data input from the latch 204 and outputs a first negative gamma compensation voltage corresponding to the gray level value of the data. The second N-decoder 202B decodes the digital video data input from the latch 204 and outputs a second negative gamma compensation voltage corresponding to the tone value of the data. The second multiplexer 203 is responsive to the kth selection signal Sk to generate a first positive gamma compensation voltage which is the output of the first P-decoder 201A and a second positive gamma compensation voltage which is the output of the second P- And the polarity gamma compensation voltage. For example, the second multiplexer 203 selects and outputs the first positive gamma compensation voltage when the kth selection signal is the third logical value, and outputs the second positive gamma compensation voltage when the k selection signal is the fourth logical value. It can be designed to select and output a voltage. The third multiplexer 204 is responsive to the kth selection signal Sk to generate a first negative gamma compensation voltage which is the output of the first N-decoder 201B and a second negative gamma compensation voltage that is the output of the second N- And the polarity gamma compensation voltage. For example, the third multiplexer 204 selects and outputs the first negative polarity gamma compensation voltage when the kth selection signal is the third logical value, and outputs the second negative polarity gamma compensation when the k selection signal is the fourth logical value. It can be designed to select and output a voltage. The third logic value may be set to a high logic value (or '1'), and the fourth logic value may be set to a low logic value (or '0').

The multiplexers 22 # 1 to # 6 are divided into I and I groups so that the positive and negative gamma compensation voltages outputted from the decoder 21 in response to the default polarity control signal POL or the inverse polarity control signal / Voltage is selected. The default polarity control signal POL is input to the control terminals of the first to sixth multiplexers 22 # 1 to # 6 by fly-eye polarity selection (FEPOL) when I is 6, The inverted polarity control signal / POL may be input to the control terminals of the seventh to twelfth multiplexers (not shown). The horizontal polarity control circuit 23 outputs a polarity control signal POL or (j) to the control terminals of the 4j + 3 and 4j + 4 multiplexers 22 # 3 and 22 # 4 in response to the horizontal polarity control signal HINV / POL) to switch between a horizontal one-dot version and a horizontal two-dot version.

The first multiplexer 22 # 1 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its non-inverted control terminal, And outputs the polarity / negative polarity gamma compensation voltage as the analog data voltage OUT1. The second multiplexer 22 # 2 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its inverting control terminal and outputs the selected positive / And outputs the negative gamma compensation voltage as the analog data voltage OUT2. The third multiplexer 22 # 3 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its non-inverted control terminal, / Negative polarity gamma compensation voltage as the analog data voltage OUT3. The fourth multiplexer 22 # 4 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its inversion control terminal, And outputs the negative gamma compensation voltage as the analog data voltage OUT # 4. The fifth multiplexer 22 # 5 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its non-inverted control terminal, And outputs the polarity / negative polarity gamma compensation voltage as the analog data voltage OUT5. The sixth multiplexer 22 # 2 selects either the positive gamma compensation voltage or the negative gamma compensation voltage in response to the polarity control signal POL or / POL supplied to its inverting control terminal and outputs the selected positive / And outputs the negative gamma compensation voltage as the analog data voltage OUT6.

The horizontal polarity control circuit 23 includes switch elements S1 and S2, and an inverter INV. The horizontal polarity control circuit 23 outputs the polarity control signals POL and / or POL to the control terminals of the 4j + 3 and 4j + 4 multiplexers 22 # 3 and 22 # 4 in response to the horizontal polarity control signal HINV. POL). The first switch element S1 directly outputs the polarity control signal POL or / POL to the 4j + 3 and 4j + 4 multiplexers 22 # 3 and 22 # 3 in response to the horizontal polarity control signal HINV of the low logic value, 4). The second switch device S2 inverts the logical value of the polarity control signal POL or / POL in response to the horizontal polarity control signal HINV of the high logic value to generate the fourth j + 3 and fourth j + 4 multiplexers 22 # 3, 22 # 4). Therefore, if the horizontal polarity control signal HINV is a high logic value, the polarity of the first to fourth data voltages OUT1 to OUT4 is a horizontal two-dot version pattern, that is, "+ - ". On the other hand, if the horizontal polarity control signal HINV is a low logical value, the polarity of the first to fourth data voltages OUT1 to OUT4 is a version pattern of horizontal one dot, that is, "+ - + - + ".

The output section 206 outputs the data voltage from the DAC 205 to the data lines through the output buffer. The output unit 206 disables the output channel in which the data voltage is not output in response to the channel enable / disable signal input from the internal control signal generating unit 202.

24 is a graph showing gamma curve curves of the gamma reference voltage input to the gamma reference voltage generating circuit shown in FIG. Referring to FIG. 24, the x-axis shows the gray level and the y-axis shows the gamma reference voltage (GMA). At this time, the gray level is represented by 0 to 255.

The second gamma curve curve C2 has a higher positive polarity gamma reference voltage than the first gamma curve curve C1. That is, since the first gamma reference voltage GMA1 'of the second gamma curve C2 is set higher than the first gamma reference voltage GMA1 of the first gamma curve C1, the second gamma curve C2 The second to eighth gamma reference voltages GMA2 'to GMA8' of the first to the eighth gamma reference voltages GMA2 to GMA8 of the first gamma curve C1 are set higher than the second to eighth gamma reference voltages GMA2 to GMA8 of the first gamma curve C1. Therefore, in the same gradation, the positive gamma reference voltage of the second gamma curve curve C2 is higher than the positive gamma reference voltage of the first gamma curve C1, thereby causing the second gamma curve C2 at the same gradation, Is higher than the luminance of the first gamma curve curve (C1).

The second gamma curve curve C2 has a lower negative gamma reference voltage as compared to the first gamma curve curve C1. That is, since the eighteenth gamma reference voltage GMA18 'of the second gamma curve C2 is set to be lower than the eighteenth gamma reference voltage GMA18 of the first gamma curve C1, the second gamma curve C2 Are also set to be lower than the eleventh to seventeenth gamma reference voltages GMA11 to GMA17 of the first gamma curve curve C1. Therefore, in the same gradation, the negative gamma reference voltage of the second gamma curve curve C2 is lower than the negative gamma reference voltage of the first gamma curve C1 so that the second gamma curve C2 Is higher than the luminance of the first gamma curve curve C1.

As a result, the present invention generates the positive and negative gamma reference voltages of the first gamma curve C1 using the first resistor connection circuit (R-String) of the gamma reference voltage generating circuit 208, Polarity and negative gamma reference voltages of the second gamma curve curve C2 are generated using a resistor connection circuit (R-String). At this time, the positive and negative gamma reference voltages of the second gamma curve C2 generated by using the second resistance connection circuit R-String are applied to the first resistance connection circuit R- Is greater than the positive and negative gamma reference voltages of the gamma curve curve C1. Therefore, the luminance of the positive and negative gamma reference voltages of the second gamma curve curve C2 generated by using the second resistance connection circuit (R-String) in the same gradation level is obtained by using the first resistance connection circuit (R-String) And the luminance of the negative gamma reference voltages of the first gamma curve C1 generated by the first gamma curve curve C1. Therefore, in the present invention, when the polarity of the Nth pixel data and the polarity of the (N + 1) th pixel data are the same, the second gamma generated by using the second resistance connection circuit By generating the data voltage by the positive polarity and negative polarity reference voltages of the curve curve C2, it is possible to solve the problem that the luminance of the Nth pixel data is affected by the (N + 1) th data line. On the other hand, the first gamma curve C1 and the second gamma curve C2 can be determined by a preliminary experiment.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

11: Data receiving unit 12: Internal algorithm processing unit
13: fly-eye polarity selection unit 14: data logic processing unit
15: data compensating unit 16: data transmitting unit
31: Weight assignment 32: First polarity application part
33: second polarity applying section 34: first counter
35: second counter 36: first cumulative counter
37: second cumulative counter 38: polarity selector
39: multiplexer 41: third polarity application unit
42: data comparison unit 43a: first look-up table
43b: second look-up table 44, 46: data output section
45: data conversion unit 100: liquid crystal display panel
101: timing controller 102: data driving circuit
104: Gate driving circuit 201: Data receiver
202: internal control signal generator 203: shift register
204: latch 205: DAC
206: output circuit 207: voltage dividing circuit
208: gamma reference voltage generating circuit

Claims (22)

(a) analyzing a degree of polarity balance of input image data in I (I is any one of 3 to 18) dots, and comparing the polarity pattern of the default polarity control signal with the polarity pattern of the default polarity control signal in the I- Selecting one of a polarity pattern of an inverted polarity control signal generated as an inverted signal of the control signal;
(b) is a natural number satisfying L (L is a natural number satisfying 1? L? p, p is the number of gate lines in the display panel) The number of data lines) of the (N + 1) th pixel data is compared with the polarity of the (N + 1) th pixel data, and if the polarity of the Nth pixel data is the same as the polarity of the And converts the N-th pixel data using the second look-up table if the polarity of the N-th pixel data and the polarity of the N + 1-th pixel data are not identical step; And
(c) converting the converted pixel data into a positive / negative analog data voltage, inverting the polarity of the data voltage in the selected polarity pattern, and outputting the reversed polarity to the data lines of the liquid crystal display panel,
And the Nth pixel data converted using the first look-up table has higher luminance than the Nth pixel data converted using the second look-up table. The method according to claim 1,
The step (b)
Wherein the gamma curve of the Nth pixel data is converted from nonlinear to linear by converting the Nth pixel data from 8 bits to 10 bits using the first look-up table. 3. The method of claim 2,
The step (b)
Wherein the Nth pixel data is converted from 8 bits to 10 bits using the second look-up table, but the gamma curve of the Nth pixel data is maintained as it is. The method according to claim 1,
The step (a)
Assigning weights of different values to each of the input image data according to the gradation level of the data;
applying a polarity pattern of the default polarity control signal and a polarity pattern of the reverse polarity control signal to data having a highest weight for n (n is a positive integer) I-dot data, respectively;
Counting the number of positive polarity and the number of negative polarity of the data to which the default polarity control signal is applied to calculate a first positive polarity count result and a first negative polarity count result of the nth I dot data, Counting the number of positive polarity and the number of negative polarity of the data to calculate a second positive polarity count result and a second negative polarity count result of the nth I dot data;
Calculating a first cumulative count result for the n-th I-dot data by adding the difference between the first positive polarity count result and the first negative polarity count result to an n-1-th cumulative count value, Calculating a second cumulative count result for the n-th I-dot data by adding the difference between the polarity count result and the second negative polarity count result to the (n-1) -th cumulative count value; And
And comparing the first cumulative count result and the second cumulative count result to determine a degree of polarity balance of the input image data according to the comparison result. 5. The method of claim 4,
The step (a)
A polarity pattern of the polarity pattern of the default polarity control signal and a polarity pattern of the polarity pattern of the reverse polarity control signal reflecting the selected count result are selected as the polarity pattern of the polarity pattern of the default polarity control signal Selecting; And
And selecting a polarity pattern of the default polarity control signal if the first and second cumulative count results are the same. The method according to claim 1,
The step (c)
The first polarity control data indicating one of the n-th I dot and the second polarity control data indicating one of a polar pattern of a horizontal one-dot version and a polar pattern of a horizontal two- Defining a polarity pattern of the selected polarity control signal;
Transmitting the first and second polarity control data to the source drive ICs along with the nth I dot data through the data bus transmission lines through which the nth I dot data is transmitted; And
And reversing the horizontal polarity of the data voltages output to the data lines of the liquid crystal display panel by restoring the selected polarity control signal based on the first and second polarity control data in the source drive IC The polarity of the data voltage is controlled. A liquid crystal display panel in which data lines and gate lines cross each other;
The polarity pattern of the default polarity control signal and the polarity pattern of the reverse polarity control signal are selected by analyzing the degree of polarity balance of the input image data in I (I is any one of 3 to 18) (N is a natural number satisfying 1? L? Q and L is a natural number satisfying 1? L? P, p is the number of gate lines) The number of data lines) of the (N + 1) th pixel data is compared with the polarity of the (N + 1) th pixel data, and if the polarity of the Nth pixel data is the same as the polarity of the And converts the N-th pixel data using the second look-up table if the polarity of the N-th pixel data and the polarity of the N + 1-th pixel data are not identical A timing controller including a data compensator;
And a source driver IC for converting the converted pixel data into a positive / negative analog data voltage and inverting the polarity of the data voltage in the selected polarity pattern and outputting the reversed polarity to the data lines of the liquid crystal display panel,
And the Nth pixel data converted using the first look-up table has higher luminance than the Nth pixel data converted using the second look-up table. 8. The method of claim 7,
Wherein the data compensator comprises:
And converts the gamma curve of the Nth pixel data from nonlinear to linear by converting the Nth pixel data from 8 bits to 10 bits using the first look-up table. 9. The method of claim 8,
Wherein the data compensator comprises:
Wherein the second look-up table is used to convert the Nth pixel data from 8 bits to 10 bits, but the gamma curve of the Nth pixel data is maintained as it is. 8. The method of claim 7,
Wherein the fly-eye polarity selection unit comprises:
A weighting unit for assigning weights of different values to each of the input image data according to a gradation level of the data;
a polarity applying unit for applying the polarity pattern of the default polarity control signal and the polarity pattern of the reverse polarity control signal to the data having the highest weight for n (n is a positive integer) I-dot data, respectively;
Counting the number of positive polarity and the number of negative polarity of the data to which the default polarity control signal is applied to calculate a first positive polarity count result and a first negative polarity count result of the nth I dot data, A counter for counting a positive number and a negative number of data to calculate a second positive polarity count result and a second negative polarity count result of the nth I dot data;
Calculating a first cumulative count result for the n-th I-dot data by adding the difference between the first positive polarity count result and the first negative polarity count result to an n-1-th cumulative count value, A cumulative counter for adding a difference between the polarity count result and the second negative polarity count result to the (n-1) -th cumulative count value to calculate a second cumulative count result for the n-th I-dot data; And
And a polarity selector for comparing the first cumulative count result and the second cumulative count result and for determining a polarity balance of the input image data according to the comparison result. 11. The method of claim 10,
Wherein the polarity selector comprises:
A polarity pattern of the polarity pattern of the default polarity control signal and a polarity pattern of the polarity pattern of the reverse polarity control signal reflecting the selected count result are selected as the polarity pattern of the polarity pattern of the default polarity control signal And selects a polarity pattern of the default polarity control signal if the first and second cumulative count results are the same. 8. The method of claim 7,
The timing controller includes:
The first polarity control data indicating one of the n-th I dot and the second polarity control data indicating one of a polar pattern of a horizontal one-dot version and a polar pattern of a horizontal two- A data logic processor for defining a polarity pattern of the selected polarity control signal; And
And a data output unit for transmitting the first and second polarity control data to the source drive ICs together with the n-th I-dot data through the data bus transmission lines through which the n-th I-dot data is transmitted,
The source drive IC includes:
And reverses the horizontal polarity of the data voltages output to the data lines of the liquid crystal display panel by restoring the selected polarity control signal based on the first and second polarity control data. (a) analyzing a degree of polarity balance of input image data in I (I is any one of 3 to 18) dots, and comparing the polarity pattern of the default polarity control signal with the polarity pattern of the default polarity control signal in the I- Selecting one of a polarity pattern of an inverted polarity control signal generated as an inverted signal of the control signal;
(b) is a natural number satisfying L (L is a natural number satisfying 1? L? p, p is the number of gate lines in the display panel) (N + 1) -th pixel data, the polarity of the (N + 1) -th pixel data is equal to the polarity of the And adding the header data of the second logical value to the Nth pixel data when the polarity of the Nth pixel data and the polarity of the N + 1 pixel data are not the same, Outputting image data; And
(c) separating the converted image data into the header data and the image data, and then selecting one of a first positive / negative polarity gamma compensation voltage and a second positive / negative polarity gamma compensation voltage from the header data, And a second polarity / negative polarity analog data voltage in accordance with the selection signal, and converts the image data into either the first positive / negative polarity analog data voltage or the second positive / negative polarity analog data voltage according to the selection signal, Inverting the polarity of the data voltage and outputting the data voltage to the data lines of the liquid crystal display panel,
Wherein the first positive polarity / negative polarity analog data voltage has a higher luminance than the second positive / negative polarity analog data voltage in the same gray level. 14. The method of claim 13,
The step (c)
Generating a second positive / negative gamma reference voltage based on a first positive / negative gamma reference voltage and a second gamma curve based on a first gamma curve curve;
Negative gamma reference voltage to divide the first positive / negative gamma reference voltage to generate the first positive / negative gamma compensation voltages, and divide the second positive / negative gamma reference voltage to divide the second positive / Generating polarity gamma compensation voltages;
And outputs a first positive / negative gamma compensation voltage corresponding to a gray value of the input image data among the first positive / negative polarity gamma compensation voltages, and outputs the first positive / negative polarity gamma compensation voltages Outputting a second positive / negative gamma compensation voltage corresponding to a gray-level value of the image data to be input; And
And outputs the first positive / negative gamma compensation voltage when the selection signal of the first logic value is input, and outputs the second positive / negative gamma compensation voltage when the selection signal of the second logic value is input ≪ / RTI > further comprising the step of: controlling the polarity of the data voltage. 15. The method of claim 14,
The step (c)
The first polarity control data indicating one of the n-th I dot and the second polarity control data indicating one of a polar pattern of a horizontal one-dot version and a polar pattern of a horizontal two- Defining a polarity pattern of the selected polarity control signal;
Transmitting the first and second polarity control data to the source drive ICs along with the nth I dot data through the data bus transmission lines through which the nth I dot data is transmitted; And
And a second polarity control signal generating circuit for generating the polarity control signal based on the first and second polarity control data in the source drive IC and for outputting any one of the first positive / Or inverting the horizontal polarity of the data voltages outputted to the data lines of the liquid crystal display panel by outputting either one of the second positive polarity / negative polarity gamma compensation voltages. . 14. The method of claim 13,
The step (a)
Assigning weights of different values to each of the input image data according to the gradation level of the data;
applying a polarity pattern of the default polarity control signal and a polarity pattern of the reverse polarity control signal to data having a highest weight for n (n is a positive integer) I-dot data, respectively;
Counting the number of positive polarity and the number of negative polarity of the data to which the default polarity control signal is applied to calculate a first positive polarity count result and a first negative polarity count result of the nth I dot data, Counting the number of positive polarity and the number of negative polarity of the data to calculate a second positive polarity count result and a second negative polarity count result of the nth I dot data;
Calculating a first cumulative count result for the n-th I-dot data by adding the difference between the first positive polarity count result and the first negative polarity count result to an n-1-th cumulative count value, Calculating a second cumulative count result for the n-th I-dot data by adding the difference between the polarity count result and the second negative polarity count result to the (n-1) -th cumulative count value; And
And comparing the first cumulative count result and the second cumulative count result to determine a degree of polarity balance of the input image data according to the comparison result. 17. The method of claim 16,
The step (a)
A polarity pattern of the polarity pattern of the default polarity control signal and a polarity pattern of the polarity pattern of the reverse polarity control signal reflecting the selected count result are selected as the polarity pattern of the polarity pattern of the default polarity control signal Selecting; And
And selecting a polarity pattern of the default polarity control signal if the first and second cumulative count results are the same. A liquid crystal display panel in which data lines and gate lines cross each other;
The polarity pattern of the default polarity control signal and the polarity pattern of the reverse polarity control signal are selected by analyzing the degree of polarity balance of the input image data in I (I is any one of 3 to 18) (N is a natural number satisfying 1? L? Q and L is a natural number satisfying 1? L? P, p is the number of gate lines) (N + 1) -th pixel data, the polarity of the (N + 1) -th pixel data is equal to the polarity of the And adding the header data of the second logical value to the Nth pixel data when the polarity of the Nth pixel data and the polarity of the N + 1 pixel data are not the same, A data conversion unit for outputting image data; A timing controller including: And
And separates the converted image data into the header data and the image data, and then generates a selection signal for selecting either the first positive / negative polarity gamma compensation voltage and the second positive / negative polarity gamma compensation voltage from the header data, And converts the image data into either the first positive / negative polarity analog data voltage or the second positive / negative polarity analog data voltage according to the selection signal, and the polarity of the data voltage in the selected polarity pattern And outputting the inverted data to the data lines of the liquid crystal display panel,
Wherein the first positive polarity / negative polarity analog data voltage has a higher luminance than the second positive / negative polarity analog data voltage in the same gray level. 19. The method of claim 18,
The source drive IC includes:
A gamma reference voltage generating circuit for generating a second positive / negative gamma reference voltage based on a first positive / negative gamma reference voltage and a second gamma curve based on a first gamma curve curve;
Negative gamma reference voltage to divide the first positive / negative gamma reference voltage to generate the first positive / negative gamma compensation voltages, and divide the second positive / negative gamma reference voltage to divide the second positive / A voltage divider circuit for generating polarity gamma compensation voltages; And
And outputs a first positive / negative gamma compensation voltage corresponding to a gray value of the input image data among the first positive / negative polarity gamma compensation voltages, and outputs the first positive / negative polarity gamma compensation voltages And a second positive / negative gamma compensation voltage corresponding to a gray-level value of the image data to be input during the first positive / negative gamma compensation voltage And a third multiplexer for outputting a second positive / negative gamma compensation voltage when a selection signal of a second logic value is input to the liquid crystal display device. 20. The method of claim 19,
The timing controller includes:
The first polarity control data indicating one of the n-th I dot and the second polarity control data indicating one of a polar pattern of a horizontal one-dot version and a polar pattern of a horizontal two- A data logic processor for defining a polarity pattern of the selected polarity control signal; And
And a data output unit for transmitting the first and second polarity control data to the source drive ICs together with the n-th I-dot data through the data bus transmission lines through which the n-th I-dot data is transmitted,
The source drive IC includes:
An internal control signal generator for restoring the selected polarity control signal based on the first and second polarity control data; And
And outputs either one of the first positive / negative polarity gamma compensation voltages or the second polarity / negative polarity gamma compensation voltages according to the selected polarity control signal to the data lines of the liquid crystal display panel And inverting the horizontal polarity of the data voltages to be applied to the liquid crystal display panel. 19. The method of claim 18,
Wherein the fly-eye polarity selection unit comprises:
A weighting unit for assigning weights of different values to each of the input image data according to a gradation level of the data;
a polarity applying unit for applying the polarity pattern of the default polarity control signal and the polarity pattern of the reverse polarity control signal to the data having the highest weight for n (n is a positive integer) I-dot data, respectively;
Counting the number of positive polarity and the number of negative polarity of the data to which the default polarity control signal is applied to calculate a first positive polarity count result and a first negative polarity count result of the nth I dot data, A counter for counting a positive number and a negative number of data to calculate a second positive polarity count result and a second negative polarity count result of the nth I dot data;
Calculating a first cumulative count result for the n-th I-dot data by adding the difference between the first positive polarity count result and the first negative polarity count result to an n-1-th cumulative count value, A cumulative counter for adding a difference between the polarity count result and the second negative polarity count result to the (n-1) -th cumulative count value to calculate a second cumulative count result for the n-th I-dot data; And
And a polarity selector for comparing the first cumulative count result and the second cumulative count result and for determining a polarity balance of the input image data according to the comparison result. 22. The method of claim 21,
Wherein the polarity selector comprises:
A polarity pattern of the polarity pattern of the default polarity control signal and a polarity pattern of the polarity pattern of the reverse polarity control signal reflecting the selected count result are selected as the polarity pattern of the polarity pattern of the default polarity control signal And selects a polarity pattern of the default polarity control signal if the first and second cumulative count results are the same.

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