KR101777028B1 - Method of parameter extraction and system thereof - Google Patents

Abstract

A method executed by at least one processor includes the steps of: generating layout data of a chip including a transistor; Determining a thermal related parameter for the transistor based on the location within the layout data; Generating netlist data that includes column related parameters; Performing post-layout simulation based on netlist data; And verifying whether the post-layout simulation meets design specifications.

Description

[0001] METHOD OF PARAMETER EXTRACTION AND SYSTEM THEREOF [0002]

In the design flow for manufacturing semiconductor integrated circuits (ICs), various methods and electronic design automation tools have been included to set up the desired simulation environment. Several built-in device models and design rules are used to verify design capabilities such as function, power, operating time, and die size. In addition, different models with different parameter sets need to be provided to solve different applications. Of the model parameters, the thermal related parameters are utilized to simulate the influence of the heat source on device function and performance. Then, considering the thermal effect, a reasonable design margin is determined and reflected in the design IC. Thus, a functional error or performance degradation due to device heating is minimized in the device.

The aspects of the disclosure are best understood when read in conjunction with the accompanying drawings from the detailed description that follows in order to practice the invention. It is noted that according to standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may optionally be increased or decreased for clarity of discussion.
1 is a schematic diagram showing a design flow according to some embodiments.
2A and 2B are schematic diagrams of a semiconductor device according to some embodiments.
3 is a schematic diagram of a layout according to some embodiments.
4 is a schematic diagram of a layout according to some embodiments.
5 is a flow diagram of a simulation process in accordance with some embodiments.
6 is a flow diagram of a simulation process in accordance with some embodiments.
7 is a block diagram of a hardware system in accordance with some embodiments.

The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and devices are described below to simplify the present disclosure. Of course, these are merely examples, and are not intended to be limiting. For example, in the ensuing description, the formation of the first feature on or above the second feature may include an embodiment wherein the first and second features are formed in direct contact, and wherein the first and second features are directly May include embodiments in which additional features may be formed between the first and second features so as not to contact them. In addition, the present disclosure may repeat the reference numerals and / or symbols in various examples. Such an iteration is for the purposes of simplicity and is not meant to imply a relationship between the various embodiments and / or configurations discussed in and of itself.

Also, terms related to space, such as "under", "under", "under", "above", "above", etc., Can be used here for ease of explanation, to illustrate the relationship to the < RTI ID = 0.0 > The terms associated with space are intended to encompass different orientations of the device in use or in addition to the orientation shown in the figures. The device may be oriented otherwise (rotated 90 degrees or in another orientation of orientation), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

1 is a schematic diagram illustrating a design flow 100 in accordance with some embodiments. The design flow 100 employed to design a semiconductor chip utilizes one or more electronic design automation (EDA) tools to perform operations internally. Typically, a workstation or personal computer is used to execute the tool to accomplish the flow. The design flow 100 includes a system design stage 110, a logic design stage 120, a synthesis stage 130, a pre-layout simulation stage 140, a layout development stage 150, A post-layout simulation stage 160, and a post-layout simulation stage 170.

Initially, at system design stage 110, the system architecture for the chip of interest is provided with a high level description. At that stage, each function of the chip is determined by design specifications along with performance requirements. These functions are generally represented by a corresponding schematic functional module or block. Optimization or performance trade-offs can also be pursued to achieve design specifications at the right cost and power.

In the logic design stage 120, a functional module or block is described as a register transfer level (RTL) using a hardware description language. Language tools are usually available from commercial software, for example, Verilog or VHDL. A preliminary functional check is performed in the logic design stage 120 to verify that the implemented functionality complies with the specifications described in the system design stage 110. [

Subsequently, in the synthesis stage 130, a module in the RTL description is converted into netlist data in which a circuit structure, for example a logic gate and a register, is built in each functional module. In some embodiments, technically mapping these logic gates and registers to available cells in a standard cell library is performed. Netlist data is also provided at gate level to describe the functional relationship of the chip elements. In one embodiment, netlist data is converted from a gate level view to a transistor level view.

The gate-level netlist data is then verified in pre-layout simulation stage 140. During the verification process of the stage 140, if some of the functionality fails verification in the simulation, the design flow 100 may be temporarily stopped and returned to the stage 110 or 120 for further correction or correction. After the pre-layout simulation stage 140, the IC chip design passes the preliminary verification and completes the front-end design process. Thus, a back-end physical design process will follow.

In the layout development stage 150, a physical architecture representing the circuit determined during the front end process is implemented. Layout development includes batch operation and routing operations in succession, which allows the detailed structure and associated geometry of each component and element to be determined in the layout operation, and the interconnections between the different components are routed do. In addition, the placement operation includes determining where to place each IC chip component and circuit within a limited amount of space, and the routing operation determines the actual wiring connection of the connection line. Both operations of placement and routing are performed so as to satisfy design criteria check (design rule check (DRC)), for example, from a chip manufacturing facility, in order to meet manufacturing standards of the chip. After the layout development stage 150, placed and routed layout data is generated and a netlist with placement and routing data is generated accordingly.

In the parameter extraction stage 160, a layout parameter extraction (LPE) operation is performed to obtain layout dependent parameters such as parasitic resistance and parasitic capacitance arising from the developed layout. In some embodiments, lay out-versus-schematic (LVS) verification is performed to check the functional performance of the chip in terms of placed and routed netlists prior to the layout parameter extraction operation. Thus, the post layout netlist data is then generated, which contains the layout dependent parameters.

In the post-layout simulation stage 170, physical verification is performed by considering the parameters obtained in the previous stages. In this stage 170, a simulation of transistor level behavior is performed to check that the chip performs the desired function within the required system specification. In addition, post-layout simulations are performed to ensure that there are no electrical and lithographic problems in the chip fabrication process.

After the post-layout simulation stage 170, it is determined at stage 180 whether the post-layout netlist satisfies the design specification. If yes, then the circuit design is accepted at stage 190 and then terminated accordingly. However, if the post-layout simulation results are not appropriate, the design flow 100 will be looped back to the previous stage for functional or performance tuning. For example, the design flow 100 may be looped back to the layout development stage 150 where the layout is redeveloped to fix problems from the layout level. Alternatively, design flow 100 may return to an earlier stage; A system design stage 110 or a logic design stage 120 for reconfiguring a chip design if the problem can not be solved in the back end stage.

The design flow 100 shown in FIG. 1 is exemplary. The further stages of the stage or operation, the division of the stage, or the stage before, during or after the stage is still within the considered range of the present disclosure.

Referring again to the parameter extraction stage 160 of FIG. 1, the layout dependent parameters extracted based on the layout data determine the effect of the SPICE (Simulation Program with Integrated Circuit Emphasis) model in simulating chip operation. Of the parameters, the column-related parameters serve to provide information about the heat generated from each component of the chip, particularly in transistor level simulation. A phenomenon called the self-heating effect (SHE) is observed to model the heat generation mechanism. Therefore, a better knowledge of SHE will help to derive the heat-related parameters more accurately.

A typical heat source for an SHE for a device modeled in a chip is found to be the current flowing through an active device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), specifically its drain region. The degree of SHE will be proportional to the operating current or the level of its power. The heat accumulation due to SHE is believed to be more prominent in advanced semiconductor devices such as FinFETs (Fin-type FETs) or SOI FETs (Silicon-on-Insulator FETs). In addition, another heat source for the modeled element can be found to be its nearby active element. As a result, identification of thermal contributors is important for SHE modeling. Therefore, SHE will be better described as the thermal effect that occurs from both the modeled device itself and the neighboring devices.

In addition to the heat source, the analysis of the SHE reveals that the distance from the neighboring active elements can determine the actual thermal contribution in the modeled device. In addition, the material or structure used to connect adjacent elements will also lead to different heat transfer paths. For example, a structure that accommodates two adjacent FET elements within a common oxide diffusion (OD) region may require more heat than a discrete structure in which two FET elements are disposed in separate OD regions, . In other words, it is believed that the SHE is in a factor that includes the power level of the modeled device itself, the power level of the nearby device, the relative distance from that neighboring device, or layout layout for the device. Based on the discussion discussed above, the column-related parameters will depend on the layout and can be accurately obtained only after the layout is complete.

Also, with reference to the post-layout simulation stage 170, the completed post-layout simulation results include the SPICE model of each element in a simulator that analyzes SHE at different times when the heat source is powered on or off . Real-time power analysis is accomplished by projecting switch activity data (i.e., a profile of the device on-off state) over a time interval to the layout data. Thus, the design flow 100 is operated such that a thermal related parameter extraction operation and a dynamic simulator setup are implemented in stages 160 and 170, respectively. For this reason, more accurate simulation results will be obtained.

Conversely, SHE modeling in some existing design flows is performed by assuming a fixed number of heat sources during the design flow. Neighboring active elements sharing a common OD region are counted in a fixed number of heat sources regardless of their power values or relative distances. The static data for the heat source is usually determined by a look-up table based on the number of elements in each OD region. Furthermore, in some existing post-layout simulation methods, the simulator does not consider the real-time switching state of the heat source. Instead, the heat source is assumed to be powered on during the simulation period. Therefore, it turns out that the simulation results will reflect the actual SHE, not the geometric structure or time. For this reason, a longer design cycle time may be required, or the manufacturing cost may be increased.

In the following, various embodiments in accordance with the present disclosure will be provided. Referring to stage 140 of FIG. 1, pre-layout netlist data will be generated to serve as input for layout development after the pre-layout simulation operation is completed and passes verification, Lt; RTI ID = 0.0 > 5 < / RTI >

M214 D1 G1 S1 B1 nch_svt

M216 D2 G2 S2 B2 nch_svt

M224 D3 G3 S3 B3 nch_svt

M226 D4 G4 S4 B4 nch_svt

M228 D5 G5 S5 B5 nch_svt

Each row of exemplary netlist data having a similar syntax corresponds to each transistor. The technology for each transistor includes, but is not limited to, a heading that provides transistor labels M214 to M228. The four numbered data and the device model name (nch_svt) follow the transistor label and are sent to the other elements of each transistor through the terminals (the drain of D1, the gate of G1, the source of S1, the body of B1) The connections are identified by the same number. Next, a width identifier L2 and a length identifier L1 are provided. The default code 'u' is appended to represent length units. The exact element geometry and location corresponding to the above-described exemplary netlist will be generated in the layout development stage, as shown in Figures 2a and 2b below.

2A is a schematic diagram of a semiconductor device 210 according to some embodiments. The coordinates of the plane follow a coordinate system in which the arrows point in the X and Y directions as shown. The semiconductor device 210 may be a FinFET device. The semiconductor device 210 also includes an OD region 212, a first gate region 214 and a second gate region 216 in accordance with the specifications described in the pre-layout netlist. In this embodiment, semiconductor device 210 is created to implement two transistors of pre-layout Netlist data, such as those named M214 and M216, as discussed above. Similarly, the other three transistors recognized in the netlist data will be generated in the layout file in the same manner.

The OD region 212 shown in two dimensions may correspond to the fin structure of the FinFET device 210. [ An OD region 212 having an OD length L1 defined along the X direction and an OD width W1 defined along the Y direction is generated. The first gate region 214 and the second gate region 216 correspond to the first transistor 214 and the second transistor 216, respectively. For convenience, the first gate region 214 and the second gate region 216 represent a first transistor 214 and a second transistor 216, respectively. In addition, in the layout of the semiconductor device 210, the first gate region 214 and the second gate region 216 are configured in the OD region 212. This visual information on the device configuration facilitates subsequent thermal-related parameter extraction operations.

2B is a schematic diagram of a semiconductor device 220 according to some embodiments. The semiconductor device 220 includes an OD region 222 having an OD length L2 and an OD width W2. The semiconductor device 220 also includes a first gate region 224, a second gate region 226 and a third gate region 228 for implementing transistors M224, M226, and M228, respectively. Semiconductor device 220 includes a FinFET structure in which three transistor elements are recognized by respective gate regions.

In some embodiments, transistors 214, 216, 224, 226, 228 may be designed with different OD configurations for different applications and limitations. For example, five transistors may be implemented with five separate OD regions or a single shared OD region. In any case, the implemented chip function may be identical to the configuration of the two shared OD regions shown in Figs. 2A and 2B. However, the subsequent SHE analysis will be significantly different due to the different OD composition.

The geometric information (L1, W1, L2, W2) of the transistors shown in Figures 2a and 2b is appended to the original netlist data, as given in the other exemplary netlist data below.

M214 D1 G1 S1 B1 nch_svt W1 = 2u L1 = 0.5u

M216 D2 G2 S2 B2 nch_svt W1 = 2u L1 = 0.5u

M224 D3 G3 S3 B3 nch_svt W2 = 2u L2 = 0.5u

M226 D4 G4 S4 B4 nch_svt W2 = 2u L2 = 0.5u

M228 D5 G5 S5 B5 nch_svt W2 = 2u L2 = 0.5u

3 is a schematic diagram of layout data 300 in accordance with some embodiments. The layout data 300 is measured in an orthogonal coordinate system having x-axis and y-axis. In addition, the origin identifier C0 is specified in the layout data 300, and is used as a reference in the layout data 300. [ The actual position of the origin identifier C0 can be adjusted. The origin identifier C0 is a global identifier. The coordinates of the global identifier are fixed in the layout development process and remain unchanged with respect to the layout configuration. Layout data 300 includes the semiconductor devices 210 and 220 discussed in Figures 2A and 2B, respectively.

The position of the OD area 212 is specified by the position identifier C2 at the bottom left corner. In one embodiment, the location identifier C2 is a global type identifier for the origin identifier CO. For example, the identifier C2 stores coordinates of (x05, y10). As a result, when the dimension of the OD region 212 is determined, the boundary of the OD region 212 can be obtained accordingly. Other locations, such as the midpoints or other corners of the OD region 212, may instead be specified instead, even though the location identifier C2 is used to relate to the OD region 212 in this embodiment.

The position of the transistors 214 and 216 for the OD region 212 is then specified. In one embodiment, the coordinate of the center of transistor 214 is M1g = (x10, y10). Similarly, the coordinate of the center of the transistor 216 is M1g = (x20, y20). Based on the location of transistors 214 and 216, the distance between transistor 214 and transistor 216 can be obtained. In addition, the distance between any one of transistor 214 or transistor 216 and another component can also be obtained. Other locations, such as the coordinates of the lower point (x20, y05) or the upper point (x20, y35) relative to the transistor 214, may be used instead of this location, even though the geometric center is used as the location identifier of the transistors 214, Lt; / RTI > The global location based information of the transistor is updated and appended to the post-layout netlist data as illustrated below (repeated parameters including terminal, device model name, and geometry information are omitted for simplicity).

M214 devx = x10, devy = y20

M216 devx = x20, devy = y20

M224 devx = x30, devy = y20

M226 devx = x40, devy = y20

M228 devx = x50, devy = y20

Layout parameters for describing the transistors 214 and 216 are then obtained which may include the identity of the OD region 212 and its location and the identity and corresponding location of the OD region 222. [ In one embodiment, for the OD region 212, the identity representation ODid = 212 is specified for both transistors 214 and 216. Similarly, for the OD region 222, the identity representation ODid = 222 is specified for the transistors 224, 226, and 228. The information on the shared OD region will facilitate SHE analysis in identifying the critical heat source for a particular transistor, in addition to the relative distance between the transistors. The location-based and OD-area-based parameters of the transistor are shown as illustrated below (repeated parameters are omitted for simplicity).

M214 devx = x10, devy = y20 ODid = 212

M216 devx = x20, devy = y20 ODid = 212

M224 devx = x30, devy = y20 ODid = 222

M226 devx = x40, devy = y20 ODid = 222

M228 devx = x50, devy = y20 ODid = 222

In one embodiment, the location information for the identifier is defined as relative coordinates. In one embodiment, the location of the OD region 212 for the identifier C2 is recorded in a local representation. For example, the transistor identifier M1 may store the coordinates M1r = (x10-x05, y20-y10). Similarly, the transistor identifier M2 may store coordinates M2r = (x20-x05, y20-y10).

The localized location information of the transistors 214 and 216 is updated and appended to the post-layout netlist data as illustrated below (repeated parameters are omitted for simplicity).

M214 devx = x10-x05, devy = y20-y10 ODid = 212

M216 devx = x20-x05, devy = y20-y10 ODid = 212

Under localized settings of coordinates M1r and M2r, positional information about the heat source for transistor 214 is limited to sharing OD region 212. [ As a result, the computational burden of global search for all heat sources is significantly reduced, especially when large layouts are evaluated for millions of transistors therein. In one embodiment, the local location coordinates of each element may be derived by a global type identifier in the post-layout simulation stage 170, or vice versa.

In one embodiment, the location information is further simplified as a serial index of a group of transistors sharing a common OD region 212. [ The indexing rules are predetermined, so that the transistors can be indexed from the leftmost or rightmost. For example, the transistors 214 and 216 are identified with serial numbers 1 and 2, respectively, for the OD region 212. Therefore, the location information for SHE analysis is further reduced. In the following, an exemplary netlist representing the serial location information is provided.

M214 devid = 1 ODid = 212

M216 devid = 2 ODid = 212

M224 devid = 1 ODid = 222

M226 devid = 2 ODid = 222

M228 devid = 3 ODid = 222

The exact SHE simulation for a particular device requires its location information and its associated OD identity. Referring to the OD regions 212 and 222, although the transistors 214 and 216 may be located at a relatively shorter distance relative to the transistor 228 than the transistor 228, since they are arranged in different OD regions, Can be quite different. In an existing approach for simulating SHE, one terminal of a total device count is provided via a predetermined look-up table, which is set to three for the case of the OD region 222. [ In this case, the number of logic elements is provided instead of the actual element geometry information. In addition, when the SHE simulation is performed, the active state of all the transistors is set to be enabled with the maximum power. As a result, post-layout simulations using existing methods can not reflect actual device activity and associated power distribution. For this reason, pessimistic evaluation results are inevitable and may result in more repetition of layout tuning.

4 is a schematic diagram of layout data 400 in accordance with some embodiments. The layout data 400 is composed of two overlapping layers with corresponding components or elements. Since the layout data 400 is shown in the top view in Fig. 4, the two layers may not be visible separately. In this embodiment, the layout data 400 includes an exemplary semiconductor device 410 in the first layer. 2A and 2B, the semiconductor device 410 includes an OD region 412 and five transistor elements 414, 416, 418, 420, and 422. As shown in FIG. Semiconductor device 410 is defined by an OD region 412 shared by transistors 414, 416, 418, 420, 422.

The layout data 400 also includes a second layer that serves as a marker layer (not shown separately) and includes a first marker region 415, a second marker region 425, and a third marker region 435, Are arranged corresponding to the transistors 414, 420, and 422, respectively. The first marker region 415, the second marker region 425 and the third marker region 435 are provided with the marker layer for the purpose of obtaining the heat-related parameter, unlike the first layer and the associated semiconductor element 410 , And thus may not be included in the post-layout data.

The marker regions 415, 425, and 435 are identified in the individual marker layers of the layout data 400. In addition, the marker regions 415, 425, and 435 in the layout data 400 can be used to label the primary heat source to facilitate extraction of the heat related parameters. The criteria for determining the marker region may include, but are not limited to, the order of the operating power level for the transistor, the location of the transistor, transistor configuration, simulation accuracy requirements, and system calculation resources.

Assuming that the gate regions in the OD region are arranged in parallel, the search distance Ds is defined as the maximum device count of the heat source for one side of the transistor of interest. Referring to FIG. 4, gate regions for five transistors are arranged in parallel along the Y-axis. In this embodiment, the search distance Ds for the OD region 412 is set to two. This means that the search range for a significant heat source of a transistor (e.g., 416) is the sum of two neighboring elements to the left (only transistor 414 is counted), two adjacent elements to the right (transistors 418 and 420) The search distance Ds is a predetermined value and remains constant during the parameter extraction operation. In another embodiment, the search distance Ds may be determined by the chip design limit < RTI ID = 0.0 > And may vary in different OD regions.

Next, the number Nt of heat-related elements for the transistor is determined by counting the number of transistors having a marker layer within the search distance Ds. Taking transistor 416 as an example, the test of FIG. 4 reveals that only transistors 414 and 420 within the search distance Ds have a marker layer. For this reason, the number of column-related elements Nt is 2 and Nt = 2. Similarly, the Nt value is determined for Nt = 1, Nt = 3, Nt = 2 and Nt = 2 for transistors 414, 418, 420 and 422, respectively. An exemplary netlist representing the number of simplified thermal related elements is provided below.

M414 Nt = 1

M416 Nt = 2

M418 Nt = 3

M420 Nt = 2

M422 Nt = 2

The updated post-layout netlist data is then provided and delivered to the simulation tool. In the conventional method, a column-related parameter is provided while the thermal parameter value of the transistor in the common OD area is determined to be the same regardless of its power value and relative position. In contrast, in the present embodiment, the number of heat sources is considered to be fixed and its actual activity data is set to be enabled during chip operation. As a result, the computational complexity for analyzing the SHE via the parameter Nt is further reduced compared to coordinate-based thermal parameters such as devx, devy, and ODid. In addition, even if simplified, the parameter Nt is determined by considering the position of the element and the corresponding power value. Therefore, since the Nt values of neighboring transistors sharing the same OD region are different, the heat related parameter Nt is still effective for SHE modeling.

The simulation tool is configured to recognize the marker region with each transistor overlapping in its lower portion and to convert the marker region to the SHE parameter, not the physical layer within the chip. In this embodiment, the marker regions are arranged in a rectangular shape and are arranged to cover the respective transistors on the layout data 400. [ However, other configurations for the marker area, for example different associative approaches to different shaped marker areas or transistors, are within the contemplated scope of this disclosure.

5 is a flow diagram of a semiconductor design process 500 in accordance with some embodiments.

At act 502, a design specification for the chip is received. At operation 504, pre-layout netlist data for a chip comprising a plurality of transistors is generated. Next, at operation 506, a pre-layout simulation is performed to verify that the pre-layout netlist conforms to the functionality required by the design specification.

At operation 508, layout data for a chip comprising a plurality of transistors is generated in response to the successful pre-layout simulation verification result. Layout data is generated through placement of elements such as transistors, OD regions, and other elements. Routing operations are also performed to provide interconnection between the devices.

The design process then proceeds to an LVS comparison at operation 510 where the post-layout schematic is compared against the pre-layout netlist data to ensure that the layout data according to the result conforms to the design rules.

At operation 512, a column-related parameter for the transistor in the layout data is determined based on its location information. The column-related parameters are determined based on the power level of the transistor, the position of the transistor, or whether the transistors share a common OD region.

In one embodiment, the layout data includes an OD region shared by the transistors, and the column-related parameters include a grouping identifier based on the OD region and a serial number corresponding to each transistor. In one embodiment, the column related parameters include coordinates. The coordinates may be a global type relative to the reference coordinate system in the layout data or a local type relative to the OD region.

In one embodiment, the layout data further comprises a marker layer in which a marker region corresponding to one of the transistors is created. For example, a marker region is created based on the rank of the transistor's power level or position. The number of heat related elements is determined based on the marker area and the search distance. In addition, a heat related parameter is determined based on whether or not the transistors share a common OD region.

At operation 514, post-layout netlist data is generated that includes the column-related parameters. Then, at operation 516, post-layout simulation is performed using enhanced netlist data. In one embodiment, a post-layout simulation is performed based on the instantaneous power level and the thermal related parameters of the transistor.

At operation 518, it is determined whether the verification result for the pre-layout netlist data satisfies the design specification. If the result is "yes ", then the circuit design is accepted at operation 520 and the design ends. Conversely, if the simulation result fails the design specification, the design loops back to operation 508 to redevelop the layout data or to operation 504 to modify the pre-layout netlist data.

6 is a flow diagram of a semiconductor design process 600 in accordance with some embodiments. Operations 602 through 608 shown in FIG. 6 follow similar steps in operations 502 through 508 shown in FIG. 5, and therefore the details are omitted for simplicity.

Then, in response to the successful verification of the pre-layout simulation, at operation 609, a marker layer having a marker region corresponding to one of the transistors is included in the layout data. The marker layer is created to identify the transistor as an important heat source. In one embodiment, the marker region is generated based on the rank of the transistor's power level or position.

Then, at operation 610, similar to operation 510 shown in FIG. 5, an LVS comparison process is performed.

Then, at act 612, the number of column related elements for each transistor is determined based on the layout data. The column-related parameters are generated based on the grouping parameter and the neighbor distance. In one embodiment, the thermal related elements are determined based on the marker region and the search distance.

Next, at operation 614, post-layout data is generated that includes the number of column-related elements. Operations 616 through 620 are then performed similar to operations 516 through 520 shown in Fig.

7 is a block diagram of a system 70 for placement and routing in accordance with some embodiments. 7, the system 70 includes a processor 71, a network interface 73, an input / output (I / O) device 75, a storage 77, a memory 78 and a bus 79 . The bus 79 couples the network interface 73, the I / O device 75, the storage 77 and the memory 78 to the processor 71.

The processor 71 is configured to execute program instructions including a tool configured to perform the method described and illustrated with reference to Fig. In addition, the tool is configured to perform a wiring routing method as described and illustrated with reference to Figs. Thus, the tool is configured to perform the following steps: providing a design specification, generating a netlist of circuits, performing a pre-layout simulation, generating a layout, performing a LVS, grouping a plurality of transistors, Generate parameter or column related parameters, generate enhanced netlist by including parameters, perform post-layout simulation, and verify post-layout simulation results.

The network interface 73 is configured to access data that is accessed by program instructions and program instructions stored remotely via a network (not shown).

The I / O device 75 includes an input device and an output device configured to enable user interaction with the system 70. In some embodiments, the input device includes, for example, a keyboard, a mouse, and other devices. In addition, the output device includes, for example, a display, a printer, and other devices.

The storage device 77 is configured to store program instructions and data accessed by program instructions. In some embodiments, the storage device 77 includes, for example, a magnetic disk and an optical disk.

Memory 78 is configured to store program instructions executed by processor 71 and data accessed by program instructions. In some embodiments, memory 78 may include random access memory (RAM) and / or some other volatile storage and / or read only memory (ROM) and / or some other non- Storage device.

In some embodiments, a method performed by at least one processor is provided. In the method, layout data of a chip including a transistor is provided by at least one processor. A thermal related parameter for the transistor is determined based on its location in the layout data. Netlist data including the column related parameters are generated by at least one processor. A post-layout simulation is generated by at least one processor based on the netlist data. The method also verifies whether the post-layout simulation meets design specifications.

In some embodiments, a method performed by at least one processor is provided. Layout data of a chip including a transistor is generated by at least one processor. A marker layer having a marker region corresponding to one of the transistors is included in the layout data by at least one processor. Based on the layout data, the number of heat related elements for each of the transistors is determined by at least one processor. Netlist data including the column related parameters are generated by at least one processor. The post-layout simulation is performed by at least one processor based on the netlist data, and it is verified whether the post-layout simulation satisfies the design specification.

In some embodiments, a system is provided that includes one or more programs that include one or more processors and instructions. Instructions, when executed by one or more processors, cause the system to generate layout data for a chip comprising transistors by at least one processor; Determine, based on the layout data, the thermal related parameters for the transistor by at least one processor; Cause netlist data including column related parameters to be generated by at least one processor; Perform post-layout simulation based on netlist data by at least one processor; And verify whether the post-layout simulation meets design specifications.

The foregoing is a summary of features of various embodiments to enable those of ordinary skill in the art to better understand aspects of the disclosure. Those of ordinary skill in the art will readily appreciate that the present disclosure can readily be utilized as a basis for designing or modifying other processes and structures to accomplish the same objectives of the embodiments disclosed herein and to achieve the same advantages. . It will also be understood by those skilled in the art that such equivalent constructions may be made without departing from the spirit and scope of the present disclosure and that various changes, substitutions, and alterations may be made herein without departing from the spirit and scope of the disclosure It should be understood.

Claims (10)

A method performed by at least one processor,
Generating layout data of a chip including a transistor;
Determining a thermal related parameter for the transistor based on the position of the transistor in the layout data;
Generating netlist data including the column related parameters;
Performing a post-layout simulation based on the netlist data; And
Verifying whether the post-layout simulation meets a design specification
Lt; / RTI >
Wherein performing the post-layout simulation comprises performing the post-layout simulation based on an instant power level and a thermal related parameter of the transistor, wherein the post-layout simulation is performed by at least one processor Way. delete The method according to claim 1,
The step of determining the thermal related parameter comprises determining the thermal related parameter based on the power level of the transistor, the position of the transistor, or whether the transistor shares a common oxide diffusion (OD) region The method comprising the steps of: The method according to claim 1,
Wherein the layout data includes an oxide diffusion (OD) region shared by the transistor, the column related parameter including a grouping identifier based on the OD region and a serial number corresponding to each transistor Gt; is performed by at least one processor. The method according to claim 1,
Wherein the thermal related parameter comprises coordinates. ≪ Desc / Clms Page number 17 > 6. The method of claim 5,
Wherein the coordinates are global, relative to a reference coordinate in the layout data. 6. The method of claim 5,
Wherein the layout data further comprises an oxide diffusion (OD) region,
Wherein the method further comprises a grouping identifier for the transistor based on the layout data. The method according to claim 1,
Wherein generating the layout data further comprises generating a marker region on a marker layer of the layout data corresponding to one of the transistors. A method performed by at least one processor,
Generating layout data of a chip including a transistor;
Including a marker layer having a marker region corresponding to one of the transistors in the layout data;
Determining a number of thermal related elements for each of the transistors based on the layout data;
Generating netlist data including the number of heat related elements;
Performing a post-layout simulation based on the netlist data; And
Verifying whether the post-layout simulation meets a design specification
Lt; / RTI >
Wherein the number of heat related elements is determined based on the marker region and the search distance. A system comprising one or more processors and one or more programs,
Wherein the at least one program comprises an instruction,
Wherein the instructions, when executed by the one or more processors,
To generate layout data of a chip including a transistor;
Determine a thermal related parameter for the transistor based on the layout data;
Generate netlist data including the column related parameters;
Performing a post-layout simulation based on the netlist data; And,
Verifying whether the post-layout simulation satisfies the design specification,
Wherein the post-layout simulation is performed based on a thermal related parameter of the transistor and an instant power level.
A system comprising one or more processors and one or more programs.

Images