KR102622415B1 - Standard cell design system, standard cell design optimization operation thereof, and semiconductor design system - Google Patents

Abstract

The standard cell design system according to an embodiment of the present invention is a control engine configured to determine planar parameters and vertical parameters for the target standard cell, and to generate a three-dimensional structure for the target standard cell based on the planar parameters and vertical parameters. A three-dimensional structure generation engine configured, an extraction engine configured to extract a standard cell model for a target standard cell from the three-dimensional structure, an evaluation engine configured to perform a plurality of evaluation operations based on the standard cell model, and results of the plurality of evaluation operations. It includes an automatic optimization engine configured to adjust the planar parameters and vertical parameters based on the parameters. The automatic optimization engine adjusts the planar parameters and vertical parameters based on a first machine learning algorithm.

Description

Standard cell design system, standard cell design optimization method thereof, and semiconductor design system {STANDARD CELL DESIGN SYSTEM, STANDARD CELL DESIGN OPTIMIZATION OPERATION THEREOF, AND SEMICONDUCTOR DESIGN SYSTEM}

The present invention relates to semiconductor devices, and more particularly to standard cell design systems, standard cell design optimization methods thereof, and semiconductor design systems.

Semiconductor integrated circuits are manufactured based on layout. The process of creating the layout of a semiconductor integrated circuit may include various processes. For example, the process of creating the layout of a semiconductor integrated circuit may include a placement process of placing semiconductor elements such as transistors in the layout, and a routing process of connecting (or routing) the semiconductor elements in the layout. there is.

As an example, semiconductor devices such as transistors may be provided in the form of a standard cell. A standard cell may be a logic element or semiconductor device that has a predetermined shape based on a specific manufacturing process. A standard cell can be predetermined through various methods. However, recently, as the manufacturing process of semiconductor integrated circuits has become more refined and semiconductor manufacturing technology has developed, various studies are being conducted to discover standard cells or next-generation standard cells optimized in the miniaturized process.

The purpose of the present invention is to provide a standard cell system with reduced optimization time for standard cells and a method of operating the same.

A standard cell design system according to an embodiment of the present invention includes a control engine configured to determine planar parameters and vertical parameters for a target standard cell, a three-dimensional structure for the target standard cell based on the planar parameters and the vertical parameters. A three-dimensional structure generation engine configured to generate, an extraction engine configured to extract a standard cell model for the target standard cell from the three-dimensional structure, an evaluation engine configured to perform a plurality of evaluation operations based on the standard cell model, and An automatic optimization engine configured to adjust the planar parameters and the vertical parameters based on results of the plurality of evaluation operations, wherein the automatic optimization engine adjusts the planar parameters and the vertical parameters based on a machine learning algorithm. .

The standard cell design optimization method of the standard cell design system according to an embodiment of the present invention includes determining planar parameters and vertical parameters for a target standard cell, and determining the planar parameters and vertical parameters to the target standard cell. generating a three-dimensional structure, extracting a standard cell model from the three-dimensional structure, performing a plurality of evaluation operations on the target standard cell based on the standard cell model, and performing a plurality of evaluation operations on the target standard cell based on the standard cell model. determining whether the results each satisfy a plurality of reference values, and when the results of the plurality of evaluation operations each do not satisfy the plurality of reference values, the determined planar parameters, the determined vertical parameters, and the plurality of evaluation operations. Readjust the planar parameters and the vertical parameters based on the learning model updated according to the results, regenerate the three-dimensional structure based on the readjusted planar parameters and the readjusted vertical parameters, and regenerate Re-extracting the standard cell model based on the three-dimensional structure, and re-performing the plurality of evaluation operations based on the re-extracted standard cell model, wherein the learning model includes the determined plane parameters, the updated based on the determined vertical parameters and the results of the plurality of evaluation operations.

A semiconductor design system according to an embodiment of the present invention includes a standard cell design system configured to optimize planar parameters and vertical parameters for a plurality of standard cells based on a first machine learning algorithm, the optimized planar parameters, and the optimized planar parameters. A standard cell library configured to generate optimized standard cell information for each of the plurality of standard cells based on vertical parameters, and generate a block layout for a target semiconductor device based on the optimized standard cell information from the standard cell library. It includes a block design system configured to:

An optimization system according to an embodiment of the present invention includes a processor and a memory including instructions executable by the processor, wherein the processor determines planar parameters and vertical parameters for a target standard cell by executing the instructions, and , generate a three-dimensional structure for the target standard cell based on the planar parameters and the vertical parameters, extract a standard cell model from the three-dimensional structure, and generate a three-dimensional structure for the target standard cell based on the standard cell model. configured to perform a plurality of evaluation operations and adjust the planar parameters and the vertical parameters based on results of the plurality of evaluation operations, wherein the processor adjusts the planar parameters and the vertical parameters based on a first machine learning algorithm. It is further configured to adjust parameters.

According to an embodiment of the present invention, since the optimization operation for the standard cell is performed based on a machine learning algorithm, the optimization time for the standard cell design is reduced.

1 is a block diagram showing a semiconductor design system according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating the standard cell design system of FIG. 1.
FIG. 3 is a flowchart showing an automatic optimization operation for a target standard cell of the standard cell design system of FIG. 2.
4A and 4B are diagrams showing an example plan layout of a target standard cell.
Figure 5 is a graph to explain the mesh size of the standard cell model.
Figure 6 is a diagram for explaining the accuracy of standard cell model evaluation according to an embodiment of the present invention.
Figure 7 is a block diagram exemplarily showing an evaluation engine according to an embodiment of the present invention.
Figure 8 is a flowchart showing the operation of the evaluation engine of Figure 7.
FIG. 9 is a diagram illustrating the automatic optimization engine of FIG. 2.
Figures 10a and 10b are diagrams for explaining the operation of the optimization engine.
FIG. 11 is an exemplary diagram for explaining the block design system of FIG. 1.
Figure 12 is a block diagram illustrating a computing device associated with a semiconductor design system according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention.

As used in the detailed description or the accompanying drawings, terms such as “unit,” “engine,” “tool,” “system,” etc. refer to a hardware component configured to perform the presented function. , software configuration, or a combination thereof. As an example, software may include machine code, firmware, embedded code, and application software, and hardware components may include electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, It may include a microelectromechanical system (MEMS), a passive element, or a combination thereof, but the scope of the present invention is not limited thereto.

1 is a block diagram showing a semiconductor design system according to an embodiment of the present invention. Referring to FIG. 1 , the semiconductor design system 10 may include a standard cell level design system 100, a standard cell library 200, and a block level design system 300. In an exemplary embodiment, the standard cell-level design system 100 and the block-level design system 300 may be a system based on Design Technology Co-Optimization (DTCO). DTCO can refer to a system or tool that optimizes standard cells used in the semiconductor design process or optimizes block-level layout using standard cells. The term “design system” used below may refer to a system or tool based on DTCO.

The standard cell level design system 100 (hereinafter referred to as “standard cell design system”) is optimized standard cell information (OSI; Optimized STC Information) based on various information such as semiconductor process conditions, standard cell layout information, etc. ) can be created. Optimized standard cell information (OSI) is based on optimized semiconductor process conditions and layout of standard cells under various conditions (e.g. Performance, Power, Area, Yield (PPAY), etc.). It may contain information about

Hereinafter, the term optimization refers to various parameters such that various conditions such as performance, power, area, or yield of the target standard cell satisfy predetermined standards. This may mean adjusting parameters (e.g., layout of standard cells, process conditions, standard cell composition materials, etc.). For example, the optimization operation is performed in the direction of improving performance, reducing power consumption, reducing area, and increasing yield, and various parameters. It can refer to the action of adjusting things.

In an exemplary embodiment, the standard cell design system 100 may simulate a 3-dimensional structure reflecting a litho contour based on an optical proximity correction (OPC) model of process conditions. The standard cell design system 100 can extract a standard cell model from a simulated three-dimensional structure. The standard cell design system 100 can perform PPAY (Performance, Power, Area, and Yeild) evaluation on the extracted standard cell model. The standard cell design system 100 can optimize various process conditions and layouts for standard cells based on evaluation results.

In an exemplary embodiment, the standard cell design system 100 may repeatedly perform the above-described operations to generate optimized standard cell information (OSI). In an example embodiment, the standard cell design system 100 may perform the above-described optimization operation based on a machine learning algorithm. In an exemplary embodiment, the standard cell design system 100 may repeatedly perform the above-described operations to create or update a learning model for performing an optimization operation. The configuration of the standard cell design system 100 and optimization operations based on machine learning algorithms are described in more detail with reference to the drawings below.

Based on optimized standard cell information (OSI), a standard cell library 200 can be created. The standard cell library 200 may include information on various standard cells used under specific process conditions.

The block-level design system 300 (hereinafter referred to as “block design system”) can generate a block layout (BLK LAY) for a semiconductor device based on the standard cell library 200. For example, the BLK design system 300 uses standard cell information stored in the standard cell library 200 to place various standard cells and wiring to connect the various standard cells to create a block layout (BLK LAY). It can be configured.

At this time, the BLK design system 300 can optimize the block layout (BLK LAY). For example, the BLK design system 300 considers the local layout effect (LLE), the self-heating effect (SHE), and the performance, power, area, and yield (PPAY; Performance-Power, Area) of the semiconductor device. , and Yield) can be created to optimize the block layout (BLK LAY). In an exemplary embodiment, various types of semiconductor devices (e.g., Application Processor (AP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), and integrated circuits, or memory devices such as flash memory, dynamic random access memory (DRAM), etc.) may be manufactured.

FIG. 2 is a block diagram illustrating the standard cell design system of FIG. 1. 1 and 2, the standard cell design system 100 includes a control engine 110, a 3D structure generation engine 120, an extraction engine 130, an evaluation engine 140, and an automatic optimization engine 150. ) may include.

The control engine 110 may determine a standard cell to be optimized among various standard cells as a target standard cell and adjust a plurality of parameters (Xs) for the determined target standard cell. The plurality of parameters (Xs) may include planar parameters and vertical parameters for the target standard cell.

For example, a standard cell refers to a semiconductor device (or logic device) whose process conditions and layout are predetermined to improve the design speed of a semiconductor integrated circuit. Standard cells can be used to manufacture or implement various semiconductor devices (or logic devices) such as inverters, 2-input NAND gates, 2-input NOR gates, flip-flops, SRAM, AIO (AND-INVERTER-OR) gates, etc. You can. A standard cell may include one or more transistors or semiconductor devices. The target standard cell may indicate a standard cell for a logic element to be optimized by the standard cell design system 100. For example, when optimization is performed for an inverter, the target standard cell optimized by the standard cell design system 100 may be a standard cell corresponding to the inverter.

In an example embodiment, the planar parameters may indicate the planar layout or various information related to the planar layout for the target standard cell. For example, when the target standard cell is an inverter, the target standard cell may include one PMOS transistor and one NMOS transistor. In this case, the plan layout for the target standard cell may refer to information about the planar arrangement of the PMOS transistor and NMOS transistor on the semiconductor wafer, the arrangement of wiring for connecting the PMOS transistor and NMOS transistor, etc. Alternatively, the plan layout may include information about the individual sizes, arrangement spacing, etc. of various elements (eg, gate electrode, gate contact, active area, etc.) included in each transistor.

That is, the plane parameters are the size, distance between elements, and configuration of the semiconductor elements or various elements (e.g., gate electrode, gate contact, source contact, drain contact, active area, etc.) in the target standard cell. It may include two-dimensional information about their locations, etc.

In an example embodiment, a vertical parameter may indicate various process information about a target standard cell. For example, a target standard cell can be created based on various process information. Various process information includes the process scale of the target standard cell (e.g., 14 nm, 10 nm, 7 nm, etc.), the transistor structure of the target standard cell (e.g., planar transistor structure, FinFET structure, or next-generation semiconductor structure, etc.), and the target standard. It may include information required to manufacture the target standard cell, such as the composition and material of the cell's transistor. Depending on the above-described process information, the shape, structure, or composition of the transistor included in the target standard cell may be changed, and accordingly, the evaluation results for the target standard cell (e.g., PPAY; Performance, Power, Area , and Yield) may change.

In an example embodiment, various information about planar parameters or vertical parameters may be provided from a separate database (not shown). A separate database can be configured to store and manage various information according to various process conditions or types of standard cells.

The 3D structure generation engine 120 generates a 3D structure (3D-STR) for the target standard cell based on a plurality of parameters (Xs) (including planar parameters and vertical parameters) determined from the control engine 110. You can create (or simulate) a 3-dimensional structure. For example, the 3D structure generation engine 120 may automatically generate a 3D structure through parameterization of a plurality of parameters (Xs). In an exemplary embodiment, the 3D structure generation engine 120 may include any one of various emulators (e.g., Synopsys Process Exploere ^TM , Conventor SEMulatore3D ^TM, etc.), and may use the various emulators to generate a target standard cell. You can create a three-dimensional structure (3D-STR) for . In an exemplary embodiment, the 3D structure may be a full-3D FEOL/MOL/BEOL structure to which MTS and process assumption (PA) are applied.

In an exemplary embodiment, the 3D structure generation engine 120 may apply a litho contour based on an optical proximity correction model (OPC model) to a 3D structure (3D-STR). For example, a three-dimensional structure (3D-STR) may be created in an ideal shape (i.e., a shape in which edge areas are orthogonal). However, due to various physical phenomena in the actual semiconductor manufacturing process, the actually manufactured standard cell may differ from the ideal shape. To correct these structural differences, the OPC model can be applied in the semiconductor manufacturing process. The 3D structure generation engine 120 according to the present invention can generate a 3D structure (3D-STR) having a shape similar to an actually manufactured standard cell using a risocontour based on the above-described OPC model. The three-dimensional structure (3D-STR) to which litho contour is applied is explained in more detail with reference to FIGS. 4A and 4B.

The extraction engine 130 may extract a standard cell model (STC-MD) from the generated three-dimensional structure (3D-STR). For example, the standard cell model (STC-MD) may include a compact model and a parasitic RC extraction (PEX) model. Extraction engine 130 may include an extraction tool such as Synopsys Mystic ^TM . The extraction engine 130 may extract a compact model for the target standard cell from IV/CV curves generated from the 3D structure using an extraction tool. In an example embodiment, the PEX model may include at least one of a two-dimensional PEX model extracted using a tool such as StarRC ^™ and a three-dimensional PEX model extracted using a tool such as Raphael ^™ .

The evaluation engine 140 may perform an evaluation operation based on a standard cell model. The evaluation operation may include various evaluation operations such as ground rule (GR) evaluation, area scaling evaluation, performance-power evaluation, yield evaluation, etc.

The ground rule (GR) evaluation operation refers to the operation of evaluating whether the standard cell model (STC-MD) satisfies the ground rule. For example, to prevent defects due to physical characteristics of the various configurations of the target standard cell, the various configurations of the target standard cell may be maintained at specific intervals. As a more detailed example, the gate contact and source contact included in the target standard cell must be spaced apart by a predetermined distance to prevent interference due to their respective electrical characteristics. Ground rule evaluation may refer to the operation of determining whether the physical distance between each of these components satisfies a predetermined condition (i.e., ground rule). In an example embodiment, the ground rule may be determined according to process conditions for the target standard cell. In an example embodiment, according to the results of the ground rule (GR) evaluation operation, the design rule of the target standard cell may be updated.

The area scaling evaluation operation can check whether the updated design rule is appropriate according to the results of the ground rule (GR) evaluation operation. For example, among vertical parameters, it can be checked whether the process scale determined by the control engine is suitable for the updated design rule. In an example embodiment, in an area scaling evaluation operation, large standard cells such as flip-flops, AOIs, etc. may be inspected considering the impact of metal interconnect complexity on the area scale.

The performance-power evaluation operation refers to the operation of evaluating the performance and power consumption of the target standard cell. In a performance-power evaluation operation, parameters such as target standard cell size, fan-out style, Vdd/Vth sweep, user scenario for dynamic power, and BEOL RC loading can be adjusted for accurate comparison. In an example embodiment, performance-power evaluation operations may be performed on basic standard cells such as inverters, 2-input NAND gates, 2-input NOR gates, etc.

The yield evaluation operation may refer to an operation of evaluating whether the electrical margin of the target standard cell is appropriate. For example, a yield evaluation operation can be performed on a 6-TR SRAM cell with statistical changes in the pull-up transistor, pull-down transistor, and pass-gate transistor. Based on the read/write/interference margin at each Vdd, Vmin can be determined.

In an exemplary embodiment, the evaluation engine 140 runs a Simulation Program with Integrated Circuit Emphasis (SPICE) simulation based on a standard cell model (STC-MD) to perform the various evaluation operations described above, and performs the evaluation results (ASR; Assessment Result) can be configured to output.

The automatic optimization engine 150 may perform automatic layout generation and multi-objective optimization operations based on the evaluation result (ASR) from the evaluation engine 140. For example, the evaluation results (ASR) from evaluation engine 140 may include various information about the target standard cell (e.g., Performance-Power, Area, and Yield (PPAY)). may include. In an example embodiment, the evaluation result (ASR) may vary depending on a plurality of parameters (Xs) (including a planar parameter and a vertical parameter) of the target standard cell. For example, depending on the size of the active area of the target standard cell or the process scaling of the target standard cell, the performance, power, area, and yield for the target standard cell may change. The automatic optimization engine 150 may adjust planar parameters and vertical parameters for the target standard cell so that performance, power, area, and yield for the target standard cell can be optimized.

In an example embodiment, the automatic optimization engine 150 may perform optimization operations based on machine learning. For example, the automatic optimization engine 150 may be configured to generate a learning model by performing a training operation on randomly sampled target standard cells, and perform the above-described automatic optimization operation based on the generated learning model. The automatic optimization engine 150 determines a plurality of parameters (Xs) (including planar parameters and vertical parameters) in the direction of increasing performance, reducing power consumption, reducing area, and increasing yield. (i.e. optimization) can be done.

The control engine 110 re-determines a plurality of parameters (Xs) based on the result (Xs') of the automatic optimization operation of the automatic optimization engine 150, and the previously described operation is repeatedly performed to determine the target standard cell. Optimized planar parameters and vertical parameters can be determined. The optimized planar parameters and vertical parameters can be output as optimized standard cell information (OSI).

In an example embodiment, a standard cell generated based on optimized planar parameters and vertical parameters may meet predetermined criteria in various conditions such as performance-power, area, and yield (PPAY). In an example embodiment, the predetermined reference value may vary depending on the type of target standard cell, a process method applied to the target standard cell, process scaling, etc.

According to the embodiment of the present invention described above, the standard cell design system 100 can output optimized standard cell information (OSI) of the target standard cell. At this time, the standard cell design system 100 can reduce the time required for standard cell optimization by performing optimization operations based on machine learning.

FIG. 3 is a flowchart showing an automatic optimization operation for a target standard cell of the standard cell design system of FIG. 2. Referring to FIGS. 2 and 3 , in step S110, the standard cell design system 100 may determine planar parameters and vertical parameters. As previously described, planar parameters may include information about the planar layout for the target standard cell, and vertical parameters may include information about process conditions for the target standard cell.

In step S120, the standard cell design system 100 may generate a three-dimensional structure (3D-STR) to which Litho Contour is applied based on planar parameters and vertical parameters. For example, the standard cell design system 100 may generate a three-dimensional structure (3D-STR) for a target standard cell using numerical planar parameters and vertical parameters.

In step S130, the standard cell design system 100 may extract a standard cell model from the generated three-dimensional structure (3D-STR). For example, the standard cell design system 100 can extract various parameters from a three-dimensional structure (3D-STR) and create a standard cell model (STC-MD) for the target standard cell based on the extracted parameters. there is.

In step S140, the standard cell design system 100 may perform various evaluation operations on the target standard cell based on the standard cell model (STC-MD). For example, the standard cell design system 100 runs SPICE (Simulation Program with Integrated Circuit Emphasis) simulation based on a standard cell model (STC-MD) to determine the performance, power, area, and yield ( Various items such as PPAY) can be evaluated.

In an exemplary embodiment, evaluated items may be different depending on the type of target standard cell. For example, performance-power is evaluated for basic standard cells such as inverter, 2-input NAND gate, 2-input NOR gate, etc., area scaling is evaluated for standard cells such as flip-flop, AOI, etc., and area scaling is evaluated for standard cells such as SRAM. Yield can be evaluated for standard cells. However, the scope of the present invention is not limited thereto.

In step S150, the standard cell design system 100 may determine whether the evaluation result is optimized. For example, the SCT design system 100 may determine whether the evaluation result satisfies a predetermined standard. The predetermined reference value may include performance conditions, power conditions, area conditions, or yield conditions for the target standard cell. The predetermined reference value may vary depending on the type of target standard cell, process method for the target standard cell, process scale, etc.

If the evaluation result is not determined to be optimized, in step S160, the standard cell design system 100 may optimize the planar parameters and vertical parameters. For example, the standard cell design system 100 may reset the planar parameters and vertical parameters in a direction that optimizes the evaluation results. For example, the standard cell design system 100 may adjust planar parameters and vertical parameters in a direction that improves performance, reduces power consumption, reduces area, or increases yield. After the planar parameters and vertical parameters are adjusted, the standard cell design system 100 may re-perform step S120.

If the evaluation result is determined to be optimized, in step S170, the standard cell design system 100 may output the planar parameters and vertical parameters as optimized standard cell information (OSI).

As described above, the SCT design system 100 may output optimized standard cell information for the target standard cell by repeatedly performing the automatic optimization operation described with reference to FIG. 3. In an exemplary embodiment, steps S150 and S160 may be performed based on machine learning.

4A and 4B are diagrams showing an example plan layout of a target standard cell. With reference to the layouts LAY1 and LAY2 of FIGS. 4A and 4B, Litho Contour based on the OPC model is explained.

Referring to FIGS. 2, 4A, and 4B, the control engine 110 may determine the layout for the target standard cell as a plane parameter of the target standard cell. In this case, the target standard cell includes first and second active regions (ACT1, ACT2), first to sixth contacts (CT1 to CT6), first and second gate electrodes (GE1, GE2), and It may include first and second gate contacts GC1 and GC2. The general plan layout of the target standard cell may be formed as the first layout (LAY1) in FIG. 4A. Like the first layout LAY1 of FIG. 4A, a general planar layout may have an ideal shape (i.e., a shape in which edge areas are right angles).

On the other hand, according to an embodiment of the present invention, the 3D structure creation engine 120 may apply a Litho Contour based on the OPC model to the first layout (LAY1). In this case, the layout of the target standard cell to which Litho Contour is applied may be the same as the second layout (LAY2) in FIG. 4B. For example, when creating a target standard cell based on the first layout (LAY1), the target standard cell will not be manufactured in the same form as the first layout (LAY1) due to various physical factors in the semiconductor manufacturing process.

That is, the 3D structure generation engine 120 can generate a 3D structure similar to the target standard cell that is actually formed by applying a Litho Contour based on the OPC model to the 3D structure. In an exemplary embodiment, the lithocontour is based on an OPC model determined according to various process conditions of the target standard cell (e.g., process method, material composition of the target standard cell, process scale, etc.).

In this case, the evaluation accuracy of the 3D structure can be improved. For example, in the first layout LAY1 to which Litho Contour is not applied, the distance between the gate contact and the source contact may be “X0”. On the other hand, in the second layout (LAY2) to which Litho Contour is applied, the distance between the gate contact and the source contact may be “X1”.

Depending on the electrical characteristics of the target standard cell, there must be a minimum distance between the gate contact and the source contact to prevent defects. At this time, even if the length of “X1” is shorter than the above-mentioned minimum distance, if the length of “X1” is longer than the minimum distance, the minimum distance condition for the target standard cell that is actually manufactured can be satisfied. (In other words, no defects due to the minimum distance condition exist.)

In other words, this may mean that by applying a litho contour based on the OPC model, the distance between the gate electrode and the adjacent contact can be further narrowed. In other words, the 3D structure generation engine 120 according to the present invention can reflect the actual manufacturing form of the target standard cell by applying the Riso contour based on the OPC model to the 3D structure, and accordingly, the ground rule (GR) The accuracy of the evaluation operation or area scaling evaluation operation may be improved.

Figure 5 is a graph to explain the mesh size of the standard cell model. Referring to FIG. 5, at extreme process scales, the accuracy and simulation time of parameters (e.g., resistance values) extracted from the standard cell model may vary depending on the mesh size of the standard cell model. In general, when the mesh size increases, the simulation time can be reduced, but the size of the extracted parameter (e.g., resistance value) may differ from the actual value. On the other hand, when the mesh size becomes smaller, the size of the extracted parameter may become similar to the actual value, but the simulation time may increase.

For example, as shown in Figure 5, when the mesh size is 0.003nm, the extracted parameter value may have a size of about 120% compared to the actual value, and the simulation time may have a time similar to the reference value. You can. On the other hand, when the mesh size is 0.001 nm, the extracted parameter values may be similar to the actual values, but the simulation time may increase by about 300% or more compared to the reference value.

The extraction engine according to an embodiment of the present invention can determine the optimized mesh size by considering the simulation time and the accuracy of extracted parameters, and extract a standard cell model based on the optimized mesh size.

Figure 6 is a diagram for explaining the accuracy of standard cell model evaluation according to an embodiment of the present invention. Referring to FIG. 6, the extraction engine 130 according to an embodiment of the present invention is configured to extract a standard cell model from a three-dimensional structure. The standard cell model can be extracted as a two-dimensional PEX model using a two-dimensional extraction tool such as StarRC ^™ , or as a three-dimensional PEX model using a three-dimensional extraction tool such as Raphael ^™ .

In an exemplary embodiment, when extracted to a 3D PEX model using a 3D extraction tool, the accuracy of the extracted parameters (e.g., resistance) is greater than that of the neck extracted to a 2D PEX model using a 2D extraction tool. It can be improved. For example, as shown in FIG. 6, when a 3D extraction tool is used, the extracted parameters (e.g., For example, the change in resistance (R) may be larger than that achieved by a two-dimensional extraction tool. This is because when extracting parameters in a 3D extraction tool, an increased portion of the barrier metal layers within the contact (eg, the second contact CT2 in FIG. 4B) is taken into consideration. In other words, by using a 3D extraction tool, the accuracy of extracted parameters can be improved, and thus the optimization accuracy for the target standard cell can be improved.

In an exemplary embodiment, the difference between the two-dimensional PEX model and the three-dimensional PEX model described with reference to FIG. 6 is simply for illustrating the accuracy of parameter changes, and the scope of the present invention is not limited thereto. For example, when the process scaling for the target standard cell is relatively large, the difference in parameter changes between the two-dimensional PEX model and the three-dimensional PEX model may be relatively small. That is, even if a two-dimensional PEX model is used, the standard cell design system 100 according to the present invention can normally perform optimization operations for the target standard cell.

Figure 7 is a block diagram exemplarily showing an evaluation engine according to an embodiment of the present invention. Referring to FIGS. 2 and 7 , the evaluation engine 140 may perform various evaluation operations based on a standard cell model. For example, the evaluation engine 140 may include a ground rule evaluation unit 141, a performance-power evaluation unit 142, and a yield evaluation unit 143.

The ground rule (GR) evaluation unit 141 may perform a ground rule evaluation operation and an area scaling evaluation operation for the target standard cell based on the standard cell model. As described with reference to FIG. 2, ground rule evaluation may refer to an operation of evaluating whether a target standard cell satisfies layout conditions (i.e., ground rule) in advance, based on a standard cell model (3D MD). The area scaling evaluation operation can check whether the updated design rule is appropriate according to the results of the ground rule evaluation operation. Since the ground rule evaluation operation and the area scaling evaluation operation have been previously described, detailed description thereof will be omitted.

The performance power evaluation unit 142 may perform a performance-power evaluation operation for the target standard cell based on the standard cell model. The performance-power evaluation operation refers to the operation of evaluating the performance and power consumption of the target standard cell based on the standard cell model (STC-MD). Since the performance-power evaluation operation has been described previously, detailed description thereof is omitted.

The parametric yield evaluation unit 143 may perform a yield evaluation operation on a target standard cell based on a standard cell model (STC-MD). The yield evaluation operation refers to the operation of evaluating the yield of a target standard cell based on the standard cell model (STC-MD). Since the yield evaluation operation has been described previously, detailed description thereof is omitted.

In an exemplary embodiment, based on the standard cell model (STC-MD), each of ground rule evaluation unit 141, performance-power evaluation unit 142, and yield evaluation unit 143 individually corresponds to an evaluation operation. can be performed. Alternatively, based on the standard cell model, the ground rule evaluation unit 141, the performance-power evaluation unit 142, and the yield evaluation unit 143 may sequentially perform corresponding evaluation operations.

In an exemplary embodiment, the ground rule evaluation unit 141, the performance-power evaluation unit 142, and the yield evaluation unit 143 may each perform a corresponding evaluation operation and output a result of the evaluation operation.

For example, the ground rule evaluation unit 141 may perform a ground rule evaluation operation on a target standard cell and output information about a design rule (DRM) or scale as a first evaluation result (Y1). The performance-power evaluation unit 142 may perform a performance-power evaluation operation for the target standard cell and output information about performance and power as a second evaluation result (Y2). The parametric yield evaluation unit 143 may perform a yield evaluation operation on the target standard cell and output information about the yield as a third evaluation result (Y3). In the exemplary embodiment, the above-described evaluation results (Y1 to Y3) are illustrative, and the scope of the present invention is not limited thereto.

In an example embodiment, some of a plurality of evaluation operations may be performed depending on the type of the target standard cell. Performance-power is evaluated for basic standard cells such as inverter, 2-input NAND gate, 2-input NOR gate, etc., area scaling is evaluated for standard cells such as flip-flop, AOI, etc., and for standard cell such as SRAM, Yield can be evaluated. However, the scope of the present invention is not limited thereto.

Figure 8 is a flowchart showing the operation of the evaluation engine of Figure 7. Referring to FIGS. 7 and 8 , the evaluation engine 140 may perform various evaluation operations by performing operations in steps S141 to S146.

In step S141, the evaluation engine 140 may evaluate the critical ground rule for the target standard cell. For example, the ground rule evaluation unit 141 of the evaluation engine 140 may evaluate whether the target standard cell satisfies the ground rule based on the standard cell model.

In step S142, the evaluation engine 140 may determine whether a defect exists. For example, the evaluation engine 140 may determine whether defects related to ground rules (eg, chronic systematic defects) exist.

If a defect exists, in step S143, the evaluation engine 140 may update the design rule manual (DRM). For example, evaluation engine 140 may screen-out faults related to ground rules. The Design Rules Manual (DRM) may be updated based on information about excluded defects.

In step S144, the evaluation engine 140 may perform area scaling evaluation. At this time, the target standard cell can be redrawn using the design rule manual or an updated design rule manual, and area scaling can be evaluated at the new node. In an example embodiment, in area scaling evaluation, design rules may be examined.

In step S145, the evaluation engine 140 may perform evaluation on performance, power, or yield. Since evaluation of performance, power, or yield has been described above, detailed description thereof is omitted.

In step S146, the evaluation engine 146 may output an evaluation result. In an example embodiment, the evaluation results may be provided to the automatic optimization engine 150.

In an example embodiment, a plurality of the evaluation operations of evaluation engine 146 described above may be automated. For example, the evaluation engine 146 is configured to automatically perform the various evaluation operations described above by running SPICE (Simulation Program with Integrated Circuit Emphasis) simulation based on the extracted standard cell model and automatically output the evaluation results. It can be. The evaluation results may include whether Performance, Power, Area, and Yield (PPAY) satisfies the respective standard or numerical information for each.

FIG. 9 is a diagram illustrating the automatic optimization engine of FIG. 2. Referring to FIG. 9, the automatic optimization engine 150 may include an input layer 151, a hidden layer 152, an output layer 153, and a learning model 154. The automatic optimization engine 150 may perform optimization operations based on a machine-learning algorithm or a neural network algorithm.

The input layer 151 receives the results of evaluation operations (Y1 to Yn) (e.g., evaluation results for performance, power, area, or yield (PPAY) for the target standard cell), and provides a hidden layer ( 152). The output layer 153 may output optimized planar and vertical parameters (X1 to Xm) from the hidden layer 152.

The hidden layer 152 can convert values received through the input layer into values necessary for optimization operation. All nodes included in the input layer 151 and the hidden layer 152 may be connected to each other through weights, and all nodes included in the hidden layer 152 and the output layer 153 may be connected to each other through weights. At this time, the weight may be set to a value based on the learning model 154 created through a training operation.

The learning model 154 may be created through a training operation of the automatic optimization engine 150. The learning model 154 may be a model in which information about the relationship between the planar and vertical parameters (X1 to Xm) of the target standard cell and the evaluation results (Y1 to Yn) is learned. The learning model 154 may be modeled so that the plane and vertical parameters (X1 to Xm) are determined in a direction in which the evaluation results (Y1 to Yn) are optimized.

The automatic optimization engine 150 performs various evaluation operations (e.g., PPAY) on randomly sampled planar and vertical parameters (X1 to Xm), and evaluates the results of the evaluation operations (Y1 to Yn) and random sampling. A learning model 154 can be created by performing a training operation based on the plane and vertical parameters (X1 to Xm). As an example, as the automatic optimization engine 150 repeatedly performs optimization operations, the learning model may be updated.

As described above, the automatic optimization engine 150 uses a machine-learning algorithm or a neural network algorithm to optimize the evaluation results (Y1 to Ym) (e.g., PPAY) for the target standard cell. Parameters and vertical parameters (X1~Xm) can be determined. That is, the time required to determine standard cell information (OSI) optimized by the automatic optimization engine 150 can be reduced.

Although the automatic optimization engine 150 operating based on a neural network has been described with reference to FIG. 9, the scope of the present invention is not limited thereto. For example, the automatic optimization engine 150 may use a supervised learning algorithm, a semi-supervised learning algorithm, an unsupervised learning algorithm, or a reinforcement learning algorithm. ), the above-described optimization operation can be performed based on any one of various machine learning algorithms such as.

Figures 10a and 10b are diagrams for explaining the operation of the optimization engine. For convenience of explanation, the performance-power optimization operation for some plane parameters (X1, X2) is explained with reference to FIGS. 10A and 10B. However, the scope of the present invention is not limited thereto, and various planar parameters and various vertical parameters may be adjusted to optimize various conditions (eg, PPAY).

Referring to FIG. 10A, the target standard cell may have the same structure as the second layout (LAY2) in FIG. 10A. For example, the target standard cell includes first and second active areas (ACT1, ACT2), first to sixth contacts (CT1 to CT6), first and second gate electrodes (GE1, GE2), and It may include first and second gate contacts GC1 and GC2. Since the second layout LAY2 in FIG. 10A is similar to the second layout LAY2 in FIG. 4B, detailed description thereof is omitted.

At this time, let the distance between the gate electrode and the active area be “X2” and the length of the active area be “X3”. In this case, the evaluation result (for example, the evaluation result for performance-power) may change depending on the length of X2 and X3. For example, the first graph G1 of FIG. 10B shows sampling points for each length of X2 and X3. The second graph G2 of FIG. 10B shows the performance-power evaluation results corresponding to each of the sampling points of the first graph G1.

For example, the first sampling point SP1 indicates that the length of X2 is “L11” and the length of X3 is “L12”. The performance-power evaluation result for the standard cell model of the target standard cell generated based on the first sampling point (SP1) is that the power (i.e. power consumption) is greater than the reference value (REF1) and the performance is greater than the reference value (REF2). It can refer to low. That is, the values of X2 and X3 of the first sampling point (SP1) may be parameters that do not satisfy the performance-power reference values (REF1 and REF2). In other words, the values of X2 and X3 of the first sampling point SP1 may not be optimized parameters.

This refers to a case where the length of X2 of the second sampling point (SP2) is “L21” and the length of X3 is “L22”. The performance-power evaluation result for the standard cell model of the target standard cell generated based on the second sampling point (SP2) may indicate that the power is greater than the reference value (REF1) and the performance is higher than the reference value (REF2). That is, the performance condition may be satisfied at the second sampling point SP2, but the power condition may not be satisfied. Accordingly, the values of X2 and X3 of the second sampling point SP2 may not be optimized values.

Similarly, the lengths of X2 of the third and fourth sampling points SP3 and SP4 are “L31” and “L41”, respectively, and the lengths of The performance-power evaluation results for the standard cell models of the target standard cell each generated based on the third and fourth sampling points (SP3, SP4) show that the power is lower than the reference value (REF1) and the performance is lower than the reference value (REF2). ) can indicate higher than. That is, the values of X2 and X3 of the third and fourth sampling points SP3 and SP4 may be values that satisfy both performance conditions and power conditions. The automatic optimization engine 150 may adjust the values of X2 and X3 for the target standard cell so that performance-power conditions are satisfied.

In an exemplary embodiment, the standard cell design system 100 may perform random sampling on the above-described planar parameters or vertical parameters, and may repeatedly perform various evaluation operations for each of the randomly sampled sampling points. The standard cell design system 100 is a Pareto set of planar parameters or vertical parameters for which performance, power, area, or yield is optimized through repeated performance of the above-described operations based on machine-learning algorithms or neural network algorithms. ) can be determined. A Pareto set may point to information about the planar parameters and vertical parameters for which evaluation results are optimized. The standard cell design system 100 may determine optimized standard cell information for the target standard cell through the above-described operation based on a machine learning algorithm or a neural network algorithm.

Although changes in the performance-power evaluation results according to changes in the two plane parameters X2 and X3 are explained in FIGS. 10A and 10B, the scope of the present invention is not limited thereto. For example, the performance-power evaluation result as well as the area or yield evaluation result may change depending on the change in the plane parameters X2 and In addition, the performance-power evaluation results may change depending on changes in not only the plane parameters X2 and X3 described with reference to FIGS. 10A and 10B, but also other plane parameters or other vertical parameters.

That is, various evaluation results may change individually or in combination according to changes in each or a combination of various planar parameters and various vertical parameters for the target standard cell. In the conventional optimization method, due to this complex relationship, a lot of time was consumed to obtain optimized standard cell information (OSI) of the target standard cell. However, the automatic optimization engine 150 according to an embodiment of the present invention may perform the above-described optimization operation based on a machine learning algorithm or a neural network algorithm. Accordingly, the time required to obtain optimized standard cell information for the target standard cell can be reduced.

FIG. 11 is an exemplary diagram for explaining the block design system of FIG. 1. Referring to FIGS. 1 and 11 , the block design system 300 may be configured to generate a block layout (BLK LAY) based on various standard cell information stored in the standard cell library 200. Block layout (BLK LAY) may indicate a layout for manufacturing a target semiconductor device that performs an intended function using various standard cell information stored in the standard cell library 200. For example, the block layout (BLK LAY) may include various information necessary to create a target semiconductor device, such as information about the arrangement of a plurality of standard cells and wiring information connecting the plurality of standard cells.

Block design system 300 may include a standard cell characterization engine 310, a synthesis engine 320, and an evaluation engine 330. The standard cell characterization engine 310 may convert or characterize standard cell information (STC) from the standard cell library 200 into information needed to generate or evaluate a block layout (BLK LAY). For example, the standard cell characterization engine 310 may characterize information such as delay, operation timing, power, signal reliability, etc. for the corresponding standard cell based on standard cell information (STC).

The synthesis engine 320 may generate a block layout (BLK LAY) by combining a plurality of standard cells based on information characterized by the standard cell characterization engine 310. For example, the synthesis engine 320 may generate a block layout (BLK LAY) including information such as the arrangement of a plurality of standard cells on a semiconductor wafer and the arrangement of wires for connecting the plurality of standard cells to each other.

The evaluation engine 330 may perform various evaluation operations on the generated block layout (BLK LAY). For example, the evaluation engine 330 may perform evaluation on performance, power, area, and yield (PPAY) for the block layout (BLK LAY). According to the evaluation result of the evaluation engine 330, the synthesis engine 320 may adjust the block layout (BLK LAY) to optimize the evaluation result. In an example embodiment, each of synthesis engine 320 and evaluation engine 330 may perform the operations described above based on machine learning or neural network algorithms.

Figure 12 is a block diagram illustrating a computing device associated with a semiconductor design system according to an embodiment of the present invention. Referring to FIG. 12 , the computing system 1000 may include a processor 1100 and a memory 1200. The computing system 1000 may be configured to drive the semiconductor design system 10 according to an embodiment of the present invention.

For example, memory 1200 may include instructions executable by processor 1100. The processor 1100 may perform the operation of the semiconductor design system 10 described with reference to FIGS. 1 to 11 by executing instructions stored in the memory. The results of the operation of the processor 1100 may be stored in the memory 1200, and the results stored in the memory 1200 may be used to manufacture a semiconductor device.

As described above, according to embodiments of the present invention, a semiconductor design system may optimize a target standard cell or optimize a block layout using a machine learning algorithm or a neural network algorithm. Accordingly, the time required to search for the optimal target standard cell can be reduced compared to a conventional standard cell optimization operation. Therefore, the semiconductor design system according to an embodiment of the present invention can facilitate next-generation logic design or establishment of a next-generation process plan.

The above-described details are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also embodiments that can be simply changed or easily changed in design. In addition, the present invention will also include technologies that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims and equivalents of the present invention as well as the claims described later.

10: Semiconductor design system
100: Standard Cell Design System
200: Standard cell library
300: Block design system
Xs: Plane parameters and vertical parameters
3D-STR: 3D structure
STC-MD: Standard Cell Model
ASR: Evaluation Results
OSI: Optimized Standard Cell Information

Claims (20)

In a standard cell design system including at least one processor,
The at least one processor:
a control engine configured to determine planar parameters and vertical parameters for a target standard cell;
a 3D structure generation engine configured to generate a 3D structure for the target standard cell based on the planar parameters and the vertical parameters;
an extraction engine configured to extract a standard cell model for the target standard cell from the three-dimensional structure;
an evaluation engine configured to perform a plurality of evaluation operations based on the standard cell model; and
configured to implement an automatic optimization engine configured to adjust the planar parameters and the vertical parameters based on the results of the plurality of evaluation operations,
The automatic optimization engine adjusts the planar parameters and the vertical parameters based on a machine learning algorithm,
The planar parameters include planar layout information for the target standard cell,
The vertical parameters include a plurality of process information for the target standard cell.
According to claim 1,
The 3D structure generation engine is further configured to generate the 3D structure by applying a risocontour based on an Optical Proximity Correction (OPC) model,
A standard cell design system wherein the OPC model is determined by the planar parameters and the vertical parameters.
According to claim 1,
The standard cell model is a standard cell design system including a compact model and a parasitic RC extraction (PEX) model for the target standard cell extracted from the three-dimensional structure.
According to claim 3,
The PEX model is a standard cell design system that is either a two-dimensional PEX model or a three-dimensional PEX model.
According to claim 1,
The plurality of evaluation operations include at least one of a ground rule (GR) evaluation operation for the target standard cell, a performance-power evaluation operation for the target standard cell, and a yield evaluation operation for the target standard cell. Standard cell design system.
According to claim 5,
A standard cell design system in which the evaluation engine selectively performs some of the plurality of evaluation operations depending on the type of the target standard cell.
According to claim 5,
The results of the plurality of evaluation operations include information about at least one of an area of the target standard cell, performance of the target standard cell, power of the target standard cell, and yield of the target standard cell,
The automatic optimization engine is configured such that the area of the target standard cell is reduced, the performance of the target standard cell is increased, the power of the target standard cell is reduced, and the yield of the target standard cell is increased. A standard cell design system that adjusts the planar parameters and the vertical parameters based on a machine learning algorithm.
According to claim 1,
A standard cell design system in which a standard cell library is generated based on the adjusted planar parameters and the adjusted vertical parameters by the automatic optimization engine.
In the standard cell design optimization method of the standard cell design system,
determining planar parameters and vertical parameters for a target standard cell;
generating a first three-dimensional structure for the target standard cell based on the planar parameters and the vertical parameters;
extracting a first standard cell model from the first three-dimensional structure;
performing a plurality of evaluation operations on the target standard cell based on the first standard cell model;
determining whether the results of the plurality of evaluation operations each satisfy a plurality of reference values;
If the results of the plurality of evaluation operations do not respectively satisfy a plurality of reference values, the determined planar parameters, the determined vertical parameters, and the learning model updated according to the results of the plurality of evaluation operations are used. readjusting the planar parameters and the vertical parameters;
generating a second three-dimensional structure based on the readjusted planar parameters and the readjusted vertical parameters;
extracting a second standard cell model based on the second three-dimensional structure;
Comprising performing the plurality of evaluation operations based on the second standard cell model,
The planar parameters include planar layout information for the target standard cell,
The vertical parameters include a plurality of process information for the target standard cell.
According to clause 9,
The three-dimensional structure is created by applying a risocontour based on an Optical Proximity Correction (OPC) model,
A standard cell design optimization method wherein the OPC model is determined by the planar parameters and the vertical parameters.
According to clause 9,
The plurality of evaluation operations include at least one of a ground rule (GR) evaluation operation for the target standard cell, a performance-power evaluation operation for the target standard cell, and a yield evaluation operation for the target standard cell. A standard cell design optimization method.
According to claim 11,
The results of the plurality of evaluation operations include at least one of information about an area of the target standard cell, performance of the target standard cell, power of the target standard cell, and yield of the target standard cell,
The plurality of reference values include a first reference value for the area of the target standard cell, a second reference value for the performance of the target standard cell, a third reference value for the power of the target standard cell, and a yield for the target standard cell. Contains at least one of the fourth criteria,
The area of the target standard cell is smaller than the first reference value, the performance of the target standard cell is larger than the second reference value, the power of the target standard cell is smaller than the third reference value, and the A standard cell design optimization method in which the planar parameters and the vertical parameters are readjusted based on the learning model so that the yield is greater than the fourth reference value. According to claim 11,
The learning model is a standard cell design optimization method in which the learning model is generated based on the results of a plurality of evaluation operations based on randomly sampled planar parameters and randomly sampled vertical parameters for the target standard cell.
In a semiconductor design system including at least one processor,
The at least one processor:
a standard cell design system configured to optimize planar parameters and vertical parameters for a plurality of standard cells based on a first machine learning algorithm;
a standard cell library configured to generate optimized standard cell information for each of the plurality of standard cells based on the optimized planar parameters and the optimized vertical parameters; and
configured to implement a block design system configured to generate a block layout for a target semiconductor device based on the optimized standard cell information from the standard cell library,
The planar parameters include planar layout information for the plurality of standard cells,
A semiconductor design system wherein the vertical parameters include a plurality of process information for the plurality of standard cells.
According to claim 14,
The at least one processor has:
In the standard cell design system,
a control engine configured to determine planar parameters and vertical parameters for a target standard cell among the plurality of standard cells;
a 3D structure generation engine configured to generate a 3D structure for the target standard cell based on the determined planar parameters and the determined vertical parameters;
an extraction engine configured to extract a standard cell model for the target standard cell from the three-dimensional structure;
an evaluation engine configured to perform a plurality of evaluation operations based on the standard cell model; and
further configured to implement an automatic optimization engine configured to adjust the determined planar parameters and the determined vertical parameters based on the results of the plurality of evaluation operations;
The automatic optimization engine adjusts the determined planar parameters and the determined vertical parameters based on the first machine learning algorithm.
According to claim 14,
The at least one processor has:
In the block design system,
a standard cell characterization engine configured to characterize the optimized standard cell information from the standard cell library to generate characterized standard cell information;
a synthesis engine configured to generate the block layout by synthesizing the characterized standard cell information; and
A semiconductor design system further configured to implement an evaluation engine configured to perform a plurality of evaluation operations for the target semiconductor device based on the block layout.
According to claim 16,
The synthesis engine generates the block layout based on a second machine learning algorithm,
A semiconductor design system wherein the evaluation engine performs the plurality of evaluation operations based on a third machine learning algorithm.

delete delete delete

Images