KR102285516B1 - Semiconductor device modeling method and system - Google Patents

Abstract

A semiconductor element modeling method of a semiconductor element modeling system including a memory storing instructions and a processor executing the instructions is disclosed. The method includes the steps of: receiving first training data sets; determining second capacitance data, second current data, or second charge data; updating parameters of the first neural network; transmitting at least one of the parameters to the second neural network; receiving second training data; determining fourth capacitance data, fourth current data, or fourth charge data; and updating parameters of the second neural network.

Description

Semiconductor device modeling method and system {Semiconductor device modeling method and system}

The present invention relates to a method and system for modeling a semiconductor device, and more particularly, to a method and system for modeling a semiconductor device using a neural network.

One semiconductor chip is implemented with a plurality of transistors. In the process of designing the single semiconductor chip, a netlist describing the connectivity between transistors, capacitors, and resistors is created. The netlist and compact model are used in a simulator such as a Simulation Program for Integrated Circuit Emphasis (SPICE) to simulate the operation of each of the transistors.

The compact model is simple mathematical descriptions of the behavior of circuit elements constituting one semiconductor chip. The compact model describes the terminal behavior of circuit elements in terms of current-voltage (I-V), or capacitance-voltage (C-V). In the conventional compact model, an equation is generated by physically analyzing the operation of the device, and parameters of the device are extracted. The conventional compact model has a disadvantage in that it takes a long time to generate the equation and extract the parameters. In addition, as the size of the semiconductor device becomes smaller and new semiconductor materials are used, there is a problem in that it is more difficult to accurately extract parameters extracted using the conventional compact model.

Korean Patent Publication No. 10-2010-0080331 (2010.07.08.)

An object of the present invention is to provide a semiconductor device modeling method and system for generating a compact model using a neural network instead of a conventional compact model using a complex equation.

In the semiconductor device modeling method of a semiconductor device modeling system including a memory for storing instructions and a processor for executing the instructions according to an embodiment of the present invention, the processor is configured to train a first semiconductor device in order to train a first neural network. receiving first training data comprising a plurality of first voltage data sets of applying voltage data sets to an input of the first neural network to determine second capacitive data, second current data, or second charge data, wherein the processor is configured to: Update parameters of the first neural network according to comparison of first current data, or the first charge data, and the determined second capacitance data, the determined second current data, or the determined second charge data transmitting, by the processor, at least one of the parameters to the second neural network in order to reuse at least one of the updated parameters of the first neural network in a second neural network, the processor Receiving a plurality of second voltage data sets of a second semiconductor device and second training data sets including third capacitance data, third current data, or third charge data to train the second neural network step, the processor determining a fourth capacitive data, a fourth current data, or the fourth charge data by applying a plurality of the second voltage data set at the input of said second neural network, and wherein the processor is the Comparison of the received third capacitance data, the received third current data, or the received third charge data, and the determined fourth capacitance data, the determined fourth current data, or the determined fourth charge data and updating the parameters of the second neural network according to

Each of the received third capacitive data and the determined fourth capacitive data is expressed as a rate of change of electric charge with respect to change of voltage. The parameters of the second neural network are updated according to the comparison of the received third capacitive data expressed as a rate of change of charge with respect to the change of voltage and the determined fourth capacitive data.

According to an embodiment, in the semiconductor device modeling method of the semiconductor device modeling system, the processor includes a target function to automatically set a hyperparameter of the first neural network or the second neural network, and the target according to the hyperparameter variable. setting an acquisition function representing the standard deviation of a function, wherein the processor arbitrarily selects the hyperparameter variable and applies the randomly selected hyperparameter variable to the first neural network or the second neural network to output an output value and a target value performing an output operation of outputting a loss value indicating a difference of performing, by a processor, a correction operation for modifying the target function according to the output loss value and the standard deviation calculated in the acquisition function, and the processor performs the output operation, the calculation operation, and the correction until convergence The method further includes the step of repeatedly performing the operation and, as a result of the execution, setting a hyperparameter variable when the loss value is minimum as a hyperparameter of the first neural network or the second neural network.

Charge data is inferred through the updated second neural network according to the comparison of the received third capacitance data and the determined fourth capacitance data expressed as a rate of change of charge with respect to the change in voltage.

The parameters include a weight matrix and a bias vector.

A part of weight matrices and bias vectors included in the first neural network and a part of weight matrices and bias vectors included in the second neural network are common.

At least one of the first capacitance data, the first current data, and the first charge data is selected by a user of the semiconductor device modeling system.

In the semiconductor device modeling method of the semiconductor device modeling system, the processor applies a plurality of third voltage data sets of the second semiconductor device to the second neural network after training of the second neural network is completed in the second neural network. inferring fifth current data, or fifth charge data, and the processor indicating a relationship between a plurality of third voltage data sets of the second semiconductor device and fifth current data, or fifth charge data The method further includes generating a lookup table and outputting it as a compact model to which a neural network is applied based on the lookup table.

According to an embodiment, in the method of modeling a semiconductor device of the semiconductor device modeling system, the processor applies a plurality of third voltage data sets of the second semiconductor device to the second neural network after training of the second neural network is completed to apply the second voltage data set. inferring fifth current data or fifth charge data in a second neural network, and the processor relates to a plurality of third voltage data sets of the second semiconductor device and fifth current data or fifth charge data The method may further include outputting a result representing ? as a compact model to which a neural network is applied.

According to an embodiment, in the semiconductor device modeling method of the semiconductor device modeling system, the processor configures the characteristic data sets of the first semiconductor device or the second semiconductor device to train the first neural network or the second neural network. receiving, by the processor, the second capacitance data using the plurality of first voltage data sets of the received first semiconductor device and the characteristic data sets of the first semiconductor device; determining the second current data or second charge data, and the processor using the plurality of second voltage data sets of the received second semiconductor device and characteristic data sets of the second semiconductor device The method may further include determining the fourth capacitance data, the fourth current data, or the fourth charge data.

A semiconductor device modeling system according to an embodiment of the present invention includes a memory for storing instructions, and a processor for executing the instructions.

The instructions include a plurality of first voltage data sets of a first semiconductor device and first training data sets including first capacitance data, first current data, or first charge data to train a first neural network. receiving, applying the plurality of first voltage data sets to an input of the first neural network to determine second capacitive data, second current data, or second charge data, the received first capacitive data; updating parameters of the first neural network according to a comparison of the received first current data, or the first charge data, with the determined second capacitance data, the determined second current data, or the determined second charge data In order to reuse at least one of the updated parameters of the first neural network in a second neural network, at least one of the parameters is transferred to the second neural network, and a second semiconductor is used to train the second neural network. Receive a second training data set comprising a plurality of second voltage data sets of a device and a third capacitance data, a third current data, or a third charge data, wherein the plurality of second voltage data sets are applied to an input of a second neural network to determine a fourth capacitive data, a fourth current data, or a fourth charge data, wherein the received third capacitive data, the received third current data, or the received first and update parameters of the second neural network according to a comparison of three charge data, the determined fourth capacitance data, the determined fourth current data, or the determined fourth charge data.

The instructions set a target function for automatically setting a hyperparameter of the first neural network or the second neural network, and an acquisition function representing a standard deviation of the target function according to the hyperparameter variable, the hyperparameter variable arbitrarily selects and applies the arbitrarily selected hyperparameter variable to the first neural network or the second neural network to perform an output operation of outputting a loss value indicating a difference between an output value and a target value, and in the acquisition function performing a calculation operation of calculating the standard deviation of the target function according to an arbitrary selected hyperparameter variable, and performing a correction operation of correcting the target function according to the output loss value and the standard deviation calculated by the acquisition function; , the output operation, the calculation operation, and the correction operation are repeatedly performed until convergence, and as a result of the execution, the hyperparameter variable when the loss value is the minimum is set as a hyperparameter of the first neural network or the second neural network. It is implemented to set

Each of the received third capacitive data CT2 or CT3 and the determined fourth capacitive data is expressed as a rate of change of charge with respect to a change in voltage, and the reception expressed as a rate of change of charge with respect to a change of voltage. The parameters of the second neural network are updated according to the comparison of the determined third capacitive data with the determined fourth capacitive data.

The commands apply a plurality of third voltage data sets of the second semiconductor device to the second neural network after training of the second neural network is completed to infer fifth current data or fifth charge data from the second neural network. and outputting a result representing a relationship between a plurality of third voltage data sets of the second semiconductor device, fifth current data, or fifth charge data as a compact model to which a neural network is applied.

According to an embodiment, the instructions receive characteristic data sets of the first semiconductor device or characteristic data sets of the second semiconductor device for training the first neural network or the second neural network, wherein the received determining the second capacitance data, the second current data, or the second charge data using the plurality of first voltage data sets of a first semiconductor device and characteristic data sets of the first semiconductor device, to determine the fourth capacitance data, the fourth current data, or the fourth charge data using the received plurality of second voltage data sets of the second semiconductor device and the characteristic data sets of the second semiconductor device. is implemented

The semiconductor device modeling method and system according to an embodiment of the present invention has the effect of overcoming the disadvantages of the conventional compact model, which takes a long time to generate complex equations and to extract parameters, by generating a compact model to which a neural network is applied.

In addition, the semiconductor device modeling method and system according to an embodiment of the present invention does not require a lot of data by transferring the knowledge generated from one trained neural network model to a new neural network model, and it is possible to expect a reduction in training time and better performance. there is an effect that

In addition, the semiconductor device modeling method and system according to an embodiment of the present invention has an effect that it is possible to extract electric charges that are difficult to measure by transferring knowledge generated from one trained neural network model to a new neural network model.

In order to more fully understand the drawings recited in the Detailed Description of the Invention, a detailed description of each drawing is provided.
1 is a block diagram of a semiconductor device modeling system according to an embodiment of the present invention.
2 is a block diagram illustrating a method for modeling a semiconductor device according to an embodiment of the present invention.
3(a) to 3(f) are block diagrams for explaining an operation of automatically setting hyperparameters performed in the learning environment manager shown in FIG. 2 .
FIG. 4 shows a block diagram of the base model shown in FIG. 2 .
FIG. 5 is a block diagram illustrating an operation of transfer learning from the base model shown in FIG. 2 to a first enhancement model.
6 shows an inference graph after the neural network is trained without knowledge being transferred in the base model shown in FIG. 2 and an inference graph after the knowledge is transferred and the neural network is trained.
FIG. 7 shows a graph regarding capacitance data deduced from the first enhancement model shown in FIG. 2 and a graph regarding charge data deduced from the second enhancement model illustrated in FIG. 2 .
FIG. 8 shows a graph regarding charge data deduced from the first enhancement model shown in FIG. 2 and a graph regarding capacitance data deduced from the second enhancement model illustrated in FIG. 2 .

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in this specification are only exemplified for the purpose of explaining the embodiments according to the concept of the present invention, and the embodiments according to the concept of the present invention are It may be implemented in various forms and is not limited to the embodiments described herein.

Since the embodiments according to the concept of the present invention may have various changes and may have various forms, the embodiments will be illustrated in the drawings and described in detail herein. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosed forms, and includes all modifications, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first or second may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one element from another element, for example, without departing from the scope of the present invention, a first element may be called a second element, and similarly The second component may also be referred to as the first component.

When a component is referred to as being “connected” or “connected” to another component, it is understood that the other component may be directly connected or connected to the other component, but other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that no other element is present in the middle. Other expressions describing the relationship between elements, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", should be interpreted similarly.

The terms used herein are used only to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In this specification, terms such as "comprises" or "have" are intended to designate that the described features, numbers, steps, operations, components, parts, or combinations thereof exist, and include one or more other features or numbers. , it is to be understood that it does not preclude the possibility of the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present specification. does not

Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings.

1 is a block diagram of a semiconductor device modeling system according to an embodiment of the present invention.

Referring to FIG. 1 , the semiconductor device modeling system 10 is a system capable of deriving a compact model to which a neural network is applied instead of a conventional compact model using a complex formula and applying the derived compact model to a simulator such as SPICE. The semiconductor device modeling system 10 may be an electronic device such as a server, a computer, a notebook computer, a tablet PC, or a personal PC. The semiconductor device modeling system 10 includes a processor 11 and a memory 13 . The processor 11 executes instructions in which the semiconductor device model method is implemented. The memory 13 stores instructions in which the semiconductor device model method is implemented. Hereinafter, a specific semiconductor device model method is disclosed.

2 is a block diagram illustrating a method for modeling a semiconductor device according to an embodiment of the present invention.

Referring to FIGS. 1 and 2 , the machine learning manager 140 is configured to train a neural network included in each model 150 , 170 , or 180 , a base model 150 , and a first enhancement model. model 170 ), and a second enhancement model 180 . Any one of the base model 150 , the first enhancement model 170 , and the second enhancement model 180 is selected by the processor 11 . The selection may be performed by the user of the semiconductor device modeling system 10 pressing a specific option in the interface of the semiconductor device modeling system 10 .

The base model 150 is a model including an artificial neural network. The first improvement model 170 is a model to which the knowledge 153 is transferred from the base model 150 . The knowledge 153 may be some of the parameters trained in the first enhancement model 170 . The first enhancement model 170 also includes an artificial neural network. The second enhancement model 180 is a model to which knowledge 153 is transferred from the base model 150 similarly to the first enhancement model 170 . However, a differential value is used for the second enhancement model 180 . However, the differential value is not used in the first enhancement model 170 . In the present invention, the base model 150 , the first enhancement model 170 , or the second enhancement model 180 are referred to as, but may be referred to by various terms according to embodiments.

Hereinafter, when the base model 150 is selected by the user of the semiconductor device modeling system 10 , a training phase of the artificial neural network included in the base model 150 will be described.

Training data sets 110 are input to the semiconductor device modeling system 10 to train the neural network included in the base model 150 . The training data sets 110 may be obtained from Technology CAD (TCAD) or may be obtained through measurement. The training data sets 110 include current data (I), capacitance data (C), or charge data (Q) of a semiconductor device such as a transistor. Specifically, the training data sets 110 include information about a value of a current, a value of a capacitance, or a value of an electric charge of a semiconductor device such as a transistor. According to an embodiment, the training data sets 110 may further include characteristic data sets of the semiconductor device. Specifically, the training data sets 110 are physical property data sets representing the width, length, temperature, oxide, or thickness of the semiconductor device, or of the semiconductor device. It may be physical property data sets indicating strain or doping concentration. The training data sets 110 include a width value, a length value, a temperature value, an oxide value, a thickness value, a strain value, or a doping concentration value of the semiconductor device. may include information about _{Current data (IT} , I _T2 , or I _T3 ), capacitance data (C _T , C _T2 , or C _T3 ), or charge data (Q _T ) of a semiconductor device by a user of the semiconductor device modeling system 10 , A neural network is trained for Q _T2 , or Q _{T3 ).} When the user of the semiconductor device modeling system 10 _{selects charge data Q T} , Q _T2 , or Q _T3 of a semiconductor device, a neural network is trained on the charge data Q _T , Q _T2 , or Q _{T3 . Current data (IT} , I _T2 , or I _T3 ), capacitance data (C _T , C _T2 , or C _T3 ), and charge data of a semiconductor device by a user of the semiconductor device modeling system 10 according to an embodiment A neural network may be trained on two or more of (Q _T , Q _T2 , or Q _T3 ) data (eg, current data and capacitive data).

Also, the training data sets 110 may include data sets of a plurality of voltages of the semiconductor device to train the neural network. When the semiconductor device is a transistor, the data sets of the plurality of voltages may include drain voltage data, gate voltage data, and source voltage data. According to an embodiment, the data sets of the plurality of voltages may further include a body voltage.

According to an embodiment, the training data sets 110 may include data sets of a plurality of voltages of the semiconductor device and characteristic data sets of the semiconductor device in order to train a neural network. The property data sets are physical property data sets representing a width, length, temperature, oxide, or thickness of the semiconductor device, or a strain of the semiconductor device, or It may include physical property data sets indicating a doping concentration. The training data sets 110 for training the neural network included in the base model 150 may be referred to as first training data sets. Also, the semiconductor device may be referred to as a first semiconductor device. The capacitive data may be referred to as first capacitive data. The current data may be referred to as first current data. The charge data may be referred to as first charge data. The plurality of voltage data sets may be referred to as a plurality of first voltage data sets.

The data converter 120 preprocesses the training data sets 110 . Specifically, the data converter 120 converts the training data sets 110 into a matrix form according to a predetermined attribute order of the data 110 (eg, drain voltage, gate voltage, source voltage, body voltage, or charge in that order). rearrange to The training data sets 110 input to the semiconductor device modeling system 10 are not in the form of a matrix.

The learning environment manager 130 selects a hyperparameter used to control the training process of the neural network. For example, the hyperparameter may be the number of hidden layers, the number of nodes in each hidden layer, a learning rate, a learning rate attenuation, or an activation function. The hyperparameter may be manually set by a user or may be set automatically.

Hereinafter, an operation in which the hyperparameter is automatically set will be described.

3(a) to 3(f) are block diagrams for explaining an operation of automatically setting hyperparameters performed in the learning environment manager shown in FIG. 2 .

1 to 3( f ), when the target function f(θ) has a maximum value, the hyperparameter θ ^* is automatically set. The automatically set hyperparameter (θ ^* ) may be expressed as the following equation.

[Equation 1]

The θ ^* denotes a hyperparameter that is automatically set, and the θ denotes a hyperparameter variable. The argmax represents a value of a variable when the target function f(θ) has a maximum value. When the target function f(θ) has a maximum value, the hyperparameter variable θ is the optimal value of the hyperparameter, and the hyperparameter θ ^* is automatically set.

The goal function is unknown. However, it is assumed that the target function is known in advance in order to explain the operation in which the hyperparameter is automatically set, and the target function is shown in the graphs of FIGS. 3(a), 3(c), and 3(e). The x-axis of the target function shown in the graphs of FIGS. 3(a), 3(c), and 3(e) represents the hyperparameter variable (θ), and the y-axis represents the value of the target function (f(θ)). .

Although the objective function is shown in Fig. 3, a surrogate model for the objective function is required, assuming that the objective function is not known. The surrogate function uses a Gaussian process. That is, the surrogate function is fitted to the Gaussian process. According to an embodiment, various functions such as a random forest may be used as the surrogate function.

In order to determine where the maximum value is in the target function, an acquisition function is required.

The acquisition function may be implemented as an expected improvement function. The expected enhancement function may be expressed by the following equation.

[Equation 2]

The EI(x) is the expected enhancement function, the μ(x) is the average for the surrogate function, the f(x ⁺ ) is the maximum to date, the ξ is a small positive number, and the Φ( Z) represents a cumulative distribution function, σ represents a standard deviation, and ø(Z) represents a probability density function. The acquisition function is shown in the graphs of Figs. 3(b), 3(d), and 3(f). The x-axis of the acquisition function shown in the graphs of Figs. 3(b), 3(d), and 3(f) is the hyperparameter variable (θ), and the y-axis is the standard deviation of the Gaussian process used in the surrogate function. represents a value.

The Z can be expressed by the following equation.

[Equation 3]

The processor 11 automatically sets the ^{hyperparameter θ *} of the first neural network of the base model 150 , the second neural network of the first enhancement model 170 , or the neural network of the second enhancement model 180 . The surrogate function in which the Gaussian process is used and the acquisition function representing the standard deviation of the Gaussian process according to the hyperparameter variable θ are set.

The processor 11 arbitrarily selects the hyperparameter variable [theta]. The processor 11 applies the selected hyperparameter variable θ to the first neural network of the base model 150 , the second neural network of the first enhancement model 170 , or the neural network of the second enhancement model 180 . to perform an output operation of outputting a negative loss value, which means that a negative number is added to the difference between the output output value and the target value. The negative loss value is the actual value of the target function f(θ). According to an embodiment, the processor 11 converts the arbitrary selected hyperparameter variable θ into the first neural network of the base model 150, the second neural network of the first enhancement model 170, or the second enhancement model 180. By applying to the neural network of

In Figs. 3(a), 3(c), and 3(e), dots represent actual values of the target function f(θ).

The processor 11 performs a calculation operation of calculating the standard deviation σ of the Gaussian process according to the arbitrary selected hyperparameter variable θ in the acquisition function. An acquisition function representing the standard deviation σ according to the hyperparameter variable θ in the graphs of FIGS. 3(b), 3(d), and 3(f) is disclosed.

The processor 11 performs a correction operation of correcting the surrogate function through the L-BFGS algorithm according to the output loss value of the negative number and the standard deviation (σ) calculated in the acquisition function. According to an embodiment, the processor 11 may perform a correction operation of correcting the surrogate function through the L-BFGS algorithm according to the output loss value and the standard deviation σ calculated in the acquisition function.

The surrogate function shown in the graph of Fig. 3(a) has been modified to the surrogate function shown in the graph of Fig. 3(c).

The processor 11 repeatedly performs the output operation, the calculation operation, and the correction operation until convergence, and as a result of the execution, the hyperparameter variable θ when the loss value of the negative number is the maximum is calculated as the base model 150 ) of the first neural network, the second neural network of the first enhancement model 170 , or the hyperparameter (θ ^* ) of the neural network of the second enhancement model 180 . According to an embodiment, the processor 11 repeatedly performs the output operation, the calculation operation, and the correction operation until convergence, and as a result of the execution, the hyperparameter variable θ when the loss value is the minimum is used as a base model. ^{The hyperparameter (θ *} ) of the first neural network of 150 , the second neural network of the first enhancement model 170 , or the neural network of the second enhancement model 180 may be set.

FIG. 4 shows a block diagram of the base model shown in FIG. 2 .

1, 2, and 4 , the base model 150 includes a neural network 160 and a loss function 151 . The neural network 160 includes an input layer 161 , a hidden layer 163 , and an output layer 165 .

_{A plurality of voltage data sets V 1} , V ₂ , and V ₃ output from the data converter 120 are input to the input layer 161 . Each of the plurality of voltage data sets V ₁ , V ₂ , and V ₃ may be drain voltage data, gate voltage data, body voltage data, or source voltage data. The plurality of voltage data sets V ₁ , V ₂ , and V ₃ input to the input layer 161 are the plurality of first voltage data sets. According to an embodiment, a plurality of voltage data sets V ₁ , V ₂ , and V ₃ and characteristic data sets of a semiconductor device may be input to the input layer 161 .

The input layer 161 includes a plurality of nodes. The number of nodes of the input layer 161 may vary according to an embodiment.

The hidden layer 163 includes a plurality of nodes. An activation function is calculated in each of the plurality of nodes. The activation function may be a sigmoid function, a Rectified Linear Unit (ReLU), a hyperbolic function, or an Exponential Linear Unit (ELU). Voltage data sets of a plurality of nodes included in the input layer 161, a weight matrix, and a bias vector are used as inputs of the activation function. The plurality of nodes and the plurality of nodes included in the input layer 161 are fully connected. According to an embodiment, the number of nodes in the hidden layer may vary. The number of hidden layers may vary according to embodiments.

The output layer 165 includes one node. The node is connected to a plurality of nodes included in the hidden layer 163 . Calculation of the activation function is performed at the node. As a result of the calculation of the activation function, capacitance data (C _O ), current data ( _IO ), or charge data (Q _O ) is output. When the capacitive data is selected by the user of the semiconductor device modeling system 10 , the capacitive data C _O is output from the output layer 165 . When the current data is selected by the user of the semiconductor device modeling system 10 , the current data I _O is output from the output layer 165 . When the charge data is selected by the user of the semiconductor device modeling system 10 , the charge data Q _O is output from the output layer 165 . The capacitance data (C _O ), current data ( _IO ), or charge data (Q _O ) output through the activation function is the second capacitance data ( _CO ), the second current data ( _IO ), or It may be referred to as second charge data Q _{O .} That is, the processor 11 applies the plurality of first voltage data sets (V ₁ , V ₂ , and V ₃ ) to the input of the neural network 160 to obtain second capacitance data (C _O ) and second current data. (I _O ), or the second charge data (Q _O ) is determined. According to an embodiment, the processor 11 _{applies the plurality of first voltage data sets V 1} , V ₂ , and V ₃ and the characteristic data sets of the semiconductor device to the input of the neural network 160 to obtain the second electricity The capacity data C _O , the second current data I _O , or the second charge data Q _O may be determined.

A loss function 151 is used to train the neural network 160 . The parameters are updated using the loss function 151 . The parameters include weight matrices and bias vectors included in the neural network 160 . _{The second capacitance data C O} , the second current data I _O , or the second charge data Q _O output from the output layer 165 is input to the loss function 151 . _{Also, the first capacitance data C T} , the first current data I _T , or the first charge data Q _T output from the data converter 120 is input to the loss function 151 . The first capacitance data C _T , the first current data I _T , or the first charge data Q _T is a first training data set input to the semiconductor device modeling system 10 as the target data 152 . It is the data included in the 110.

When the first capacitive data C _T and the second capacitive data C _O are input to the loss function 151 , the processor 11 generates the first capacitive data C _T and the second capacitive data (C _O ) is compared and parameters of the neural network 160 are updated according to the comparison result. The processor 11 calculates the slope of the loss function 151 and updates the parameters of the neural network 160 to minimize the difference between _{the first capacitive data C T} and the second capacitive data C _{O .} . When the first current data I _T and the second current data I _O are input to the loss function 151 , the processor 11 generates the first current data I _T and the second current data I _O ), and the parameters of the neural network 160 may be updated according to the comparison result. When the first charge data Q _T and the second charge data Q _O are input to the loss function 151 , the processor 11 generates the first charge data Q _T and the second charge data Q _O . may be compared and parameters of the neural network 160 may be updated according to the comparison result. That is, the processor 11 includes the first capacitance data C _T , the first current data I _T , or the first charge data Q _T input to the semiconductor device modeling system 10 , and the neural network 160 . ), the parameters of the neural network 160 are updated according to a comparison between the second capacitance data C _O , the second current data I _O , or the second charge data Q _{O .}

Hereinafter, when the first enhancement model 170 is selected by the user of the semiconductor device modeling system 10 , a training step of the neural network included in the first enhancement model 170 will be described.

FIG. 5 is a block diagram illustrating an operation of transfer learning from the base model shown in FIG. 2 to a first enhancement model.

1, 2, and 5 , the structure of the first enhanced model 170 is the same as or similar to that of the base model 150 shown in FIG. 4 . However, the structure or values of the parameters of the neural network 160 of the base model 150 and the structure of the neural network 175 of the first enhancement model 170 or values of parameters may be different. The source model 203 shown in FIG. 5 corresponds to the base model 150 shown in FIG. 1 , and the neural network 160 shown in FIG. 5 is the neural network 160 of the base model 150 shown in FIG. 4 . corresponds to The target model 209 illustrated in FIG. 5 corresponds to the first enhancement model 170 or the second enhancement model 180 illustrated in FIG. 1 . The first enhancement model 170 includes a neural network 175 . The second enhancement model 180 includes a neural network 185 .

Hereinafter, the neural network 160 of the base model 150 may be referred to as a first neural network, and the neural network 175 of the first enhanced model 170 may be referred to as a second neural network. The source data 201 illustrated in FIG. 5 corresponds to the plurality of first voltage data sets V ₁ , V ₂ , and V ₃ illustrated in FIG. 4 . According to an embodiment, the source data 201 illustrated in FIG. 5 may further include characteristic data sets of the first semiconductor device 101 .

The source label 205 illustrated in FIG. 5 is the first capacitance data C _T , the first current data I _T , or the first charge data Q _T input to the semiconductor device modeling system 10 . . The source data 201 and the source label 205 include information about the first semiconductor device 101 .

The target data 207 shown in FIG. 5 is a plurality of second voltage data sets V ₄ , V ₅ , and V ₆ input to the second neural network 175 of the first enhancement model 170 . Each of the plurality of second voltage data sets V ₄ , V ₅ , and V ₆ may represent drain voltage data, gate voltage data, body voltage data, or source voltage data of the second semiconductor device 103 . When the source data 201 shown in FIG. 5 further includes characteristic data sets of the first semiconductor device 101 , the target data 207 shown in FIG. 5 is the characteristic data set of the second semiconductor device 103 . may include more.

The target label 211 shown in FIG. 5 is the third capacitance data of the second semiconductor device 103 input to the semiconductor device modeling system 10 to train the neural network 175 of the first enhancement model 170 . (C _T2 ), the third current data (I _T2 ), or the third charge data (Q _T2 ). The second semiconductor device 103 is a semiconductor device different from the first semiconductor device 101 .

The amount of the source data 201 and the amount of the source label 205 are greater than the amount of the target data 207 and the amount of the target label 211 . That is, the amount of the target data 207 and the amount of the target label 211 are less than the amount of the source data 201 and the amount of the source label 205 , so that the target model 209 which is the neural network 175 of the first enhancement model 170 . ), the computation time required can be reduced.

The processor 11 is configured to reuse at least any one of the updated parameters of the neural network 160 of the base model 150 in the neural network 175 of the first enhancement model 170 to reuse (reuse) at least any one of the parameters. One may be transmitted to the neural network 175 of the first enhancement model 170 . For example, a part of weight matrices and bias vectors of the neural network 175 of the first enhancement model 170 and a part of weight matrices and bias vectors of the neural network 160 of the base model 150 are the same. Also, according to an embodiment, weight matrices and bias vectors of the neural network of the first enhancement model 170 may be the same as weight matrices and bias vectors of the neural network 160 of the base model 150 . The knowledge transfer 153 represents at least one of the updated parameters of the neural network 160 of the base model 150 .

The processor 11 applies the plurality of second voltage data sets V ₄ , V ₅ , and V ₆ to the input of the second neural network 175 to obtain the fourth capacitance data, the fourth current data, or the fourth Determine the charge data. According to an embodiment, the processor 11 applies the characteristic data sets of the second semiconductor device 103 to the input of the second neural network 175 as well, so that the fourth capacitance data, the fourth current data, or the fourth charge data is applied. can be decided

The processor 11 is configured to obtain a second capacitive data _{according to a comparison of the received third capacitive data C T2} , or the received third current data I _T2 , with the determined fourth capacitive data or the determined fourth current data. 2 Update the parameters of the neural network 175 .

6 shows an inference graph after the neural network is trained without knowledge being transferred in the base model shown in FIG. 2 and an inference graph after the knowledge is transferred and the neural network is trained. FIG. 6(a) is an inference graph after the neural network (175, or 185 in FIG. 5) is trained without knowledge 153 being transferred in the base model 150 shown in FIG. 2, and FIG. 6(b) is FIG. After knowledge 153 is transferred from the base model 150 shown in Fig. 2 and the neural network (175, or 185 in Fig. 5) is trained, an inference graph is shown. In FIGS. 6A and 6B , the X-axis represents the drain-source voltage Vds, and the Y-axis represents the drain-source current Ids.

Referring to FIG. 6( a ), when the drain-source voltage Vds is between 0.2 μV and 1.2 μV, an error occurs between the actual drain-source current Ids and the inferred drain-source current Ids. can be known Assuming that the neural network 175 or 185 shown in FIG. 5 does not receive the knowledge 153 from the base model 150, the neural network 175, or 185) cannot be sufficiently learned.

Referring to FIG. 6(b), when the voltage Vds is between 0.2 μV and 1.2 μV, unlike FIG. 6(a), there is a difference between the actual drain-source current Ids and the inferred drain-source current Ids. It can be seen that no error occurs. This is because, even if the target data 207 of the neural network 175 or 185 is insufficient, the neural network 175 or 185 can be sufficiently trained by receiving the knowledge 153 from the base model 150 . That is, even if the target data 207 of the neural network 175 or 185 is insufficient, the neural network 175 or 185 is sufficiently learned by reusing at least one of the parameters of the first neural network 160 of the base model 150 . because it can be done It can be seen that the neural network 175 or 185 can be sufficiently trained with only a small amount of target data 207 through the transfer of the knowledge 153 .

Hereinafter, when the second enhancement model 180 is selected by the user of the semiconductor device modeling system 10 , a training step of the neural network included in the second enhancement model 180 will be described.

FIG. 5 may be a block diagram for explaining an operation of transfer learning from the base model shown in FIG. 2 to a second enhancement model.

1 , 2 , 4 , and 5 , the structure of the second enhancement model 180 is the same as or similar to that of the base model 150 illustrated in FIG. 4 . The structure or values of parameters of the neural network 160 of the base model 150 may be different from the structure of the neural network 185 of the second enhancement model 180 or values of parameters. That is, the first enhancement model 170 and the second enhancement module 180 are the same or similar. However, the differential value is used in the second enhancement model 180 , but the differential value is not used in the first enhancement model 170 . Since the structure of the second enhancement model 180 and the structure of the first enhancement model 170 are the same or similar, a detailed description of the second enhancement model 180 will be omitted.

The target data 207 shown in FIG. 5 is a plurality of voltage data sets V ₇ , V ₈ , and V ₉ input to the neural network 185 of the second enhancement model 180 . Each of the plurality of voltage data sets V ₇ , V ₈ , and V ₉ is the drain voltage data of the second semiconductor device 103 or the third semiconductor device 105 different from the second semiconductor device 103 , the gate It may represent voltage data, body voltage data, or source voltage data. According to an embodiment, the neural network 185 of the second enhancement model 180 may also be referred to as a second neural network. Also, according to an embodiment, the plurality of voltage data sets V ₇ , V ₈ , and V ₉ may be referred to as a plurality of second voltage data sets. According to an embodiment, the target data 207 illustrated in FIG. 5 may further include characteristic data sets of the third semiconductor device 105 .

The target label 211 shown in FIG. 5 is the second semiconductor device 103 or the third semiconductor device input to the semiconductor device modeling system 10 to train the neural network 185 of the second enhancement model 180 . Capacitance data (C _T3 ), current data (I _T3 ), or charge data (Q _T3 ) of ( 105 ). According to an embodiment, the capacitance data C _T3 , the current data I _T3 , or the charge data Q _T3 may be referred to as third capacitance data, third current data, or third charge data.

The processor 11 generates at least one of the parameters in order to reuse at least one of the updated parameters of the neural network 160 of the base model 150 in the neural network 175 of the first enhancement model 170. It can be transmitted to the neural network 185 of the two-enhancement model 180 .

The processor 11 applies the plurality of voltage data sets V ₇ , V ₈ , and V ₉ to the input of the neural network 185 to generate electricity of the second semiconductor device 103 or the third semiconductor device 105 . Capacitance data (not shown), current data (not shown), or charge data (not shown) are determined. According to an embodiment, the determined capacitance data, the determined current data, or the determined charge data may be referred to as fourth capacitance data, fourth current data, or fourth charge data. According to an embodiment, the processor 11 applies the characteristic data sets of the third semiconductor device 105 to the input of the neural network 185 , so that the capacitance of the second semiconductor device 103 or the third semiconductor device 105 is applied. Data (not shown), current data (not shown), or charge data (not shown) may be determined.

_{The processor 11 includes the received capacitance data C T2} , or the received current data I _T2 of the second semiconductor device 103 , or the third semiconductor device 105 , and the second semiconductor device 103 . , or the determined capacitance data of the third semiconductor device 105 or the determined current data is compared with the parameters of the neural network 185 of the second enhancement model 180 are updated. That is, the neural network 185 is trained.

The capacitance can be expressed as the following equation.

[Equation 4]

C=dq/dv

Wherein C denotes capacitance, dq denotes a change in charge, and dv denotes a change in voltage.

That is, capacitance can be expressed as a rate of change of electric charge with respect to change of voltage. The charge is very small and difficult to measure.

_{The received capacitance data C T2 of} the second semiconductor device 103 or the third semiconductor device 105 and the second semiconductor device to update parameters of the neural network 185 of the second enhancement model 180 , (103), or the determined capacitance data of the third semiconductor element 105 is compared. In this case, each of the received capacitance data C _T2 input for comparison and the determined capacitance data may be expressed as a rate of change of charge with respect to a change of voltage. That is, each of the received capacitance data C _T2 and the determined capacitance data may be in a differential form.

The parameters of the neural network 185 are updated according to the comparison of _{the received capacitance data C T2} , which is expressed as a rate of change of charge with respect to the change of voltage, with the determined capacitance data.

After the training of the neural network 185 is completed, information about electric charges may be inferred from the updated neural network 185 . That is, charge data, which is very difficult to measure, can be inferred by learning the differential value of capacitance. Charge data can be inferred without training the neural network 185 by using the charge data directly.

Charge data for the second semiconductor device 103 or the third semiconductor device 105 may be inferred from the neural network 185 of the second enhancement model 180 .

In addition, the electric charge can be expressed as the following equation.

[Equation 5]

Q=∫Cdv

Wherein Q denotes a charge, ∫ denotes an integral symbol, C denotes capacitance, and dv denotes a change in voltage. That is, the electric charge can be expressed as the integral of the capacitance.

In order to update the parameters of the neural network 185 of the second enhancement model 180, the received charge data Q _{T2 of} the second semiconductor device 103 or the third semiconductor device 105, and the second semiconductor device ( 103), or the determined charge data of the third semiconductor device 105 are compared. In this case, each of the received charge data Q _T2 input for comparison and the determined charge data may be expressed as an integral expression of capacitance. That is, each of the received charge data Q _T2 and the determined charge data may be in an integral form.

The parameters of the neural network 185 are updated according to the comparison of the received charge data Q _{T2 expressed in the integral form with the determined charge data.}

After the training of the neural network 185 is finished, information about the capacitance may be inferred from the updated neural network 185 . Even if the neural network 185 is not trained using the capacitive data directly, inference of the capacitive data is possible.

After the training of the second neural network 175 is finished, the processor 11 applies a plurality of third voltage data sets of the second semiconductor device 103 to the second neural network 175 to generate a fifth in the second neural network 175 . Current data or fifth charge data is output. That is, the reasoning step of the neural network is performed.

According to an embodiment, after the training of the second neural network 175 is finished, the processor 11 includes a plurality of third voltage data sets of the second semiconductor device 103 in the second neural network 175 and the second semiconductor device ( 103), the fifth current data or the fifth charge data may be output from the second neural network 175 by applying the characteristic data sets.

According to an embodiment, the processor 11 applies a plurality of voltage data sets of the first semiconductor device 101 to the first neural network 160 after the training of the first neural network 160 is completed in the first neural network 160 . Current data or charge data can be output.

According to an embodiment, after the training of the first neural network 160 is finished, the processor 11 includes a plurality of voltage data sets of the first semiconductor device 101 and the first semiconductor device 101 in the first neural network 160 . Current data or charge data may be output from the first neural network 160 by applying the characteristic data sets of .

In addition, according to an embodiment, the processor 11 applies a plurality of voltage data sets of the third semiconductor device 105 to the neural network 185 after the training of the neural network 185 is completed to obtain current data from the neural network 185, or Charge data can be output.

According to an embodiment, after the training of the neural network 185 is finished, the processor 11 includes a plurality of voltage data sets of the third semiconductor element 105 and a characteristic data set of the third semiconductor element 105 in the neural network 185 . By applying them, current data or charge data may be output from the neural network 185 .

The compact model manager 190 includes a look up table (LUT) generator 191 , an open model interface (OMI) generator 192 , and a Verilog-A generator 193 . The LUT generator 191 converts the output output from the machine learning manager 140 into a table form. The result is a weight binary. The LUT generator 191 generates a lookup table indicating a relationship between the plurality of third voltage data sets of the second semiconductor device 103 and the fifth current data or the fifth charge data. According to an embodiment, the LUT generator 191 may generate a lookup table indicating a relationship between the plurality of voltage data sets of the first semiconductor device 101 , the current data, or the charge data. Also, according to an embodiment, the LUT generator 191 may generate a lookup table indicating a relationship between the plurality of voltage data sets of the third semiconductor device 105 and the current data or the charge data. A compact model 220 may be output based on the lookup table.

The OMI generator 192 generates the result output from the machine learning manager 140 or the lookup table generated by the LUT generator 191 as OMI (Open Model Interface) so that the SPICE simulator can understand the compact model 220 . provided with The OMI generator 192 generates a result representing a relationship between the plurality of voltage data sets of the third semiconductor device 105, the current data, or the charge data as an Open Model Interface (OMI), and a neural network is applied output as a model. When the OMI generator 192 generates the lookup table as an OMI, the first compact model 221 is provided. When the OMI generator 192 generates the output output from the machine learning manager 140 as OMI, the second compact model 223 is provided. The first compact model 221 or the second compact model 223 is one of several types of the compact model 220 . The Verilog-A generator 193 generates the lookup table generated by the LUT generator 191 or the output output from the machine learning manager 140 as an interface implemented in Verilog-A so that the SPICE simulator can understand it, Model 220 is provided. The Verilog-A generator 193 generates a result representing the relationship between the plurality of voltage data sets of the third semiconductor device 105 and the current data or the charge data as an interface implemented in Verilog-A. and output as a Compaq model to which the neural network is applied.

The output output from the machine learning manager 140 is expressed as a weight binary. When the Verilog-A generator 193 generates the lookup table as an interface implemented in Verilog-A, the third compact model 225 is provided. When the verilog-A generator 193 generates the output output from the machine learning manager 140 as an interface implemented in verilog-A, the fourth compact model 227 is provided. The third compact model 225 or the fourth compact model 227 is one of several types of the compact model 220 . According to an embodiment, the compact model 220 may be provided in any one of various forms 221 , 223 , 225 , or 227 .

It should be understood that operations of the data converter 120 , the learning environment manager 130 , the machine learning manager 140 , and the compact model 190 in the present invention are performed by the processor 11 .

FIG. 7 shows a graph regarding capacitance data deduced from the first enhancement model shown in FIG. 2 and a graph regarding charge data deduced from the second enhancement model illustrated in FIG. 2 .

FIG. 7( a ) shows a graph regarding capacitance data inferred from the first improvement model shown in FIG. 2 . In the graph, the X-axis represents the gate-source voltage (Vgs) and the Y-axis represents the capacitance.

Referring to FIGS. 2, 5, and 7A , after the neural network 175 of the first enhancement model 170 is trained, inferred values for capacitance data of an arbitrary semiconductor device are shown. The arbitrary semiconductor device may be the second semiconductor device 103 , the third semiconductor device 105 , or another semiconductor device.

Referring to FIG. 7A , it can be seen that the actual capacitance data and the inferred capacitance data match. That is, the capacitance data is accurately inferred.

7(b) shows a graph regarding charge data deduced from the second improvement model shown in FIG. 2 . In the graph, the X-axis represents the gate-source voltage (Vgs), and the Y-axis represents the charge.

2, 5, and 7(b) , after the neural network 185 of the second enhancement model 180 is trained, inferred values for charge data of the arbitrary semiconductor device are shown. The arbitrary semiconductor device may be the second semiconductor device 103 , the third semiconductor device 105 , or another semiconductor device. The neural network 185 of the second enhancement model 180 compares the capacitance data expressed as a rate of change of electric charge with respect to a change of voltage to learn the neural network 185 . That is, the neural network 185 is trained in the form of differentiation. Referring to FIG. 7(b) , it can be inferred that charge data, which is very difficult to measure, is inferred.

FIG. 8 shows a graph regarding charge data deduced from the first enhancement model shown in FIG. 2 and a graph regarding capacitance data deduced from the second enhancement model illustrated in FIG. 2 .

FIG. 8( a ) shows a graph regarding charge data deduced from the first improvement model shown in FIG. 2 . In the graph, the X-axis represents the gate-source voltage (Vgs), and the Y-axis represents the charge.

2, 5, and 8 (a), after the neural network 175 of the first enhancement model 170 is trained, inferred values for the capacitance data of an arbitrary semiconductor device are shown. The arbitrary semiconductor device may be the second semiconductor device 103 , the third semiconductor device 105 , or another semiconductor device.

Referring to FIG. 8( a ), it can be seen that the actual charge data and the inferred charge data match. That is, the charge data is accurately inferred. The charge is very small and difficult to measure, but it can be obtained from TCAD (Technology CAD).

8(b) shows a graph regarding capacitance data inferred from the second improvement model shown in FIG. 2 . In the graph, the X-axis represents the gate-source voltage (Vgs), and the Y-axis represents the charge.

2, 5, and 8(b) , after the neural network 185 of the second enhancement model 180 is trained, inferred values for the capacitance data of the arbitrary semiconductor device are shown. The arbitrary semiconductor device may be the second semiconductor device 103 , the third semiconductor device 105 , or another semiconductor device. The neural network 185 of the second enhancement model 180 compares charge data expressed as an integral of the capacitance of the electric charge, and the neural network 185 is trained. That is, the neural network 185 may be trained in the form of an integral.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

10: semiconductor device modeling system;
11: processor;
13: memory;
110: data;
120: data converter;
130: learning environment manager;
140: machine learning manager;
150: base model;
170: first improvement model;
180: second enhancement model;

Claims (22)

In the semiconductor device modeling method of the semiconductor device modeling system (10) comprising a memory (13) for storing instructions and a processor (11) for executing the instructions,
The processor 11 includes a plurality of first voltage data sets V ₁ , V ₂ , V ₃ of a first semiconductor device to train a first neural network 150 , and a first capacitance ) receiving first training data sets 110 including data C _T , first current data I _T , or first charge data Q _{T ;}
The processor applies the plurality of first voltage data sets 110 to the input of the first neural network 150 to obtain second capacitance data C _O , second current data I _O , or a second determining charge data (Q _O );
The processor includes the received first capacitance data (C _T ), the received first current data ( _IT ), or the first charge data (Q _T ), and the determined second capacitance data (C _{O )} ), updating the parameters of the first neural network 150 according to the comparison of the determined second current data (I _O ), or the determined second charge data (Q _{O );}
The processor converts at least one of the parameters to the second neural network (175, 185) in order to reuse (reuse) at least one of the updated parameters of the first neural network (150) in the second neural network (175, 185) 185);
The processor is configured to train the second neural networks 175 and 185 with a plurality of second voltage data sets V ₄ , V ₅ , V ₆ , or V ₇ , V ₈ , V ₉ of a second semiconductor device and , third capacitive data (C _T2 , or C _T3 ), third current data (I _T2 , or I _T3 ), or third charge data (Q _T2 , or Q _T3 ). receiving;
Wherein the processor is a fourth capacitive data (not shown), a fourth current data (not shown), or the fourth charge is applied to the input of said second neural network (175, 185) to the plurality of second voltage data set determining data (not shown); and
The processor is configured to configure the received third capacitive data C _T2 , or C _T3 , the received third current data I _T2 , or I _T3 , or the received third charge data Q _T2 , or Q _T3 ) and the determined fourth capacitance data (not shown), the determined fourth current data (not shown), or the determined fourth charge data according to the comparison of the parameters of the second neural network 175 or 185 A method for modeling a semiconductor device in a semiconductor device modeling system, comprising updating them. The method of claim 1 , wherein the semiconductor device modeling method of the semiconductor device modeling system comprises:
setting, by the processor, a target function to automatically set a hyperparameter of the first neural network or the second neural network, and an acquisition function representing a standard deviation of the target function according to a hyperparameter variable;
The processor arbitrarily selects the hyperparameter variable and applies the randomly selected hyperparameter variable to the first neural network or the second neural network to output a loss value indicating a difference between an output value and a target value. performing;
performing, by the processor, a calculation operation of calculating a standard deviation of the target function according to the arbitrary selected hyperparameter variable in the acquisition function;
performing, by the processor, a correction operation of modifying the target function according to the output loss value and the standard deviation calculated by the acquisition function; and
The processor repeatedly performs the output operation, the calculation operation, and the correction operation until convergence, and as a result of the execution, the hyperparameter variable when the loss value is the minimum of the first neural network or the second neural network A semiconductor device modeling method of a semiconductor device modeling system further comprising the step of setting a hyperparameter. The method according to claim 1, wherein each of the received third capacitive data (CT2, or CT3) and the determined fourth capacitive data comprises:
It is expressed as the rate of change of charge with respect to change of voltage,
A method for modeling a semiconductor device in a semiconductor device modeling system in which parameters of the second neural network are updated according to a comparison of the received third capacitance data and the determined fourth capacitance data expressed as a change rate of charge with respect to a change in voltage . 4. The method of claim 3, wherein charge data is inferred from the updated second neural network according to a comparison of the received third capacitive data expressed as a rate of change of charge with respect to the change of voltage and the determined fourth capacitive data. A semiconductor device modeling method in a semiconductor device modeling system. According to claim 1, wherein each of the received third charge data and the determined fourth charge data,
It is expressed as the integral of the capacitance,
A method for modeling a semiconductor device in a semiconductor device modeling system in which parameters of the second neural network are updated according to a comparison between the received third charge data expressed as an integral of the capacitance and the determined fourth charge data. The semiconductor device modeling system of claim 5 , wherein capacitance data is inferred from the updated second neural network according to a comparison of the received third charge data expressed as an integral of the capacitance and the determined fourth charge data. of semiconductor device modeling methods. The method of claim 1 , wherein the parameters are
contains a weight matrix and a bias vector,
A method for modeling a semiconductor device in a semiconductor device modeling system in which a part of weight matrices and bias vectors included in the first neural network and a part of weight matrices and bias vectors included in the second neural network are common. The method of claim 1 , wherein at least one of the first capacitance data, the first current data, and the first charge data is selected by a user of the semiconductor device modeling system. . The method of claim 1 , wherein the semiconductor device modeling method of the semiconductor device modeling system comprises:
After training of the second neural network is finished, the processor applies a plurality of third voltage data sets of the second semiconductor device to the second neural network to infer fifth current data or fifth charge data from the second neural network. to do; and
The processor generates a lookup table representing a relationship between a plurality of third voltage data sets of the second semiconductor device, fifth current data, or fifth charge data, and based on the lookup table, a neural network is applied as a compact model. A semiconductor device modeling method of a semiconductor device modeling system further comprising the step of outputting. The method of claim 1 , wherein the semiconductor device modeling method of the semiconductor device modeling system comprises:
After training of the second neural network is finished, the processor applies a plurality of third voltage data sets of the second semiconductor device to the second neural network to infer fifth current data or fifth charge data from the second neural network. to do; and
and outputting, by the processor, a result representing a relationship between a plurality of third voltage data sets of the second semiconductor device, fifth current data, or fifth charge data as a compact model to which a neural network is applied. A method of modeling a semiconductor device in a modeling system. The method of claim 1 , wherein the semiconductor device modeling method of the semiconductor device modeling system comprises:
receiving, by the processor, characteristic data sets of the first semiconductor device or characteristic data sets of the second semiconductor device to train the first neural network or the second neural network;
The processor is configured to use the received plurality of first voltage data sets of the first semiconductor device and characteristic data sets of the first semiconductor device to obtain the second capacitance data, the second current data, or a second determining charge data; and
The processor is configured to use the plurality of second voltage data sets of the received second semiconductor device and characteristic data sets of the second semiconductor device to generate the fourth capacitance data, the fourth current data, or a fourth charge. The method of modeling a semiconductor device of a semiconductor device modeling system further comprising the step of determining the data. a memory storing instructions; and
a processor for executing the instructions;
The commands are
In order to train a first neural network 150 , a plurality of first voltage data sets V ₁ , V ₂ , V ₃ of a first semiconductor device and a first capacitance data C _T ) , a first current data ( _IT ), or a first charge data (Q _T ) to receive the first training data sets 110 including,
By applying the plurality of first voltage data sets 110 to the input of the first neural network 150, second capacitance data (C _O ), second current data ( _IO ), or second charge data ( Q _O ) is determined,
The received first capacitance data (C _T ), the received first current data (I _T ), or the first charge data (Q _T ), the determined second capacitance data (C _O ), the Updating the parameters of the first neural network 150 according to the comparison of the determined second current data (I _O ), or the determined second charge data (Q _{O ),}
In order to reuse at least one of the updated parameters of the first neural network 150 in the second neural networks 175 and 185, at least one of the parameters is transferred to the second neural networks 175 and 185. convey,
In order to train the second neural networks 175 and 185, a plurality of second voltage data sets V ₄ , V ₅ , V ₆ , or V ₇ , V ₈ , V ₉ of a second semiconductor device and a third receiving second training data sets comprising capacitive data (C _T2 , or C _T3 ), third current data (I _T2 , or I _T3 ), or third charge data (Q _T2 , or Q _{T3 ),}
By applying the plurality of second voltage data sets to the inputs of the second neural networks 175 and 185, fourth capacitance data (not shown), fourth current data (not shown), or fourth charge data (not shown) ) to determine
The received third capacitive data (C _T2 , or C _T3 ), the received third current data (I _T2 , or I _T3 ), or the received third charge data (Q _T2 , or Q _T3 ) and , to update the parameters of the second neural network 175 or 185 according to a comparison of the determined fourth capacitance data (not shown), the determined fourth current data (not shown), or the determined fourth charge data. Implemented semiconductor device modeling system. 13. The method of claim 12, wherein the instructions:
setting a target function to automatically set hyperparameters of the first neural network or the second neural network, and an acquisition function representing a standard deviation of the target function according to hyperparameter variables,
arbitrarily selecting the hyperparameter variable and applying the arbitrarily selected hyperparameter variable to the first neural network or the second neural network to output a loss value indicating a difference between an output value and a target value;
performing a calculation operation of calculating a standard deviation of the target function according to an arbitrary selected hyperparameter variable in the acquisition function;
performing a correction operation of correcting the target function according to the output loss value and the standard deviation calculated in the acquisition function,
The output operation, the calculation operation, and the correction operation are repeatedly performed until convergence, and as a result of the execution, the hyperparameter variable when the loss value is minimum is used as a hyperparameter of the first neural network or the second neural network. A semiconductor device modeling system implemented to set up. 13. The method of claim 12, wherein each of the received third capacitive data (CT2, or CT3) and the determined fourth capacitive data comprises:
It is expressed as the rate of change of charge with respect to change of voltage,
A semiconductor device modeling system in which parameters of the second neural network are updated according to a comparison of the received third capacitive data expressed as a rate of change of electric charge with respect to the change of voltage and the determined fourth capacitive data. 15. The method of claim 14, wherein charge data is inferred from the updated second neural network according to a comparison of the received third capacitance data expressed as a rate of change of charge with respect to the change of voltage and the determined fourth capacitance data. Semiconductor device modeling system. The method of claim 12, wherein each of the received third charge data and the determined fourth charge data comprises:
It is expressed as the integral of the capacitance,
A semiconductor device modeling system in which parameters of the second neural network are updated according to a comparison between the received third charge data expressed as an integral of the capacitance and the determined fourth charge data. The semiconductor device modeling system of claim 16 , wherein capacitance data is inferred from the updated second neural network according to a comparison of the received third charge data expressed as an integral of the capacitance and the determined fourth charge data. . 13. The method of claim 12, wherein the parameters are
contains a weight matrix and a bias vector,
A semiconductor device modeling system in which parts of weight matrices and bias vectors included in the first neural network and parts of weight matrices and bias vectors included in the second neural network are common. The semiconductor device modeling system of claim 12 , wherein any one of the first capacitance data, the first current data, and the first charge data is selected by a user of the semiconductor device modeling system. 13. The method of claim 12, wherein the instructions:
After the training of the second neural network is finished, inferring fifth current data or fifth charge data from the second neural network by applying a plurality of third voltage data sets of the second semiconductor device to the second neural network,
A lookup table representing the relationship between a plurality of third voltage data sets of the second semiconductor device, fifth current data, or fifth charge data is generated, and based on the lookup table, it is implemented to output as a compact model to which a neural network is applied. semiconductor device modeling system. 13. The method of claim 12, wherein the instructions:
After the training of the second neural network is finished, inferring fifth current data or fifth charge data from the second neural network by applying a plurality of third voltage data sets of the second semiconductor device to the second neural network,
A semiconductor device modeling system configured to output a result representing a relationship between a plurality of third voltage data sets of the second semiconductor device, fifth current data, or fifth charge data as a compact model to which a neural network is applied. 13. The method of claim 12, wherein the instructions:
receiving characteristic data sets of the first semiconductor device or characteristic data sets of the second semiconductor device for training the first neural network or the second neural network;
The second capacitance data, the second current data, or the second charge data are generated using the received plurality of first voltage data sets of the first semiconductor device and characteristic data sets of the first semiconductor device. decide,
Determine the fourth capacitance data, the fourth current data, or the fourth charge data by using the plurality of second voltage data sets of the received second semiconductor device and characteristic data sets of the second semiconductor device A semiconductor device modeling system implemented to do so.

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