KR101760688B1 - Power Semiconductor Device And Method of Manufacturing The same - Google Patents

Abstract

To a power semiconductor device and a manufacturing method thereof. The power semiconductor device of the present embodiment includes a semiconductor substrate having an active region and a termination region defined therein, a first trench formed on the semiconductor substrate and corresponding to the active region, a first trench formed in a boundary portion between the active region and the termination region, A drift region having at least one second trench formed in the first trench and a third trench formed in a portion corresponding to the termination region, a Schottky diode semiconductor layer formed in the first trench, A guard ring, a conductive spacer remaining on the sidewalls of the third trench, and a bridge configured to electrically connect the Schottky diode semiconductor layer, the guard ring, and the conductive spacer in the drift region.

Description

TECHNICAL FIELD [0001] The present invention relates to a power semiconductor device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device and a method of manufacturing the same, and more particularly, to a power semiconductor device and a manufacturing method thereof capable of improving breakdown voltage and current driving capability.

As the power conversion apparatus is being reduced in power consumption, expectation for lower power consumption of a power semiconductor device that plays a central role in the power conversion apparatus is increasing. At present, the use of an insulated gate bipolar transistor (IGBT) which can attain a low on-voltage by the conductivity modulation effect and which is easy to control the gate is settled. By using the IGBT, a high breakdown voltage can be ensured and the switching speed can be improved. It is known that when the IGBT element is turned on, a large amount of Electro Magnetic Interference (EMI) noise is generated. Currently, a high-speed diode such as a schottky diode is integrated with an IGBT in order to solve the above-mentioned EMI problem and ensure high-speed switching characteristics.

On the other hand, the power semiconductor device may include a drift region having carriers of the same type as the semiconductor substrate. The concentration and the thickness of the drift region are known to affect on-resistance and breakdown voltage characteristics of a power semiconductor device. However, since the ON resistance characteristic and the breakdown voltage characteristic of the power semiconductor device are in a trade-off relationship with respect to the concentration and the thickness of the drift region, researches for simultaneously satisfying both characteristics have continued .

As one of such schemes, a structure has been proposed in which a trench is formed in a drift region and a Schottky diode is formed in the trench.

However, there is a problem that the electric field is concentrated at the boundary between the active region and the termination region in which the Schottky diode and the power semiconductor device are formed, thereby deteriorating the breakdown voltage characteristic.

The present invention provides a power semiconductor device capable of improving breakdown voltage characteristics and a method of manufacturing the same.

A power semiconductor device according to an embodiment of the present invention includes a semiconductor substrate having an active region and a termination region defined therein, a first trench formed on the semiconductor substrate, a first trench formed in a portion corresponding to the active region, A drift region having at least one second trench formed in a portion corresponding to a boundary portion of the first trench and a third trench formed in a portion corresponding to the termination region, a Schottky diode semiconductor layer formed in the first trench, A guard ring formed in the second trench, a conductive spacer remaining on the sidewall of the third trench, and a bridge configured to electrically connect the semiconductor layer for the Schottky diode, the guard ring, and the conductive spacer in the drift region .

In addition, a method of manufacturing a power semiconductor device according to another embodiment of the present invention provides a semiconductor substrate including an active region, a termination region, and a boundary region between the active region and the termination region. Next, a drift region is formed on the semiconductor substrate. Forming a first trench in the active region by etching the drift region, forming a second trench in the boundary region, forming a third trench in the termination region, and forming a second trench in the first to third trenches, Thereby forming a bridge trench for electrically connecting the bridge trenches. A liner insulating film is formed on the surfaces of the first to third trenches and the bridge trenches, a conductive layer is buried in the first to third trenches and the bridge trenches, and a semiconductor layer of the Schottky diode, And a bridge. Thereby forming a field plate which is selectively in contact with the semiconductor layer of the Schottky diode.

According to the present invention, the semiconductor layer of the Schottky diode, the guard ring formed on the interface between the active region and the termination region, and the conductive spacers that can remain on the sidewall of the termination region are electrically connected by the bridge to form a leakage current source and an applied voltage And the cause of the lowering of the breakdown voltage due to the increase of the electric field can be eliminated. Thus, the breakdown voltage of the power semiconductor device can be improved.

During the step of forming the semiconductor layer of the Schottky diode, excessive etching proceeds to expose the sidewalls of the trench in which the semiconductor layer of the Schottky diode is formed. As a result, the Schottky junction area can be increased, and the current driving capability of the power semiconductor device can be improved.

1 is a plan view of a power semiconductor device according to an embodiment of the present invention.
2 is a cross-sectional view taken along line II-II 'of FIG.
3 is a cross-sectional view taken along line III-III 'of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification.

1 is a plan view of a power semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor substrate 100 on which a power semiconductor device is formed may be divided into an active region A and a termination region B.

The active region A may include a plurality of trench power MOSFETs (not shown), a plurality of trench IGBT devices (not shown) and a plurality of trench Schottky diodes 106a, such as a plurality of trench power MOSFETs Semiconductor devices. The plurality of Schottky diodes 106a may be formed in the first trench having the first line width provided in the semiconductor substrate 100, as will be described later in detail. Although the Schottky diode 106a is formed in the form of a frame having the first line width in the drawing, it is needless to say that the Schottky diode 106a may be implemented in the form of a stripe pattern or a dot pattern.

The termination region B may be provided to define the active region A in the semiconductor substrate 100. For example, the termination region B may be composed of a trench having a line width larger than the first trench.

A plurality of guard rings 106b may be provided in the boundary region between the active region A and the termination region B. [ A plurality of guard rings 106b may be formed to surround the periphery of the active region A. [ The plurality of guard rings 106b may be spaced apart from each other at a predetermined interval. In addition, each of the plurality of guard rings 106b may be embodied by embedding a conductive material in the trenches, thereby alleviating the electric field concentration on the interface between the active region A and the termination region B. Reference numeral 106c and 106d may denote a conductive spacer as the outermost guard ring remaining at the edge of the termination region B and Br_106 may denote a Schottky diode 106a, a plurality of guard rings 106b and a conductive spacer 106c Indicates the bridge for electrical connection. Reference numeral 112 denotes a field plate formed on the active region A and the termination region B. Here, the conductive spacers 106c and 106d corresponding to the outermost guard ring may have a line width of 1 to 200 mu m, more preferably 5 to 45 mu m.

FIG. 2 is a sectional view taken along line II-II 'of FIG. 1, and FIG. 3 is a sectional view taken along a line III-III' of FIG. The structure and manufacturing method of the power semiconductor device according to the embodiment of the present invention will be described in more detail with reference to FIGS. 2 and 3. FIG.

First, referring to FIGS. 1 to 3, a semiconductor substrate 100 having an active region A and a termination region B is prepared. The semiconductor substrate 100 may be, for example, a silicon substrate containing an impurity of the first conductivity type, for example, an n-type impurity. The drift region 102 can be formed by implanting the low concentration first conductivity type impurity into the semiconductor substrate 100. [ At this time, the drift region 102 may have a concentration higher than the impurity concentration of the semiconductor substrate 100.

A first trench T1 is formed in the active region A by partially etching the drift region 102 of each of the active region A and the termination region B to form the active region A and the termination region B And the third trenches T2 and T3 are formed in the termination region C. The third trenches T2 and T3 are formed in the termination region C as shown in FIG. The second trench T2 may be formed to have the same width as the first trench T1 and the third trench T3 may be formed to have a wider width than the first and second trenches T1 and T2. have. The first to third trenches T1, T2, and T3 may be formed through a known photolithography process and an etching process.

Meanwhile, when forming the first to third trenches T1, T2, and T3, a bridge trench Br_T connecting the first to third trenches T1, T2, and T3 may be further formed. The bridge trench Br_T may be implemented, for example, substantially perpendicular to the first to third trenches T1, T2, and T3. Since such a bridge trench Br_T is formed simultaneously with the first to third trenches T1, T2 and T3, no additional process for forming the bridge trench Br_T is required. Since the bridge trench Br_T is formed to be in communication with the first to third trenches T1, T2 and T3 at the same time, when the bridge trench Br_T is cut along the line III-III 'of FIG. 1 (FIG. 3) Br_T and the first to third trenches T1, T2 and T3 can be viewed as one trench.

The liner insulating film 104 is formed on the surface of the resultant semiconductor substrate 100 on which the first to third trenches T1, T2, and T3 are formed. The liner insulating film 104 can be used as a gate insulating film in a region where the power MOSFET or the IGBT element of the active region A is formed. As such a liner insulating film 104, for example, a silicon oxide film may be used.

A conductive layer may be formed on the resultant product of the semiconductor substrate 100 on which the liner insulating film 104 is formed. The conductive layer may be a gate material of a power MOSFET or an IGBT formed in the active region (A), and may be a high concentration semiconductor layer or a metal film constituting a Schottky diode. Such a conductive layer may be, for example, a polysilicon film containing a high concentration first conductivity type impurity, but the present invention is not limited thereto, and a semiconductor film showing conductivity can be included here. For example, since the conductive layer is deposited targeting the gate thickness of the IGBT, it is filled in the first and second trenches T1 and T2 and the bridge trench Br_T having a relatively narrow line width, The third trench T3 having a wide line width can be deposited along the inner wall of the third trench T3. The conductive layer may be formed by a deposition method such as LPCVD (low voltage), which can achieve excellent step coverage so that the conductive layer can be completely filled without voids in the first and second trenches T1 and T2 and the bridge trench Br_T. pressure chemical vapor deposition (PECVD) or plasma enhanced chemical vapor deposition (PECVD).

The conductive layer may be etched to define a gate (not shown), a Schottky diode semiconductor layer 106a, a guard ring 106b, and a bridge (Br_106). The gate may be formed using a mask in a part of the active region (A). The semiconductor layer 106a, the guard ring 106b and the bridge Br_106 of the Schottky diode are formed in the first trench T1 and the second trench Tb1 using an anisotropic blanket etching or an anisotropic etch- T2, and inside the bridge trench Br_T, respectively. In this anisotropic etching process, the conductive layer may remain in the form of a spacer on the sidewall of the third trench T3.

The semiconductor layer 106a of the Schottky diode, the guard ring 106b and the conductive spacer 106b remaining on the sidewall of the third trench T3 may be partially electrically connected by the bridge Br_106.

On the other hand, during an anisotropic blanket etch or anisotropic etch back process to form the semiconductor layer 106a, the guard ring 106b and / or the conductive spacers 106c of the Schottky diode, the conductive layer is excessively etched Lt; / RTI > Accordingly, the upper sidewalls of the first to third trenches T1, T2, and T3 can be partially exposed. In addition, the transient etching may be selectively performed on the semiconductor layer 106a of the Schottky diode.

The interlayer insulating film 108 may be formed on the semiconductor substrate 100 on which the semiconductor layer 106a of the Schottky diode, the guard ring member 106b and / or the conductive spacer 106c are formed. The interlayer insulating film 108 may be partially etched to expose the Schottky diode semiconductor layer 106a and its peripheral portion in the first trench T1.

A metal layer may be deposited on the upper surface of the interlayer insulating film 108 and the back surface of the semiconductor substrate 100 to form the field plate 112 and the cathode electrode 114 as the anode electrode.

A part of the field plate 112 is contacted with the Schottky diode semiconductor layer 106a to form a Schottky junction J. [ Since the Schottky diode semiconductor layer 106a is formed to have a thickness shallower than the depth of the first trench T1, the Schottky junction J is formed on the surface of the Schottky diode semiconductor layer 106a as well as on the surface of the first trench T1 ), The Schottky junction area is increased. Thus, the Schottky diode 106a with greatly improved current density and current driving capability can be formed.

On the other hand, as electrical signals are applied to the guard ring 106b and the conductive spacer 106c through the field plate 112, the leakage current can be greatly reduced.

Generally, the guard ring formed in the termination region B is formed to prevent electric field overcorrection. However, since the conventional guard ring and the conductive spacer inevitably generated are in a floating form despite having conductivity, In the United States. As a result, the breakdown voltage of the power semiconductor device is affected.

In the embodiment of the present invention, the bridge Br_106 is formed in the drift region 102 between the semiconductor layer 106a, the guard ring 106b and the conductive spacer 106b of the Schottky diode, To the guard ring 106b and the conductive spacer 106b, which have been served as a leakage current source. As a result, the leakage current source can be removed originally.

According to the present invention, during the step of forming the semiconductor layer of the Schottky diode, excessive etching proceeds to expose the sidewall of the trench in which the semiconductor layer of the Schottky diode is formed. As a result, the Schottky junction area can be increased, and the current driving capability of the power semiconductor device can be improved.

Also, the leakage current source can be removed by electrically connecting the semiconductor layer of the Schottky diode, the guard ring formed on the interface between the active region and the termination region, and the conductive spacer remaining on the sidewall of the termination region by the bridge.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but variations and modifications may be made without departing from the scope of the present invention. Do.

100: semiconductor substrate 106a: Schottky diode
106b: guard ring 106c: conductive spacer
106a: Schottky diode

Claims (5)

A semiconductor substrate having an active region and a termination region defined therein;
A first trench formed on the semiconductor substrate and corresponding to the active region, at least one second trench formed in a portion corresponding to a boundary portion between the active region and the termination region, A drift region having a third trench formed in the portion;
A Schottky diode semiconductor layer formed in the first trench;
A guard ring formed in the second trench;
A conductive spacer remaining on a sidewall of the third trench; And
A semiconductor layer for the Schottky diode, the guard ring, and a bridge configured to electrically connect the conductive spacer in the drift region. The method according to claim 1,
Wherein the Schottky diode semiconductor layer is formed at a height at which an upper sidewall portion of the first trench is exposed. 3. The method of claim 2,
A field plate formed on an upper surface of the semiconductor substrate, the field plate being in electrical contact with a semiconductor layer of the Schottky diode and a sidewall of the first trench; And
And a cathode electrode formed on a back surface of the semiconductor substrate. Providing a semiconductor substrate comprising an active region, a termination region, and a boundary region between the active region and the termination region;
Forming a drift region on the semiconductor substrate;
Forming a first trench in the active region by etching the drift region, forming a second trench in the boundary region, forming a third trench in the termination region, and forming a second trench in the first to third trenches, Forming a bridge trench for electrically connecting the bridge trench;
Forming a liner insulating film on the surfaces of the first to third trenches and the bridge trenches;
Burying a conductive layer in the first to third trenches and the bridge trench to form a semiconductor layer, a guard ring, a conductive spacer, and a bridge of the Schottky diode; And
And forming a field plate that is selectively in contact with the semiconductor layer of the Schottky diode. 5. The method of claim 4,
Wherein forming the semiconductor layer of the Schottky diode comprises:
Performing an anisotropic blanket etch or transient etch back process to expose the conductive layer to the side walls of the first trench,
Wherein the field plate is in contact with the semiconductor layer of the Schottky diode and is electrically in contact with the drift region corresponding to the sidewall of the first trench.

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