KR101713580B1 - Apparatus and method for monitoring quality of chip mounter processing - Google Patents

Abstract

An apparatus and method for monitoring quality of a chip mounter process are provided. An apparatus for monitoring quality of a chip mounter process according to an embodiment of the present invention includes: a pickup unit for picking up a chip and mounting the chip on a substrate; A detecting unit for supplying electric power through the pick-up unit to detect a level of energization of the chip and the substrate; And a determination unit that determines both sides of the chip mounting based on the energization level detected by the detection unit.

Description

[0001] Apparatus and method for monitoring quality of a chip mounter process [0002]

The present invention relates to an apparatus and method for monitoring quality of a chip mounter process, and more particularly, to an apparatus and method for monitoring the quality of a chip mounter process in real time by supplying electric power to a pick-up unit when picking up a chip.

A flip-chip process is a technique of bumping a substrate of a die, which is a semiconductor chip, to a substrate instead of a wire bonding technique of connecting a conventional semiconductor chip and a lead frame with wires.

A plurality of pins are bonded to the pads at a time through the flip chip package to improve the productivity. However, since the state of the solder balls or bumps formed on the pad determines whether the soldering process is defective or not, Is required.

For this purpose, there is a method of determining whether or not the chip is correctly mounted using an X-ray image before the chip mounter passes through a reflow process after mounting, And the die tilt (chip inclination) or the like can not be detected.

In addition, there is a method of determining whether or not the chip is mounted by inspecting the position of the mounted chip using a fiducial camera provided in the chip mount after chip mounting, And there is also a problem that a die tilt or the like can not be detected.

In addition, there is a destructive inspection that directly detects the quality of the material that has passed through the reflow process. However, the destruction of the material is accompanied by the destruction of the material, and production is stopped until the completion of the inspection and the influence of reflow is not detected There is a problem that can not be done.

SUMMARY OF THE INVENTION The present invention provides a device and method for monitoring quality of a chip-mounter process, in which an electric signal is supplied when a chip mounter is mounted on a chip to judge whether or not the chip is mounted in real time.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided an apparatus for monitoring quality of a chip mounter process, comprising: a pickup unit for picking up a chip and mounting the chip on a substrate; And the other terminal is connected to the substrate so that when the chip is mounted on the substrate and electrically connected to the chip, electricity is supplied to the chip through the pick-up unit to supply the supplied electricity to the substrate A detection unit for detecting a level of energization of the chip and the substrate by outputting the detection signal; And a determination unit for determining the amount of mounting of the chip on the substrate based on the energization level detected by the detection unit.

According to an aspect of the present invention, there is provided a method of monitoring quality of a chip mounter process, the chip being mounted on a substrate by picking up a chip. Wherein when the chip is mounted on and electrically connected to the substrate, the chip is supplied with electricity, and the supplied electricity is supplied to the substrate through the chip, and electricity supplied from the chip is sent through the substrate, Detecting a level of energization of the chip and the substrate; And determining whether the chip is mounted on the substrate based on the detected energization level.

Other specific details of the invention are included in the detailed description and drawings.

According to the present invention, when a chip is mounted on a substrate in a chip-mounter process, an electrical signal is given to check the quality of chip mounting in real time.

In addition, it is possible to prevent the loss of the working time by checking the quality of the mounting without interrupting the chip-mounter process, and to improve the productivity by improving the working efficiency.

In addition, it is possible to prevent damage and destruction of the material by the conventional destructive inspection and the like, thereby reducing the cost.

1A is a perspective view of a chip mounter mounting a chip on a substrate, and Figs. 1B and 1C are side views showing a mounting state between the chip and the substrate.
2 is a block diagram of a quality monitoring apparatus for a chip mounter process according to an embodiment of the present invention.
Figs. 3A to 3C are schematic diagrams showing the mounting state between the chip and the substrate.
4 is a method for monitoring quality of a chip mounter process according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms "comprises" and / or "made of" means that a component, step, operation, and / or element may be embodied in one or more other components, steps, operations, and / And does not exclude the presence or addition thereof.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1A is a perspective view of a chip mounter mounting a chip on a substrate, and Figs. 1B and 1C are side views showing a mounting state between the chip and the substrate.

1A, a pick-up nozzle 12 provided in a pickup 10, which is a part of a chip mounter, picks up a chip 20 and mounts the chip 20 on the substrate 30. [ Here, the pickup unit 10 includes at least one pickup nozzle 12, and one pick-up nozzle 12 picks up one chip 20. 1A shows only one pick-up nozzle 12 in one pick-up unit 10, but generally one pick-up unit 10 is provided with a plurality of pick-up nozzles 12.

1B, a state in which the chip 20 is in contact with the substrate 30 is shown. The chip 20 has a plurality of chip bumps 22. Further, the substrate 30 has a unit mounting region 31 in which one chip 20 is mounted. The portion where the chip bumps 22 are in contact becomes the electrically conductive layer 32 and the remaining portion becomes the insulating layer 34. [ In general, the insulating layer 34 uses a PSR (Photo Imageable Solder Regist), and supports the chip bump 22 with a short prevention between patterns through the PSR. In particular, the conductive layer 32 may be recessed in a region where the chip bumps 22 are engraved.

In Fig. 1C, the structure of the substrate 30 is different from that of Fig. 1B. A conductive layer 32 in which the chip bumps 22 are in contact with the unit mounting region 31 of the substrate 30 on which one chip 20 is mounted and an insulating layer 34 for preventing a short circuit between the patterns are provided , And the conductive layer 32 are formed by being embossed.

2 is a block diagram of a quality monitoring apparatus for a chip mounter process according to an embodiment of the present invention.

The apparatus for monitoring the quality of the chip mounter process includes a pickup unit 10, a detection unit 40, and a determination unit 50.

The pick-up unit 10 picks up the chip 20 and mounts the chip 20 on the substrate 30. The pick-up unit 10 includes at least one pick-up nozzle 12 for picking up the chip 20 by picking up the chip. The pick-up nozzle 12 provided in the pick-up unit 10 sucks the chip 20 using air pressure and releases the air pressure on the substrate 30 to mount the chip 20 on the substrate 30. [

Here, the chip 20 includes a plurality of chip bumps 22, so that the electrodes of the chip 20 and the substrate 30 are connected to the chip bumps 22.

The detection unit 40 detects the energization level between the chip 20 and the substrate 30 by supplying electricity through the pickup unit 10. [ Therefore, the pickup unit 10, the chip 20, and the substrate 30 are electrically connected. In particular, the detection unit 40 may include an electric power supply module (not shown) for supplying electric power to the pickup unit 10. [ However, it may be provided not only in the case where the electric power supply module is included in the detection portion 40, but also in the pickup portion 10 and the like. In general, the electric power supply module may be a voltage source or a current source, but is not limited thereto.

The energization between the chip 20 and the substrate 30 is carried out when the chip 20 and the substrate 30 are brought into contact with each other and the chip 20 includes a plurality of chip bumps 22, A conductive layer 32 corresponding to one-to-one must be provided on the substrate 30. [ The conductive layer 32 may be embossed or embossed with respect to the insulating layer 34 of the substrate 30. Therefore, the substrate 30 includes a plurality of substrate bumps 32 or a plurality of chip bumps 22 provided on the chip 20, the plurality of chip bumps 22 provided on the chip 20, And has a plurality of recessed grooves 32 of recessed shape which are seated and brought into contact with each other.

The level of energization between the chip 20 and the substrate 30 is determined in accordance with the electrical signal supplied through the pickup 10 so that the voltage, . ≪ / RTI > The detection section 40 can detect the level of the current flowing through the pickup section 10, the chip 20, and the substrate 30 because the possibility that the rated voltage is generally set is large. Alternatively, an impedance level between the chip 20 and the substrate 30 can be detected.

The determination unit 50 determines whether or not to mount the chip 20 based on the energization level detected by the detection unit 40. [ That is, the determination unit 50 determines whether the chip 20 is mounted on the substrate 30 correctly.

Particularly, since the detecting unit 40 detects the level of the current transmitted to the substrate 30 through the chip 20, the judging unit 50 judges that the chip 20 is on the substrate 30, It is judged whether or not it is mounted correctly on the board. Therefore, the determination unit 50 determines that the chip 20 is not correctly mounted on the substrate 30 when the current level detected by the detection unit 40 is equal to or smaller than a predetermined reference current, and determines that the chip 20 is defective.

Since the detection unit 40 detects the impedance level by the chip 20 and the substrate 30, the judging unit 50 judges whether or not the chip 20 is mounted on the basis of the impedance level . Therefore, when the impedance level detected by the detection unit 400 is equal to or lower than the predetermined reference impedance, the determination unit 50 determines that the chip 20 is mounted poorly.

Here, the predetermined reference current or predetermined impedance current is set in advance based on the rated power of the chip 20.

Figs. 3A to 3C are schematic diagrams showing the mounting state between the chip and the substrate.

3A to 3C, the structure of the unit mounting region 31 of the substrate 30 is such that the conductive layer 32 is formed in a convex shape and includes a plurality of substrate bumps 32. However, Of course not.

3A, a plurality of chip bumps 22 provided on the chip 20 are properly brought into contact with a plurality of substrate bumps 32 provided in the unit mounting area 31 of the substrate 30, The determination unit 50 will judge the mounting of the chip 20 to be good because the energization level detected by the detection unit 50 will satisfy the preset reference level.

3B, a plurality of chip bumps 22 provided on the chip 20 are in contact with only a part of the plurality of substrate bumps 32 provided in the unit mounting area 31 of the substrate 30, , The judging unit 50 will judge the mounting of the chip 20 to be defective because the energizing level detected by the detecting unit 50 may not satisfy the preset reference level.

3C, the plurality of chip bumps 22 provided on the chip 20 are not in contact with the plurality of substrate bumps 32 provided in the unit mounting region 31 of the substrate 30, The judging section 50 judges that the electric current level detected by the detecting section 40 does not meet the predetermined reference level because the electric current is in contact with the insulating layer 34 provided in the unit mounting area 31 of the chip 30, (20) is determined to be bad.

4 is a method for monitoring quality of a chip mounter process according to an embodiment of the present invention.

The method for monitoring the quality of a chip mounter process includes the steps of picking up a chip 20 and mounting the chip 20 on the substrate 30 at step S410 and supplying electricity to the chip 20 when the chip 20 is mounted on the substrate 30. [ And the level of energization of the substrate 30 is detected (S420), and whether or not the chip 20 is mounted is determined based on the detected energization level (S430).

The chip 20 is picked up by the pick-up section 10 and mounted on the substrate 30 by the pick- When the chip 20 is mounted on the substrate 30, power is applied to the pickup 10, the chip 20, the substrate 30, and the detector 40 in this order. Based on the energization level detected by the detection unit 40, the determination unit 50 determines whether the chip 20 is correctly mounted on the substrate 30 or not.

As described above, the chip 20 has a plurality of chip bumps 22. The substrate 30 may be provided with at least one of a plurality of substrate bumps 32 on which the plurality of chip bumps 22 provided on the chip 20 contact or a plurality of seating grooves 22 on which the plurality of chip bumps 22 are seated One.

When the chip 20 is mounted on the substrate 30, the energization level of the chip 20 and the substrate 30 to which electricity is supplied and detected is compared with a predetermined predetermined reference level, 30).

Particularly, the energization level is a level of current supplied to the substrate 30 through the pick-up portion 10 of the chip mounter and the chip 20 or an impedance level of the chip 20 and the substrate 30 .

When the current level detected by the detecting section 40 is lower than the predetermined reference current, the mounting of the chip 20 can be determined as defective. Further, when the impedance level detected by the detection unit 40 is lower than the predetermined reference impedance, the mounting of the chip 20 may be determined as defective. When the detected current level or impedance level is lower than at least one of the predetermined reference currents or the predetermined reference impedance, the determination unit 50 determines that the chip 20 has failed to mount on the substrate 30 It may be decided to judge.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

10: pickup part 12: pick-up nozzle
20: chip 22: chip bump
30: substrate 32: conductive layer
34: insulating layer 40:
50:

Claims (14)

A pickup unit for picking up a chip and mounting the chip on a substrate;
And the other terminal is connected to the substrate so that when the chip is mounted on the substrate and electrically connected to the chip, electricity is supplied to the chip through the pick-up unit to supply the supplied electricity to the substrate A detection unit for detecting a level of energization of the chip and the substrate by outputting the detection signal; And
And a judging section for judging whether the chip is mounted on the substrate based on the energization level detected by the detecting section. The method according to claim 1,
Wherein the chip comprises a plurality of chip bumps. Claim 3 has been abandoned due to the setting registration fee. 3. The method of claim 2,
Wherein the substrate includes a plurality of substrate bumps on which the plurality of chip bumps contact. Claim 4 has been abandoned due to the setting registration fee. 3. The method of claim 2,
Wherein the substrate has a plurality of seating grooves on which the plurality of chip bumps are seated. The method according to claim 1,
Wherein the pick-up section includes an electric supply module for supplying electric power to the chip. The method according to claim 1,
Wherein the detecting unit detects a level of a current transmitted to the substrate through the chip. Claim 7 has been abandoned due to the setting registration fee. The method according to claim 6,
Wherein the determination unit determines that the mounting of the chip is defective when the current level detected by the detecting unit is less than or equal to a predetermined reference current. The method according to claim 1,
Wherein the detecting unit detects an impedance level by the chip and the substrate. Claim 9 has been abandoned due to the setting registration fee. 9. The method of claim 8,
Wherein the judging unit judges that the chip is mounted improperly when the impedance level detected by the detecting unit is equal to or smaller than a predetermined reference impedance. Claim 10 has been abandoned due to the setting registration fee. A chip is picked up and mounted on a substrate;
Wherein when the chip is mounted on and electrically connected to the substrate, the chip is supplied with electricity, and the supplied electricity is supplied to the substrate through the chip, and electricity supplied from the chip is sent through the substrate, Detecting a level of energization of the chip and the substrate; And
And determining whether the chip is mounted on the substrate based on the detected energization level. Claim 11 has been abandoned due to the set registration fee. 11. The method of claim 10,
Wherein the chip comprises a plurality of chip bumps. Claim 12 is abandoned in setting registration fee. 12. The method of claim 11,
Wherein the substrate comprises any one of a plurality of substrate bumps to which the plurality of chip bumps contact or a plurality of seating grooves to which the plurality of chip bumps are seated. Claim 13 has been abandoned due to the set registration fee. 11. The method of claim 10,
Wherein the energization level is any one of a level of a current supplied to the substrate through the chip or an impedance level of the chip and the substrate. Claim 14 has been abandoned due to the setting registration fee. 14. The method of claim 13,
Wherein the step of determining the positive /
And judging that the mounting of the chip is defective when the detected energization level is lower than a predetermined reference energization level.

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