KR101699237B1

KR101699237B1 - Clock Arbiter Circuit Capable of Combining 2 Respective Clock Synchronizing System into One System and Circuit Comprising the Clock Arbiter Circuit

Info

Publication number: KR101699237B1
Application number: KR1020150106641A
Authority: KR
Inventors: 김영승; 정민철; 남효윤; 이현석
Original assignee: (주)에이디테크놀로지
Priority date: 2015-07-28
Filing date: 2015-07-28
Publication date: 2017-01-24

Abstract

A circuit comprising a clocked intermediate circuit and its intermediate circuit is disclosed. The clock relay circuit of the present invention receives two different clocks (CLK_A and CLK_B) and outputs one alternate clock (Alt_CLK), and the alternate clock (Alt_CLK) outputs a clock corresponding to each of the two clocks It is possible to output in order according to the difference. Therefore, when the alternate-clock (Alt_CLK) of the intermediate block is input as the clock of the external circuit block, one circuit block performs operations according to two different clocks.

Description

[0001] The present invention relates to a clock distribution circuit and a circuit including the intermediate clock circuit, and more particularly, to a clock distribution circuit capable of merging two separate clock synchronization systems into one,

The present invention relates to a clock relay circuit that receives two different clocks and generates a command pulse corresponding to a phase difference between two clocks to provide the clock signal as a clock signal to a circuit block and a circuit including the relay circuit.

In some integrated circuits, different external clocks may be received and processed, or different internal clocks may be generated and used simultaneously. In addition, there is a case where a design is required in which the same circuit block (Block) receives and processes all of these clocks.

In this case, conventionally, two identical circuit blocks for processing different clocks are arranged. For example, as shown in FIG. 1, the two circuit blocks U1 and U2 are the same circuit that receives the same data signal (or address signal, PAD) and performs the same operation. U1 receives clock A and operates in synchronization with clock A. U2 receives clock B and operates in synchronization with clock B. The circuit blocks U1 and U2 at this time may be implemented as discrete components or may be internal circuit blocks of one integrated circuit.

Given the recent tendency for various chips to be highly integrated and circuit design to become increasingly precise, attempts to reduce circuitry and thereby reduce data bus lines (plus address bus lines) are an essential step.

If Fig. 1 is implemented as one integrated circuit, if only one circuit block can be used instead of two circuit blocks, the length of the data bus line will be reduced accordingly, and a variety of design You can expect this.

[Related Prior Art]
Korean Patent Laid-Open No. 10-2001-0094529 (delay locked loop circuit and delayed synchronous method for correcting the duty cycle of a clock signal)
However, the present invention discloses a delay locked loop circuit and a delay locked method for correcting the duty cycle of a clock signal, and is not relevant to the intermediate circuit considered by the present invention. 5 generates the internal clock signal Clk_int by mixing the rising edge of the first clock signal Clk_r and the falling edge of the second clock signal Clk_f, Clk_int is not a clock corresponding to each of the first clock signal Clk_r and the second clock signal Clk_f but a signal obtained by adding the first clock signal Clk_r and the second clock signal Clk_f, Can not be used at the same time.

An object of the present invention is to provide a clock relay circuit which receives two different clocks and generates a command pulse corresponding to a phase difference between two clocks and provides the clock signal as a clock signal to a circuit block and a circuit including the relay circuit .

According to the present invention, an alternate-clock (Alt_CLK) according to a phase difference between a first clock (CLK_A) and a second clock (CLK_B) different from each other is generated and provided as a clock signal to the circuit block A clock relay circuit is proposed.

The clock mediation circuit includes a first pulse portion, a first logic portion, a second logic portion, a first adder, and an output-adder. The first pulse portion is triggered by the first clock CLK_A having a phase that is higher than the second clock CLK_B to generate a first delay pulse (Tuning_CK_B) of the first pulse width. The first logic unit outputs the first command pulse (Command_A) to the output-adder when the first clock (CLK_A) is input.

The first adder adds the first delay pulse (Tuning_CK_B), the first command pulse (Command_A), and the feedback signal (Feed_Back) from the circuit block according to the first command pulse to the second logic section do. The second logic unit outputs the second command pulse (Command_B) to the output-adder after the output of the first adder becomes inactive when the second clock (CLK_B) is input.

The output-adder outputs to the circuit block the substitute-clock (Alt_CLK) obtained by adding the first command pulse (Command_A) of the first logic section and the second command pulse (Command_B) of the second logic section to the circuit block, (ALT_CLK) outputs a pulse corresponding to the first clock (CLK_A) first, and after a predetermined time delay, the second clock (CLK_B) And outputs a corresponding pulse. Here, the predetermined delay time is a time obtained by adding the first delay pulse (Tuning_CK_B), the first command pulse (Command_A), and the feedback signal (Feed_Back_A) from the circuit block according to the first command pulse (Command_A) do.

If the phase of the second clock CLK_B is faster than the first clock CLK_A, the clock intermediation circuit of the present invention may further include a second pulse portion and a second adder. The second pulse unit generates a second delay pulse (Tuning_CK_A) having a second pulse width by triggering a second clock (CLK_B) having a phase earlier than the first clock (CLK_A) So that the first pulse unit does not output the first delay pulse (Tuning_CK_B).

The first pulse unit does not output the first delay pulse (Tuning_CK_B) when the first control signal is input. On the other hand, when the first clock (CLK_A) is out of phase with the second clock (CLK_B) 2 pulse unit so that the second pulse unit does not output the second delay pulse (Tuning_CK_A).

The second adder adds the second delay pulse (Tuning_CK_A), the second command pulse (Command_B) and the feedback signal (Feed_Back_B) from the circuit block according to the second command pulse (Command_B) The first logic unit outputs the first command pulse (Command_A) after the output of the second adder is inactivated. Therefore, when the phase of the second clock CLK_B is faster than the first clock CLK_A, the alternate-clock signal Alt_CLK corresponding to the first clock signal is output after being delayed from the pulse corresponding to the second clock signal CLK_B.

In an embodiment, the first pulse section includes a first filter section and a first pulse generator. The first filter unit outputs the first clock CLK_A as it is and does not output the first clock CLK_A when the first control signal arrives before the first clock CLK_A is input . The first pulse generator is triggered at the output of the first filter unit and outputs the first delay pulse (Tuning_CK_B).

The second pulse unit includes a second filter unit and a second pulse generator. The second filter unit outputs the second clock CLK_B as it is and does not output the second clock CLK_B when the second control signal arrives before the second clock CLK_B is input . And the second pulse generator is triggered at the output of the second filter section to output the second delay pulse.

According to the embodiment, in order to determine the priority order between the first command pulse (Command_A) and the second command pulse (Command_B) when the phase difference between the first clock (CLK_A) and the second clock (CLK_B) The pulse widths of the first delay pulse (Tuning_CK_B) generated by the first pulse generator and the second delay pulse (Tuning_CK_A) generated by the second pulse generator can be determined differently.

For example, when the phase difference between the first clock CLK_A and the second clock CLK_B is almost zero, the pulse width of the first delay pulse Tuning_CK_B is made larger than the second delay pulse Tuning_CK_A, (Alt_CLK) may output the first command pulse (Command_A) for the first clock (CLK_A) before the second command pulse (Command_B).

At this time, it is preferable that the first delay pulse (Tuning_CK_B) is kept active for at least the time required for generating the first command pulse (Command_A).

In an embodiment, the first logic section comprises a logic sub-pulse generator, a first tuner and an on-off section. The logic subpulse generator maintains a logic high and outputs a logic low pulse PN_CK_A when receiving the first clock CLK_A. The first tuner maintains a logic high and becomes logic low when the output (PN_CK_A) of the logic subpulse generator is logic low and becomes logic high again at the high edge of the output of the second adder And outputs a signal ON_Cmd_A. The ON / OFF unit generates the first command pulse (Command_A) when the output signal (ON_Cmd_A) of the first tuner is inputted.

Further, the first logic unit may further include a logic filter and a second tuner, and may further include a pulse of the first command pulse (Command_A) according to a feedback signal (Feed_Back_A) from the circuit block in accordance with the first command pulse, The width can be determined.

The logic filter receives and outputs a feedback signal (Feed_Back_A) from the circuit block according to the first command pulse while the first command pulse (Command_A) is logic high, thereby outputting a first command pulse And feeds back the feedback signal Feed_Back_A. The second tuner maintains a logical high, and when the output (ON_Cmd_A) of the first tuner becomes logic low, the signal goes to logic low and then to a logic high signal OFF_Cmd_A again at the high edge of the output of the logic filter ) To the on-off unit. The ON / OFF unit transitions the first command pulse (Command_A) to a logic high when the output signal (ON_Cmd_A) of the first tuner is input, and outputs the first command pulse (Command_A) when the output signal (Command_A) to a logical low to determine the pulse width of the first command pulse (Command_A).

According to another embodiment of the present invention, the clock intermediation circuit for generating an alternate-clock (Alt_CLK) according to a phase difference between a first clock (CLK_A) and a second clock (CLK_B) The present invention is also applicable to a circuit having a circuit block that outputs a result of operation according to the first clock CLK_A and the second clock CLK_B by operating the alternate-clock signal Alt_CLK as a clock input.

The clock distributing circuit according to the present invention may receive two different clocks (CLK_A, CLK_B) and output one alternate-clock (Alt_CLK). At this time, the alternate-clock (Alt_CLK) can output the clocks corresponding to the two clocks in order according to the phase difference. Therefore, when an alternate-clock (Alt_CLK) of a clock mediating block is input as a clock of an external circuit block, one circuit block performs operations according to two different clocks.

1 is a diagram showing a conventional use state using two circuit blocks,
2 is a circuit diagram showing a circuit having a clock distribution circuit according to the present invention,
3 is a timing diagram provided to illustrate the operation of the clock mediation circuit of the present invention;
Figure 4 is a block diagram of a clock mediator circuit of the present invention;
Figure 5 is a block diagram of a first logic portion of the clock mediator circuit of Figure 5;
Figure 6 is a block diagram of a second logic portion of the clock mediator circuit of Figure 5;
Fig. 7 is a timing diagram provided in the explanation of the operation of the first pulse section and the second pulse section of the clock relay circuit of Fig. 4 in case 1 and case 2,
Fig. 8 is a timing diagram provided in the explanation of the operation of the first pulse section and the second pulse section of the clock distribution circuit of Fig. 4 in case 3,
Fig. 9 is a timing chart provided in the operation description of the clock relay circuit as a whole in Case 1,
Fig. 10 is a timing diagram provided in the operation explanation of the whole clock relay circuit in Case 2, and
Fig. 11 is a timing chart provided in the explanation of the operation of the entire clocking circuit in Case 3; Fig.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail with reference to the drawings.

Referring to FIG. 2, the clock mediator 200 of the present invention receives a first clock CLK_A and a second clock CLK_B different from each other, and generates and outputs a new alternate-clock signal Alt_CLK. Thus, when providing the alternate-clock (Alt_CLK) of the intermediate circuit 200 to the clock input of the circuit block 10, the circuit block 10 generates the first and second clocks CLK_A and CLK_B, And operates. Since the alternate-clock signal Alt_CLK includes the pulses corresponding to the first clock CLK_A and the second clock CLK_B, the first command pulse Command_A and the second command pulse Command_B are output.

The clock intermediate circuit 200 generates an alternate-clock (Alt_CLK) according to the phase difference between the first clock (CLK_A) and the second clock (CLK_B), so it must be able to cope with the following three cases.

3, when the phase of the first clock CLK_A is faster than the second clock CLK_B, the first command pulse Command_A corresponding to the first clock CLK_A is output first and the second clock The second command pulse (Command_B) in accordance with the clock signal CLK_B (CLK_B) is generated. At this time, it is preferable that the second command pulse (Command_B) is outputted after the circuit block (10) receives the feedback (Feed_Back_A) as a result of performing the operation according to the first command pulse (Command_A).

(Case 2) Conversely, when the phase of the second clock CLK_B is faster than the first clock CLK_A, the second command pulse Command_B is first output to the substitute-clock Alt_CLK and the first command pulse Command_A is output to the substitute- Should be output next. Similarly, it is preferable that the first command pulse (Command_A) is output after the circuit block 10 receives the feedback (Feed_Back_B) as a result of performing the operation according to the second command pulse (Command_B).

(Case 3) In addition, even when the phase difference between the first clock (CLK_A) and the second clock (CLK_B) is extremely small, the clock intermediation circuit (200) has priority over the first command pulse Command_A and the second command pulse Command_B You must rank and output the alternate-clock (Alt_CLK) with a constant interval.

Hereinafter, with reference to FIG. 4 and FIG. 5, an implementation example of the clock mediator 200 capable of coping with all three cases described above will be described. 4, the clock mediator 200 includes a first pulse unit 410-a, a second pulse unit 410-b, a first logic unit 430-a, a second logic unit 430- b, a first adder 451, a second adder 453, and an output-adder 455.

The first pulse unit 410-a receives the first clock CLK_A and outputs a first delay pulse (Tuning_CK_B) as a result of the processing to the first adder 451. The second pulse unit 410-b receives the second clock CLK_B and outputs a second delay pulse (Tuning_CK_A) as a result of the processing to the second adder 453. The first delay pulse Tuning_CK_B is used to delay the output of the second command pulse Command_B according to the second clock CLK_B and the second delay pulse Tuning_CK_A is used to delay the output of the second command pulse Command_B according to the first clock CLK_A. And is used to delay the output of the command pulse (Command_A).

The second pulse unit 410-b outputs a first control signal for controlling the first pulse unit 410-a so as not to output the first delay pulse (Tuning_CK_B) to the first pulse unit 410-a, And the first pulse unit 410-a outputs a second control signal for controlling the second pulse unit 410-b not to output the second delay pulse Tuning_CK_A to the second pulse unit 410- b. Here, the first control signal may use the second clock CLK_B, and the second control signal may use the first clock CLK_A.

The first logic unit receives the first clock CLK_A, the feedback of the circuit block 10 and the output of the second adder 453. When the first clock CLK_A is input, the first logic unit receives the output of the second adder 453, And outputs the first command pulse (Command_A) to the output-adder 455 after the output of the first command pulse (Command_A) is inactive. The second logic unit receives the second clock CLK_B, the feedback of the circuit block 10 and the output of the first adder 451. When the output of the second filter unit Clock_B_F is input, And outputs the second command pulse (Command_B) to the output-adder 455 after the output is inactive.

The first adder 451 receives the first delay pulse (Tuning_CK_B), the feedback (Feed_Back) of the circuit block 10 and the first command pulse (Command_A) . The second adder 453 receives the second delay pulse (Tuning_CK_A), the feedback (Feed_Back) of the circuit block 10 and the second command pulse (Command_B) .

The output-adder 455 adds the first command pulse Command_A output from the first logic unit 430-a and the second command pulse Command_B output from the second logic unit 430-b, And finally outputs the clock (Alt_CLK) to the circuit block 10.

The first logic unit 430-a and the second logic unit 430-b shown in FIG. 5 and FIG. 6 have the same configuration but output different signals according to different input signals. The first logic unit 430-a includes a logic sub-pulse generator 501, a first tuner 503, a second tuner 505, a logic sub-filter 507, and an on-off unit 509 And the second logic unit 430-b includes a logic pulse generator 601, a first tuner 603, a second tuner 605, a logic filter 607, 609).

Hereinafter, the operation of the clock relay circuit 200 shown in Figs. 4 to 6 will be described in detail with reference to Figs. 7 to 10. Fig. First, the outputs of the first pulse section 410-a or the second pulse section 410-b in case 1 to case 3 described above will be described.

&Lt; Case 1: Output of first pulse section and second pulse section: Fig. 7 (a)

The case where the phase of the first clock CLK_A is faster than the second clock CLK_B will be described.

Referring to FIG. 7A, the first filter unit 411 of the first pulse unit 410-a outputs the first clock signal CLK_A as it is, and the first clock signal CLK_A outputs the second control signal And is provided to the second filter unit 413. The first pulse generator 415 outputs a first delay pulse (Tuning_CK_B) to the first adder 451 according to the output (Clock_A_F) of the first filter unit 411.

Since the second filter unit 413 filters the second clock CLK_B by the first clock CLK_A provided as the second control signal, the output (Clock_B_F) of the second filter unit 413 has no signal No output. Accordingly, the second pulse generator 417 does not operate and does not output the second delay pulse (Tuning_CK_A).

&Lt; Case 2: Output of first pulse section and second pulse section: Fig. 7 (b)

The case where the phase of the second clock CLK_B is faster than the first clock CLK_A will be described.

Referring to FIG. 7B, the second clock CLK_B is first input to the second filter unit 413 of the second pulse unit 410-b, and the second filter unit 413 receives the second clock CLK_B, (CLK_B) as it is, and the second clock (CLK_B) becomes the first control signal and is provided to the first filter unit 411. In the example of FIG. 4, the first control signal uses the output (Clock_B_F) of the second filter unit 413. The second pulse generator 417 outputs a second delay pulse (Tuning_CK_A) to the second adder 453 according to the output (Clock_B_F) of the second filter unit 413.

The first control signal is provided before the first clock CLK_A is input to the first filter unit 411. [ Accordingly, the first filter unit 411 filters the first clock CLK_A by the first control signal, and no signal is output to the output (Clock_A_F) of the first filter unit 411. Accordingly, the first pulse generator 415 does not operate and does not output the first delay pulse (Tuning_CK_B).

&Lt; Case 3: Output of first pulse section and second pulse section: Fig. 8 >

Case 3 is a case where the phase difference of the first clock (CLK_A) and the second clock (CLK_B) hardly occurs.

8, the first filter unit 411 and the second filter unit 413 are connected to the first clock signal CLK_A and the second clock signal CLK_B before the first control signal and the second control signal, respectively, The output (Clock_A_F) of the first filter unit 411 and the output (Clock_B_F) of the second filter unit 413 are generated, respectively. Accordingly, both the first pulse generator 415 and the second pulse generator 417 generate the first delay pulse (Tuning_CK_B) and the second delay pulse (Tuning_CK_A).

The first pulse generator 415 and the second pulse generator 417 generate a first clock CLK_A and a second clock CLK_A by making the pulse widths of the first delay pulse (Tuning_CK_B) and the second delay pulse (Tuning_CK_A) And the clock CLK_B. The first delay pulse Tuning_CK_B is for delaying the output of the second command pulse Command_B according to the second clock CLK_B and the second delay pulse Tuning_CK_A is for delaying the output of the first clock CLK_A, When the pulse width of the first delay pulse (Tuning_CK_B) is larger than the second delay pulse (Tuning_CK_A) as shown in FIG. 8, the output of the first command pulse (Command_A) Since the output of the second command pulse Command_B is delayed more than the output of the first command pulse Command_A corresponding to the first clock CLK_A, the first clock CLK_A is prioritized over the second clock CLK_B .

&Lt; Replacement in case 1 - Output of first command pulse in clock: Fig. 9 >

The logic sub-pulse generator 501 of the first logic unit 430-a maintains the logic high and outputs the logic low pulse PN_CK_A to the first tuner 503 when receiving the first clock CLK_A. The logic sub-pulse generator 601 of the second logic unit 430-b also maintains a logical high, and upon receiving the second clock (CLK_B), outputs a logical low pulse (PN_CK_B) to the first tuner 603.

The first tuner 503 maintains a logic high and becomes logic low when the output (PN_CK_A) of the logic subpulse generator 501 becomes a logic low and then goes to a logic high at the high edge of the output of the second adder 453 And provides a signal ON_Cmd_A that is logic high again to the ON / OFF section 509. [

At this time, the second adder 453 receives the second delay pulse (Tuning_CK_A), the feedback (Feed_Back) of the circuit block 10, and the second command pulse (Command_B) a). Since there is no input at this time, there is no output of the second adder 453. When the output (PN_CK_A) of the logic sub-pulse generator 501 becomes logic high, the output signal ON_Cmd_A of the first tuner 503 also becomes logic high because there is no output of the second adder 453.

The ON / OFF unit 509 starts outputting the first command pulse (Command_A) which is logic high by the output signal (ON_Cmd_A) of the first tuner 503. Since the start timing of the output of the first command pulse (Command_A) is important in the present invention, the pulse width of the first command pulse (Command_A) can be set as variously as desired. For example, (Command_A) can be set.

However, in order to make the pulse width of the first command pulse (Command_A) dependent on the feedback (Feed_Back_A) by the first command pulse (Command_A), the logic filter 507 and the second tuner 505 And determines the pulse width of the first command pulse Command_A. Thus, the logic filter 507 and the second tuner 505 may not be an essential configuration.

The first command pulse Command_A is input to the circuit block 10 by the output-adder 455 and the feedback (Feed_Back) in accordance with the first command pulse Command_A in the circuit block 10 is input to the logic filter 507 ). The logic filter 507 filters the feedback (Feed_Back_A) by the first command pulse (Command_A) among the feedback (Feed_Back) of the circuit block 10, (Feed_Back) of the first tuner 10 and outputs it to the second tuner 505.

The second tuner 505 maintains the logic high and becomes logic low when the output (ON_Cmd_A) of the first tuner 503 becomes logic low and returns to the logic low again at the high edge of the output of the logic filter 507 And supplies a signal (OFF_Cmd_A) that is logic high to the on-off unit 509. [ The on-off unit 509 changes the first command pulse (Command_A) in the logic high state to a logic low by the output signal (OFF_Cmd_A) of the second tuner 505. [ This completes the first command pulse (Command_A).

As a result, when the phase of the first clock CLK_A is faster than the second clock CLK_B, the first logic unit 430-a outputs a delay after the delay corresponding to the output signal ON_Cmd_A of the first tuner 503 And outputs the first command pulse (Command_A) first.

&Lt; Replacement in case 1 - Output of second command pulse in clock: Fig. 9 >

On the other hand, when the logic sub-pulse generator 601 of the second logic unit 430-b receives the second clock CLK_B, which is kept at a logic high level and is later than the first clock signal CLK_A, a logic low pulse PN_CK_B To the first tuner 603.

The first tuner 603 maintains a logic high and goes to a logic low when the output PN_CK_B of the logic subpulse generator 601 becomes a logical low and then goes to a high edge of the output of the first adder 451 And provides a signal (ON_Cmd_B) that is logic high again to the on / off unit 609. [

At this time, the first adder 451 receives the first delay pulse (Tuning_CK_B) and then receives the first command pulse (Command_A) and the feedback (Feed_Back_A) of the circuit block 10 according to the first command pulse The first adder 451 outputs a logic high when the feedback (Feed_Back) transitions to logic low after the first adder 451 becomes logic high at the first delay pulse (Tuning_CK_B) And outputs a pulse that becomes low. Accordingly, the output signal ON_Cmd_B of the first tuner 603 becomes a signal having a considerably long logical low period as compared with the output signal ON_Cmd_A of the first tuner 503 of the first logic unit 430-a.

The on-off unit 609 starts outputting the second command pulse (Command_B) which is logic high when the output signal (ON_Cmd_B) of the first tuner 603 becomes logic high. Therefore, the output of the second command pulse Command_B is the same as the output signal of the circuit block 10 according to the first delay pulse (Tuning_CK_B), the first command pulse (Command_A), and the first command pulse (Command_A) The signal is delayed by the interval.

Similarly, the pulse width of the second command pulse (Command_B) can be set in various ways, for example, the on / off unit 609 arbitrarily sets the second command pulse (Command_B ) Can be set. However, in the present invention, the second tuner 605 is separately provided so that the second command pulse (Command_B) becomes logic low at the time of outputting the feedback (Feed_Back_B) according to the second command pulse (Command_B). Therefore, the logic filter 607 and the second tuner 605 may not be essential.

The second command pulse Command_B is input to the circuit block 10 by the output-adder 455 and the feedback (Feed_Back_B) in response to the second command pulse Command_B in the circuit block 10 is input to the logic filter 607 ). The logic filter 607 outputs the feedback of the circuit block 10 while the second command pulse Command_B is logic high to filter the feedback (Feed_Back_B) of the circuit block 10 by the second command pulse (Command_B) (Feed_Back) to the second tuner 605.

The second tuner 605 maintains a logic high and goes to a logic low when the output (ON_Cmd_B) of the first tuner 603 becomes logic low and then to a logic low again at the high edge of the output of the logic filter 607 And provides a signal (OFF_Cmd_B) that is logic high to the on-off unit 609. [ The on-off unit 609 changes the second command pulse (Command_B) of the logic high state to a logic low by the output signal (OFF_Cmd_B) of the second tuner 605. [ This completes the second command pulse (Command_B).

As a result, when the phase of the first clock CLK_A is faster than the second clock CLK_B, the second logic unit 430-b outputs the first delay pulse Tuning_CK_B, the first command pulse Command_A, And outputs a second command pulse (Command_B) after being delayed by a feedback (Feed_Back_A) signal interval of the circuit block 10 according to the first command pulse (Command_A).

&Lt; Replacement in case 2 - Output of clock: Fig. 10 >

The case of Case 2 in which the phase of the second clock CLK_B is earlier than the first clock CLK_A is opposite to Case 1 and the operation of the first pulse portion 410- And the operation of the second pulse unit 410-b is the same as that of the first pulse unit 410-a in case 1. [ On the contrary, the operation of the first logic unit 430-a is the same as that of the second logic unit 430-b in the case 1, and the operation of the second logic unit 430- Is the same as the operation of the logic unit 430-a.

Therefore, the second command pulse (Command_B) is output before the first command pulse (Command_A), and the first command pulse (Command_A) is output after being delayed by the output of the second adder 453. The output of the second adder 453 receives the second delay pulse (Tuning_CK_A), the second command pulse (Command_B) and the feedback (Feed_Back) of the circuit block 10 according to the second command pulse (Command_B) The first command pulse Command_A receives the second delay pulse Tuning_CK_A, the second command pulse Command_B and the feedback_Back_B signal of the circuit block 10 according to the second command pulse Command_B, As shown in FIG.

&Lt; Replacement in case 3 - Output of clock: Fig. 11 >

Before describing the case 3, the case where the pulse width of the first delay pulse (Tuning_CK_B) is set larger than the second delay pulse (Tuning_CK_A) as described above will be mainly described.

The second adder 453 receives the second pulse (Tuning_CK_A), the second command pulse (Command_B), and the feedback (Feed_Back) of the circuit block 10 according to the second command pulse (Command_B) The second adder 453 is equal to the second delay pulse (Tuning_CK_A) because the second command pulse (Command_B) is not generated while the second delay pulse (Tuning_CK_A) is active.

The first tuner 503 of the first logic unit 430-a maintains a logic high and becomes logic low when the output PN_CK_A of the logic subpulse generator 501 is logic low, Off section 509 to the ON / OFF section 509, and the second adder 453 supplies the second delay pulse (Tuning_CK_A) to the first logic section The output ON_Cmd_A of the first tuner unit 503 is set such that the output of the first tuner 503 when the second delay pulse Tuning_CK_A becomes logical low is outputted to the first tuner unit 503 of the first tuner unit 430- The signal ON_Cmd_A also becomes logic high. The ON / OFF unit 509 starts outputting the first command pulse (Command_A) which is logic high by the output signal (ON_Cmd_A) of the first tuner 503. When the circuit block 10 outputs feedback (Feed_Back) by the first command pulse (Command_A), the logic filter 507 outputs the feedback (Feed_Back) while the first command pulse (Command_A) The first command pulse (Command_A) becomes logic low again by the output (OFF_Cmd_A) of the second tuner unit 505. Thus, the first command pulse (Command_A) is output after being delayed by the second delay pulse (Tuning_CK_A).

On the other hand, the delay of the second command pulse (Command_B) is much larger than the delay of the first command pulse (Command_A).

The first adder 451 receives the first delay pulse (Tuning_CK_B), the first command pulse (Command_A), and the feedback (Feed_Back_A) of the circuit block 10 according to the first command pulse (Command_A) Since the first command pulse (Command_A) and the feedback (Feed_Back) of the circuit block 10 according to the first command pulse (Command_A) occur while the first delay pulse (Tuning_CK_B) is active, The output of the first delay circuit 451 is a pulse obtained by adding the first delay pulse (Tuning_CK_B), the first command pulse (Command_A) and the feedback (Feed_Back_A) of the circuit block 10 according to the first command pulse (Command_A). The output of the first tuner unit 603 is delayed by the pulse width of the output of the first adder 451 and is input to the on-off unit 609. The output of the second adder 451 is delayed by the output of the first adder 451, Command_B) begins to be generated at a logic high. The second command pulse (Command_B) is completed while the feedback (Feed_Back) of the circuit block 10 by the second command pulse (Command_B) starts to be output and then transits to a logic low again.

In this manner, even when there is no phase difference between the first clock CLK_A and the second clock CLK_B, the first command pulse Command_A according to the first clock CLK_A is output first, and the second clock CLK_B The second command pulse Command_A is delayed and output. The first delay pulse (Tuning_CK_B) is activated for at least the time required for generating the first command pulse (Command_A) by at least the second delay pulse (Tuning_CK_A) in order to design the delay of the second command pulse (Command_A) .

Naturally, the scope of right of the present invention extends to a corresponding intermediate circuit in only one of the three cases. For example, the intermediate circuit for processing Case 1 includes a first pulse portion 410-a, a first logic portion 430-a, a second logic portion 430-b, a first adder 451, and an output- 455, and the second pulse portion 410-b and the second adder 453 are unnecessary, and neither the first control signal nor the second control signal is required.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the invention as defined by the appended claims. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

Claims

CLAIMS 1. A mediation circuit capable of generating a substitute-clock (Alt_CLK) according to a phase difference between a first clock (CLK_A) and a second clock (CLK_B)
A first pulse unit triggered by the first clock signal CLK_A having a phase that is higher than the second clock signal CLK_B to generate a first delay pulse signal Tuning_CK_B having a first pulse width;
A first logic unit for outputting a first command pulse (Command_A) when the first clock (CLK_A) is input;
A first adder for adding the first delay pulse (Tuning_CK_B), the first command pulse, and a feedback signal (Feed_Back) from the circuit block that receives the first command pulse and outputs the result;
A second logic unit for outputting a second command pulse (Command_B) after the output of the first adder is inactive when the second clock (CLK_B) is input;
And an output-adder for outputting the substitute-clock (Alt_CLK) obtained by adding the first command pulse (Command_A) of the first logic section and the second command pulse (Command_B) of the second logic section.

The method according to claim 1,
And a second control unit for generating a second delay pulse (Tuning_CK_A) having a second pulse width by triggering a second clock (CLK_B) having a phase higher than the first clock (CLK_A) A second pulse unit for preventing one pulse unit from outputting the first delay pulse (Tuning_CK_B); And
A pulse obtained by adding the second delay pulse (Tuning_CK_A), the second command pulse (Command_B) and the feedback signal (Feed_Back) from the circuit block according to the second command pulse (Command_B) to the first logic unit And a second adder for adding a second adder,
The first pulse unit outputs a second control signal to the second pulse unit when the first clock signal CLK_A is in phase with the second clock signal CLK_B so that the second pulse unit does not output the second delay pulse However,
Wherein the first logic unit outputs the first command pulse after the output of the second adder is deactivated.

3. The method of claim 2,
Wherein the first pulse section comprises:
Wherein the first clock signal CLK_A is output as it is and the first clock signal CLK_A is not output when the first control signal arrives before the first clock signal CLK_A is input. ; And
And a first pulse generator triggered by an output of the first filter unit to output the first delay pulse (Tuning_CK_B).

The method of claim 3,
Wherein the second pulse section comprises:
And a second filter (CLK_B) that outputs the second clock (CLK_B) as it is and does not output the second clock (CLK_B) when the second control signal arrives before the second clock ; And
And a second pulse generator triggered by an output of the second filter unit to output the second delay pulse.

5. The method according to any one of claims 2 to 4,
(Alt_CLK) when there is no phase difference between the first clock (CLK_A) and the second clock (CLK_B) by making the pulse width of the first delay pulse (Tuning_CK_B) larger than the second delay pulse (Tuning_CK_A) And the first command pulse (Command_A) for the first clock (CLK_A) is outputted before the second command pulse (Command_B).

6. The method of claim 5,
Wherein the first delay pulse (Tuning_CK_B) remains active for at least the time required to generate the first command pulse (Command_A).

6. The method of claim 5,
Wherein the first logic unit comprises:
A logic pulse generator for generating a logic low pulse (PN_CK_A) when the first clock (CLK_A) is received while maintaining a logic high (High);
A signal (ON_Cmd_A) that becomes a logical low when the output (PN_CK_A) of the logic sub-pulse generator is at a logic low and becomes logic high again at a high edge of the output of the second adder while maintaining a logical high, A first tuner for outputting the first tuner; And
And an on-off unit (509) for generating the first command pulse (Command_A) when the output signal (ON_Cmd_A) of the first tuner is inputted.

8. The method of claim 7,
Wherein the first logic unit comprises:
A logic part filter for receiving and outputting a feedback signal (Feed_Back_A) from the circuit block according to the first command pulse while the first command pulse (Command_A) is logic high; And
(OFF_Cmd_A) which becomes logic low when the output (ON_Cmd_A) of the first tuner becomes logic low while it is logic high again at the high edge of the output of the logic filter while maintaining the logic high, Further comprising a second tuner for outputting to the off-
The ON / OFF unit transitions the first command pulse (Command_A) to a logic high when the output signal (ON_Cmd_A) of the first tuner is input, and outputs the first command pulse (Command_A) when the output signal (Command_A) is changed to a logical low to determine the pulse width of the first command pulse (Command_A).

A clock intermediate circuit according to claim 5 for generating an alternate-clock (Alt_CLK) according to a phase difference between a first clock (CLK_A) and a second clock (CLK_B)
And a circuit block for outputting an operation result according to the first clock (CLK_A) and the second clock (CLK_B) by operating the clock-input (Alt_CLK) of the clock distribution circuit as a clock input. .

The clock relay circuit according to any one of claims 1 to 4, which generates an alternate-clock (Alt_CLK) according to a phase difference between the first and second clocks (CLK_A and CLK_B)
And a circuit block for outputting an operation result according to the first clock (CLK_A) and the second clock (CLK_B) by operating the clock-input (Alt_CLK) of the clock distribution circuit as a clock input. .