KR101697044B1 - Improved transistor channel - Google Patents

Abstract

A transistor device includes a substrate provided with a first region and a second region; a first semiconductor layer of a first semiconductor material provided with a first portion on the first region and a second portion on the second region, in which the first region is separated from the second region; a second semiconductor layer of second semiconductor materials on the second portion of the first semiconductor layer; a first transistor having a first conductive type; and a second transistor having a second conductive type. The first transistor is provided with a first set of source electrode/drain electrode regions formed in the first semiconductor layer, and arranged in the first region. The second transistor is provided with a second set of source electrode/drain electrode regions formed in the second semiconductor layer, and arranged in the second region. The second conductive type is different from the first conductive type, and the second semiconductor materials are different from the first semiconductor materials.

Description

Improved transistor channel {IMPROVED TRANSISTOR CHANNEL}

The present invention relates to a semiconductor device.

The semiconductor integrated circuit (IC) industry has experienced rapid growth over the past several decades. Technological advances in semiconductor materials and design have produced smaller and more complex circuits. Technological advances in processing and manufacturing have also undergone technological advancement, enabling the development of such materials and designs. As the size of the smallest component is reduced, various challenges have increased. For example, a three-dimensional transistor such as a fin-like field-effect transistor (FinFET) has been introduced. Methods of fabricating existing devices and devices are generally appropriate for their intended purposes, but are not entirely satisfactory in all respects. For example, limiting the effective gate length creates challenges for semiconductor device development, even for FinFETs. It is desirable to improve this area.

It is an object of the present invention to provide an improved transistor channel.

According to one example, a transistor device comprises a substrate having a first region and a second region, a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, The first part is separated from the second part. The device further comprises a second semiconductor layer of a second semiconductor material on a second portion of the first semiconductor layer, a first transistor of a first conductivity type, and a second transistor of a second conductivity type, Drain region and a second set of source / drain regions formed in the second semiconductor layer, and the second transistor is disposed in the second region. The first conductivity type is different from the second conductivity type, and the second semiconductor material is different from the first semiconductor material.

According to one example, a transistor device includes a gate device, a source region having a vertex pointing towards the channel under the gate device, and a drain region having a vertex toward the channel. The tip at the apex of the tip and drain regions at the apex of the source region includes a superlattice structure.

According to one example, a method for manufacturing a semiconductor device includes providing a first wafer comprising a substrate and a first layer of semiconductor material, bonding a first wafer to a second wafer, And removing the sacrificial layer, patterning the bonded wafer to produce a first structure and a second structure, depositing a second semiconductor material from the first structure, Forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.

According to the present invention, it is possible to provide an improved transistor channel.

Embodiments of the present disclosure are best understood by reading the following detailed description together with the accompanying drawings. Note that according to standard practice in the industry, various features are not shown in scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of explanation.
1 is a flow chart illustrating an exemplary method for manufacturing a semiconductor device, in accordance with one example of the principles described herein.
Figures 2-6 illustrate a cross-sectional view of an exemplary semiconductor device in the fabrication steps described in the method of Figure 1, in accordance with an example of the principles described herein.
7A-7H illustrate an exemplary process for forming an embedded channel in a transistor device, in accordance with one example of the principles described herein.
8 is a diagram illustrating an exemplary tip having a high dopant concentration, in accordance with one example of the principles described herein.
Figure 9 is a diagram illustrating an exemplary tip with a superlattice structure, in accordance with an example of the principles described herein.
10 is a flow diagram illustrating an exemplary method of forming a transistor having an improved channel, in accordance with one example of the principles described herein.

The following inventive disclosures provide a number of different embodiments, or examples, that implement different features of a given subject matter. Specific examples of components and arrangements are described below to simplify disclosure of the present invention. Of course, this description is for illustrative purposes only, and not for limitation. For example, in the following description, formation of a first feature on a second feature or on a second feature may include embodiments in which a first feature and a second feature are formed in direct contact, and the first feature and the second feature 2 features may be formed between the first feature and the second feature such that the second feature is not in direct contact. In addition, the disclosure of the present invention may repeat the reference numerals and / or characters in various examples. Such repetition is for simplicity and clarity and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

Moreover, it is to be understood that spatial relation terms such as "below", "under", "subordinate", "above", "above", etc., Can be used herein for ease of explanation. Spatial relationship terms are intended to encompass different orientations of the device being used or operating, as well as those depicted in the drawings. The device can be oriented differently (with a 90 degree rotation or in a different orientation), and accordingly the spatial relationship explanations used herein are also understood.

An example of a semiconductor device that can benefit from one or more embodiments of the present application is a semiconductor device. Semiconductor devices include, for example, complementary devices including P-type metal-oxide-semiconductor (PMOS) devices and N-type metal-oxide-semiconductor And may be a complementary metal-oxide-semiconductor (CMOS) device. The following disclosure will continue with examples of semiconductor devices to illustrate various embodiments of the present application. It should be understood, however, that this application is not intended to be limited to any particular type of device, except as specifically claimed.

1 is a flow diagram of one example of a method 100 of manufacturing one or more semiconductor devices in accordance with various aspects of the present disclosure. The method 100 is discussed in detail below with reference to the semiconductor device 200 shown in Figs. 2-6 for illustrative purposes.

Referring to Figures 1 and 2, the method 100 begins at step 102 by providing a substrate 210. The substrate 210 may be a bulk silicon substrate. Alternatively, the substrate 210 may comprise an elemental semiconductor such as silicon or germanium in a crystalline structure; Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium phosphide, and / or indium antimonide; Or a combination thereof. Possibly, the substrate 210 also includes a silicon-on-insulator (SOI) substrate. The SOI substrate is fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

The substrate 210 may include various doped regions according to design requirements known in the art. The doped region may be a p-type dopant such as boron or BF2; An n-type dopant such as phosphorus or arsenic; Or a combination thereof. The doped region may be formed directly on the substrate 210 as a P-well structure, as an N-well structure, as a dual well structure, or may be formed using a protruding structure. The substrate 210 may further include various active regions, such as regions configured for an N-type metal oxide semiconductor transistor device and regions configured for a P-type metal oxide semiconductor transistor device.

In the case of a FinFET, the substrate 210 may comprise a plurality of pins formed by any suitable processes, including various deposition processes, photolithographic processes, and / or etching processes. For example, the pins are formed by patterning and etching the substrate 210.

The substrate 210 may include an isolation region 212 to isolate the active regions of the substrate 210. The isolation regions 212 may be formed using conventional isolation techniques such as shallow trench isolation (STI) to define and electrically isolate the various regions. The isolation region 212 includes silicon oxide, silicon nitride, silicon oxynitride, air gaps, other suitable materials, or combinations thereof. The isolation region 212 is formed by any suitable process. For example, the formation of the STI can be accomplished by a photolithographic process, an etching process (e.g., using dry etch and / or wet etch) to etch the trenches in the substrate, and a deposition to fill the trench with one or more dielectric materials Process (e. G., Using a chemical vapor deposition process). The trench can be partially filled as in this embodiment, in which case the remaining substrate between the trenches forms a fin structure. In some instances, the filled trench may have a multilayer structure, such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.

Referring again to Figures 1 and 2, the method 100 includes forming a first gate stack 220 over a substrate 210, including overlying (lapping) fins in a FinFET, forming a first gate stack 220 The process proceeds to step 104 by forming gate spacers 225 along the sidewalls of the gate electrode. The first gate stack 220 may include a dielectric layer and a gate electrode layer. The first gate stack 220 may be formed by a procedure including a deposition process, a photolithographic patterning process, and an etching process. Deposition processes may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. The photolithographic patterning process may be performed by any suitable process, such as photoresist coating (e.g., spin-on coating), soft bake, mask alignment, exposure, post exposure bake, photoresist development, And combinations of these. The etching process includes dry etching, wet etching, and / or other etching methods.

In this embodiment, the first gate stack 220 is a dummy gate stack and is later replaced with a second gate stack. The dummy gate stack 220 may include a dielectric layer and a polysilicon layer.

The gate spacer 225 includes a dielectric material such as silicon oxide. Alternatively, the gate spacers 225 may comprise silicon nitride, silicon carbide, silicon oxynitride, or a combination thereof. The gate spacers 225 may be formed by depositing a dielectric material over the first gate stack 220 and then etch back the dielectric material to anisotropic.

Referring to Figures 1 and 3, the method 100 includes forming a plurality of recesses 230 on both sides of the first gate stack 220 to form recesses 230A and 230B (collectively referred to as recesses 230) And proceeds to step 106 by removing a portion of the substrate 210, including a portion thereof. The recess 230 is formed in the source region and the drain region of the field effect transistor 205 such that the first gate stack 220 is interposed in the recesses 230. [ These are referred to as source recess 230A and drain recess 230B. The recess process may include a wet etch process, a dry etch process, and / or a combination thereof. The recess process may also include selective wet etching or selective dry etching. The wet etch solution comprises tetramethylammonium hydroxide (TMAH), HF / HNO ₃ / CH ₃ COOH solution, or other suitable solution. Dry etching process gas containing pullulans cut out (for _{example, CF 4, SF 6, CH} 2 F 2, CHF 3, and / or C ₂ F _6), chlorine-containing gas _{(e.g., Cl 2, CHCl 3, CCl} 4, and / or BCl _3), bromine-containing gas (e. g., it may implement a HBr and / or CHBR _3), iodine-containing gas, another suitable gas, and / or plasma, and / or combinations thereof. The etch process may include etch selectivity, flexibility, and multi-step etch to obtain the desired etch profile.

The etching process is controlled to achieve the desired profile of the recesses 230A and 230B. In this embodiment, the profiles of the recesses 230A and 230B are formed to have at least one vertex 232A and 232B, respectively, of the surfaces facing the first gate stack 220, as shown in FIG. As an example, the vertex 232A is formed by two Si planes with (111) crystallographic orientation. The first distance d1 is defined as the distance between the two closest source and drain corner points 232A and 232B. In this embodiment, the gate 220 with sidewall spacers 225 has a width greater than 30 nm, and the first distance dl is less than or equal to 40 nm. Although illustrated in the drawings as point, in some embodiments, the source and drain vertices 232A and 232B may be rounded and may have a width less than or equal to 10 nm. By way of example, the rounded corners can be achieved by post recess-etch thermal annealing (process temperature and pressure are> 700 C and <100 torr respectively).

Referring to Figures 1 and 4, the method 100 includes forming epitaxial structures 240A and 240B (collectively referred to as epitaxial structure 240) in recesses 230A and 230B, respectively, Lt; / RTI &gt; In this embodiment, the epitaxial structure 240 includes a source / drain structure. A source / drain epitaxial structure 240 is formed by epitaxially growing a semiconductor material 242 in the recess 230. As a result, at least a portion of the source / drain epitaxial structure 240 has the same profile as the recess 230.

Semiconductor material 242 may be a single element semiconductor material such as germanium (Ge) or silicon (Si); Or compound semiconductor materials such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs); Or semiconductor alloys such as silicon germanium (SiGe) and gallium arsenide (GaAsP). In one embodiment, the semiconductor material 242 is different from the material of the substrate 210. The source / drain epitaxial structure 240 has a suitable crystallographic direction (e.g., (100), (110), (111) or (311) crystallographic orientation). In an example, if an NFET device is desired, the source / drain epitaxial structure 240 may comprise epitaxially grown silicon (epi Si, or Si: C) 242. In another example, if a PFET device is desired, the source / drain epitaxial structure 240 may comprise epitaxially grown silicon germanium (SiGe) 242. Si: C and SiGe can provide tensile strain and compressive strain on the channel through the S / D corners. The source / drain epitaxial structure 240 may be formed by one or more epitaxial or epitaxial (epi) processes. The epitaxial process may be performed using a CVD deposition technique such as selective epitaxy growth (SEG), vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD) ], Molecular beam epitaxy, and / or other suitable processes.

The source / drain epitaxial structure 240 may be in-situ doped or undoped during the epi process. For example, the epitaxially grown SiGe source / drain feature 240 can be doped with boron, and the epitaxially grown Si epi source / drain features can be doped with carbon, phosphorus, or both. If the source / drain epitaxial structure 240 is not in situ doped, a second implant process (e.g., a junction implant process) is performed to dope the source / drain epitaxial structure 240. One or more annealing processes may be performed to activate the source / drain dopant in the epitaxial structure. The annealing process may include rapid thermal annealing (RTA) and / or laser annealing processes.

Referring to Figures 1 and 5A, the method 100 includes removing the first gate stack 220 to form the gate trench 250, and further etching the substrate 210, including the fin, . The etching processes may include selective wet etching or selective dry etching so as to have sufficient etch selectivity for the gate spacers 225. The etching processes may be similar in many respects to those discussed above with respect to FIG. In this embodiment, the gate trench 250 is formed with a profile having at least one gate vertex 255. In one embodiment, gate vertex 255 is formed at the bottom of gate trench 250 by two (111) planes of Si substrate 210. In this embodiment, the second vertical distance d2 between the horizontal line A-A connecting the gate vertex 255 and the source and drain vertices 232A and 232B is less than or equal to 30 nm. Although shown in the drawings as a point, in some embodiments, gate vertex 255 may be rounded and may have a width less than or equal to 10 nm. As an example, the rounded corners can be achieved by post recess-etch thermal annealing (temperature &gt; 700 C at low pressure of <100 torr).

In another embodiment, after formation of the gate trench 250, ion implantation is performed to dope the target region 256 to the substrate 210, which may include gate vertices 255, And is located between the source apex 232A and the drain apex 232B.

Referring to Figures 1 and 6, the method 100 proceeds to step 112 by forming a second gate stack 260 in the gate trench 250. The second gate stack 260 may include a dielectric layer 262 and a gate electrode layer 264. The gate stack may include additional layers such as an interfacial layer, a capping layer, a diffusion / barrier layer, a dielectric layer, a conductive layer, another suitable layer, and / or combinations thereof. For example, the dielectric 262 may comprise an interfacial layer (IL) and a gate dielectric layer. Exemplary ILs include silicon oxide (e.g., thermal oxide or chemical oxide) and / or silicon oxynitride (SiON). The gate dielectric layer may comprise a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high -k dielectric materials, HfO _2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum _{oxide, HfO 2 -Al 2 O 3 (} hafnium dioxide-alumina) alloy, other suitable high -k dielectric material , And combinations thereof.

The gate electrode layer 264 may be formed of any suitable material such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, , &Lt; / RTI &gt; and / or combinations thereof.

The gate dielectric layer 262 and the gate electrode layer 264 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable methods, and / .

A dielectric layer 270 is deposited over the substrate 210, including over the source / drain epitaxial structure 240 and the second gate stack 250. Dielectric layer 270 includes silicon oxide, silicon nitride, silicon carbide, oxynitride, or other suitable material. Dielectric layer 270 is deposited by suitable techniques such as ALD, CVD, PVD, thermal oxidation, or combinations thereof. In addition, a CMP process is performed to planarize the top surface of the second gate stack 260 and dielectric layer 270.

Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, removed, or moved for further embodiments of the method 100 . IC device 200 may include additional features that may be formed by subsequent processing. For example, various contact / via / line and multilayer interconnect features (e.g., metal layers, interlayer dielectrics) may be formed on the substrate and configured to connect various features or structures of the IC device 200. For example, multilayer interconnects include vertical interconnects such as conventional vias or contacts and horizontal interconnects such as metal lines. Various interconnecting features may implement various conductive materials including copper, tungsten, and silicide.

Based on the above, the present disclosure presents a semiconductor device and its fabrication. Semiconductor devices use a corner structure for each of the gate stack, source and drain structures. The vertexes of the gate, the source, and the drain are formed to be separated from each other by a very small distance. The semiconductor device also has the option of having a doped region located between the vertices of the gate stack, source and drain. Thus, such a semiconductor device can act as a tunneling device, or as a single electron transistor (SET), demonstrating the development of small gate lengths, low Vt, and low power consumption.

7A-7H illustrate an exemplary process for forming an embedded channel in a transistor device. Figure 7A shows a first wafer 700 comprising a semiconductor substrate 702 on which a first layer of semiconductor material 704 is formed. The semiconductor substrate 702 may be, for example, a silicon-on-insulator (SOI) substrate. Such a substrate may comprise a semiconductor layer, an insulator layer such as an oxide layer, and another semiconductor layer.

The first semiconductor material 704 is a semiconductor material that can be designed for NMOS transistors. Thus, the semiconductor type may have N-type conductivity. In this example, the first semiconductor material 704 is selected such that the channel region can be appropriately deformed to improve the corresponding mobility, such as tensile strain, in the channel region of the NMOS transistor. The first semiconductor material 704 may be comprised of silicon germanium (SiGe) in one example. The first semiconductor material 704 may be epitaxially grown on the semiconductor substrate 702. [ In one example, the first semiconductor material 704 may be formed using a low-pressure chemical vapor deposition (LPCVD) process. Such a process can occur at temperatures in the range of about 800-1100 degrees centigrade. This process can occur at pressures in the range of approximately 1-600 torr.

7B is a view showing a second wafer 701 to be eventually bonded to the first wafer 700. Fig. The second wafer 701 includes a sacrificial substrate 706 and a second semiconductor material layer 708. The sacrificial substrate 706 is thus referred to because it will eventually be removed as described below. The sacrificial substrate 706 may be composed of, for example, indium phosphide (InP).

The second semiconductor material 708 may be designed for PMOS transistor devices. Thus, the second semiconductor material may have a P-type conductivity. In this example, a second semiconductor material 708 is selected such that the channel region formed therein is appropriately deformed to improve corresponding mobility, such as compressive strain, in the channel region of the PMOS transistor. The second semiconductor material 708 may comprise, for example, indium gallium arsenide (InGaAs). The second semiconductor material layer 708 may be formed through an epitaxial process. The second semiconductor material layer 708 may be formed using a metal-organic chemical vapor deposition (MOCVD) process. Such processes can occur at temperatures in the range of about 500-700 degrees centigrade. Such a process can occur at a pressure of about 75 torr.

Fig. 7C is a diagram showing a combined wafer 703 after bonding of the first wafer 700 and the second wafer 701. Fig. Bonding is performed so that the second semiconductor material 708 is bonded to the first semiconductor material 704 using the bonding layer 710. [ Depending on the type of material used in the second semiconductor material layer 708, a surface passivation process may be applied to the second semiconductor material layer 708 before bonding occurs. Additionally, depending on the type of material used in the first semiconductor material layer 704, a plasma post oxidation process may be performed on the first channel layer material 704. The bonding layer 710 applied before the bonding process occurs may be composed of aluminum oxide (Al ₂ O ₃ ). The bonding layer 710 may be applied to both wafers 700 and 701 through atomic layer deposition (ALD).

7D is a view showing the removal of the sacrificial substrate 706. Fig. The sacrificial substrate 706 is removed after the bonding process is completed. The sacrificial substrate 706 may be removed using a wet etch process. For example, hydrochloric acid may be used to remove the sacrificial substrate 706.

7E is a diagram illustrating the patterning of a combined wafer 703 to form a first structure in a first region 705 and a second structure in a second region 707. FIG. Throughout the subsequent processes, the first structure of the first region 705 will be the first transistor device and the second structure of the second region 707 will be the second transistor device. In particular, the first structure will be an NMOS device and the second structure will be a PMOS device. The combined wafer 703 can be patterned using various photolithographic techniques. For example, a photoresist can be used to form the desired pattern. An anisotropic etch process, such as a dry etch process, can then be used to remove a portion of the combined wafer exposed according to the pattern. The etching gas used in such an etching process may be a mixture of chlorine and nitrogen or a mixture of chlorine and argon. The bias power used in the etching process may be 25 watts or less.

7F is a view showing the removal of the second semiconductor material 708 and the bonding layer 710 from the first structure of the first region 705. FIG. Thus, the first semiconductor material layer 704 of the first region 705 is exposed. Removal of the second semiconductor material 708 may involve a variety of photolithographic techniques. For example, a photoresist may be used to cover the second feature 707 of the wafer and other features of the second semiconductor material layer 708 that are not intended to be removed. A wet etch process may then be used to remove the exposed portions of the second semiconductor material layer 708. [ The wet etch process may include one of a variety of wet etch solutions such as HCl or H ₃ PO ₄ .

7G is a view showing the formation of the gate structures 712 and 716. FIG. In particular, the first gate 712 is formed in the first region 705 and the second gate 716 is formed in the second region 707. The gate structures 712 and 716 may be formed by various fabrication techniques. In one example, the gate structures 712 and 716 may be formed in a manner similar to the gate devices described above with respect to FIGS. 2-6. In particular, in some examples, gate structures 712 and 716 may include gate vertices as described above.

7H is a view showing the formation of the source / drain regions 714 and 718. FIG. In particular, a source / drain region 714 is formed in the first semiconductor material layer 704 of the first region 705 and a source / drain region 718 is formed in the second semiconductor material layer 707 of the second region 707 708). The source / drain regions 714 and 718 are formed by first removing a portion of the underlying semiconductor material, and then depositing the source / drain material within the removed portion.

The source / drain regions 714 may be formed by removing portions of the first semiconductor material layer 704 to form recesses on opposite sides of the gate 712. The material may be removed by using an anisotropic etch process, such as a dry etch process, or a combination thereof, in addition to wet etch processes such as TMAH wet etch. The removal process may be a multi-step process to obtain the desired profile. After the removal process, there may be a recess that is shaped to direct the tip toward the channel region beneath the gate 712. These recesses can then be filled with the source / drain material. The source / drain material may be silicon germanium doped with a dopant for an NMOS device such as boron. The source / drain regions 714 may be formed through a LPCVD process using a silicon germanium based precursor gas as well as a gas containing a desired dopant type such as B ₂ H ₆ . The LPCVD process can occur at a temperature in the range of about 300-800 degrees centigrade and at a pressure in the range of about 1-500 torr.

The source / drain regions 718 may be formed by removing portions of the second semiconductor material layer 708 to form recesses on opposite sides of the gate 716. The material can be removed by using a multistage wet etch process that utilizes a variety of wet etchants such as H ₃ PO ₄ , H ₂ O ₂ , or HCl, or mixtures thereof. [Inventor: Dry etching process is also used here] After the removal process, there may be a recess formed such that the tip is directed to the channel region under the gate 716. These recesses can then be filled with the source / drain material. The source / drain material may be silicon germanium doped with a dopant for a PMOS device such as phosphorus. Source / drain regions 718 may be formed through the LPCVD process using a precursor gas placed a gas containing a desired dopant type, as well as based on silicon-germanium, such as PH _3. The LPCVD process can occur at a temperature in the range of about 300-800 degrees centigrade and at a pressure in the range of about 1-500 torr.

7H shows a structure in which NMOS device 705 and PMOS device 707 are formed adjacent to each other. The PMOS device 707 is on a different level than the NMOS device 705. Specifically, the PMOS device 707 is on a higher level than the NMOS device 705 with respect to the substrate 702. It is understood that the features of Figure 7h do not necessarily include all of the features that may be part of a transistor in an integrated circuit. For example, additional dielectric layers, metal contacts, and other features are part of the transistor device.

The use of the principles described herein provides a number of advantages. For example, using a particular type of channel material for NMOS and PMOS devices can provide more efficient transistors. Specifically, certain types of materials can lower tunneling barriers, thus lowering the voltage threshold. An integrated circuit composed of such transistors can consume less power during operation.

For example, in the case of an NMOS transistor, using a source / drain region comprised of a silicon germanium channel and doped silicon germanium, there is less lattice mismatch between the channel and the source / drain region. This leads to fewer potentials in the source / drain regions. Similarly, for PMOS transistors, using indium gallium arsenide as the channel material and using doped silicon germanium for the source / drain regions, there is also less lattice flint.

8 is a drawing 800 illustrating an exemplary tip portion 804 having a higher dopant concentration than the remaining portion 802 of the source / drain region. As described above, the source / drain region has a corner portion directed toward the channel side. For example, in the case of an NMOS device having a source / drain region doped with boron, the concentration of boron in the tip portion 804 of the device is higher. The tip portion 804 having a high dopant concentration can be formed before the remaining portion 802 of the source / drain region is formed. Specifically, after a portion of the semiconductor material is removed and before the source / drain material is deposited in the recess, a high concentration of tip portion 804 may be formed in the recess at a suitable location. In one example, the thickness 806 of the tip portion 804 with a high dopant concentration is approximately 5 nanometers.

9 is a drawing 900 showing an exemplary tip portion 904 with a superlattice structure. The remaining portion 902 of the source / drain region may be a common source / drain material. The superlattice structure alternates between two types of semiconductor materials. Specifically, the superlattice structure alternates between a first type of material 906 and a second type of material 908. For example, in the case of an NMOS device, the first material 906 may be silicon germanium doped with boron and the second material 908 may be silicon doped with boron. For a PMOS device, the first material 906 may be phosphorus doped silicon germanium and the second material 908 may be phosphorus doped silicon. In some cases, the two different materials 906 and 908 are both doped silicon germanium, but can have two different germanium concentrations. The thickness of each section of material (910, 912) may be approximately 3 nanometers.

Using the above technique for the tips of the source / drain regions, the current can be sent more efficiently through the channel. This allows the tunneling voltage to be further reduced, allowing the transistor to operate at lower power.

10 is a flow chart illustrating an exemplary method of forming a transistor with an improved channel. According to this example, the method 1000 can be used to form the structure shown in Figure 7h. The method 1000 includes a step 1002 for providing a first wafer comprising a semiconductor layer and a first layer of semiconductor material. The semiconductor layer may be a silicon-on-insulator substrate. The first semiconductor material layer may be a material intended for use in an NMOS device.

The method 1000 further includes a step 1004 for bonding a first wafer to a second wafer, wherein the second wafer comprises a sacrificial layer and a second layer of semiconductor material. The second channel layer may be a material intended for use in a PMOS device. The method further includes a step (1006) for removing the sacrificial layer. This is done after the wafer is bonded.

The method 1000 further includes the step 1008 of patterning the bonded substrate to create a first structure in the first region and a second structure in the second region. The first structure is used to form an NMOS device, and the second structure is used to form a PMOS device. The method 1000 further includes a step 1010 for removing a second semiconductor material from the first feature. This exposes the first semiconductor material.

The method 1000 further includes a step 1012 for forming a first type of transistor in the first semiconductor material of the first region. This involves forming a gate device and a source / drain region adjacent to the gate device. The source / drain regions may be formed such that they have a vertex pointing toward the channel region under the gate. The transistor device may have features as described in Figs. 2-9.

The method 1000 further includes a step 1014 for forming a second type of transistor in the second semiconductor material of the second region. This involves forming a gate device and a source / drain region adjacent to the gate device. The source / drain regions may be formed such that they have a vertex pointing toward the channel region under the gate.

According to one example, a transistor device comprises a substrate having a first region and a second region, a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, The first part is separated from the second part. The device further comprises a second semiconductor layer of a second semiconductor material on a second portion of the first semiconductor layer, a first transistor of a first conductivity type, and a second transistor of a second conductivity type, Drain region and a second set of source / drain regions formed in the second semiconductor layer, and the second transistor is disposed in the second region. The first conductivity type is different from the second conductivity type, and the second semiconductor material is different from the first semiconductor material.

According to one example, a transistor device includes a gate device, a source region having a vertex pointing towards the channel under the gate device, and a drain region having a vertex toward the channel. The tip at the apex of the tip and drain regions at the apex of the source region includes a superlattice structure.

According to one example, a method for manufacturing a semiconductor device includes providing a first wafer comprising a substrate and a first layer of semiconductor material, bonding a first wafer to a second wafer, And removing the sacrificial layer, patterning the bonded wafer to produce a first structure and a second structure, depositing a second semiconductor material from the first structure, Forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.

The foregoing has described features of various embodiments to enable those skilled in the art to more fully understand aspects of the disclosure. Those skilled in the art will readily appreciate that the present disclosure can readily be used as a basis for designing or modifying structures and other processes that achieve the same advantages of the embodiments introduced herein and / or perform the same purpose. Those skilled in the art should also realize that the equivalent constructions do not depart from the spirit and scope of the present disclosure and that various changes, substitutions and changes can be made herein without departing from the spirit and scope of the disclosure.

Claims (5)

In a transistor device,
Board;
A gate device on the substrate;
A source region in the substrate having a corner portion oriented toward a channel below the gate device, the source region including a tip portion and a remaining portion within the corner portion; And
A drain region in the substrate, the drain region having a corner portion directed toward the channel, the drain region including a tip portion and a remainder in the corner portion,
Wherein at least one of the tip portions of the source region and the drain region comprises a superlattice structure and wherein the superlattice structure is not located within the remaining portions of the source region and the drain region. In a transistor device,
Board;
A gate device on the substrate;
A source region in the substrate having a corner portion oriented toward a channel under the gate device, the source region including a tip portion within a corner portion of the source region; And
A drain region in the substrate having a corner portion oriented toward the channel, the drain region including a tip portion within a corner portion of the drain region,
Wherein at least one of the tip portions of the source region and the drain region comprises a superlattice structure wherein the superlattice structure alternates between silicon germanium and silicon in a direction perpendicular to the surface of the substrate, &Lt; / RTI &gt; has the same type of dopant. 2. The transistor device of claim 1, wherein each section of the superlattice structure has a thickness of 3 nanometers. 2. The transistor device of claim 1, wherein the tip portions of the source region and the drain region are doped with a higher concentration dopant than the remaining portions of the source region and the drain region. 5. The transistor device of claim 4, wherein the heavily doped dopant extends from the tip of the corner portion by 5 nanometers in a direction parallel to the surface of the substrate.

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