CN112382570B - PMOS manufacturing method - Google Patents
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- CN112382570B CN112382570B CN202011201682.4A CN202011201682A CN112382570B CN 112382570 B CN112382570 B CN 112382570B CN 202011201682 A CN202011201682 A CN 202011201682A CN 112382570 B CN112382570 B CN 112382570B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 89
- 238000010438 heat treatment Methods 0.000 claims abstract description 58
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000004151 rapid thermal annealing Methods 0.000 claims description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 229920006395 saturated elastomer Polymers 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000005259 measurement Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000007669 thermal treatment Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a method for manufacturing PMOS, which comprises the following steps: step one, forming a PMOS grid structure on a wafer, and forming embedded germanium-silicon epitaxial layers on two sides of the grid structure; measuring the on-chip distribution of the T2G on the wafer; thirdly, compensating the influence of the T2G on the stress of the channel region by utilizing the influence of the temperature of the heat treatment process on the stress of the channel region according to the temperature distribution of the heat treatment process of the distributed stress memory technology in the chip of the T2G, so that the difference of the stress of the channel region of each region on the wafer is reduced and meets the required value; and step four, carrying out the heat treatment process according to the set temperature distribution. The invention can realize the timely and dynamic adjustment of the PMOS product of the wafer and can improve the uniformity of saturated source leakage current in the chip, among chips and among batches of the product.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a PMOS manufacturing method.
Background
In order to improve the performance of PMOS, such as saturation source drain current (Idsat), a technology of increasing stress of a channel region, that is, a Stress Memory Technology (SMT), is adopted in the prior art, the SMT of PMOS is that an embedded sige epitaxial layer is formed in a source drain region, then, a SMT heat treatment process is performed on the sige epitaxial layer, so that the stress of the sige epitaxial layer is conducted into the channel region, thereby increasing mobility of hole carriers in the channel region, and finally, increasing Idsat of a device, so as to improve the performance of the device.
In the existing PMOS manufacturing method, idsat non-uniformity, i.e., uniformity of Idsat, of PMOS in the same wafer, among different wafers in the same lot, and among wafers in different lots is easily poor. One existing method to improve the uniformity of Idsat is by setting the Rapid Thermal Annealing (RTA) temperature of the SMT,
When the technology node is scaled down to 40nm or below 28nm, the SMT RTA temperature adjustment method for improving the uniformity of the Idsat of the PMOS comprises the following steps:
the product piece, i.e. the whole piece of the wafer with the PMOS product, idsat is measured first, and the large Idsat corresponds to the high SMT RTA temperature.
And comparing the Idsat intra-chip distribution pattern of the product chip with the resistance intra-chip distribution pattern of the baffle control chip for monitoring the SMT RTA temperature change, wherein no product is produced on the baffle control chip, the special test is performed, and the low resistance of the baffle control chip represents the high SMT RTA temperature. The comparison step comprises the following steps: whether the resistance corresponding to the baffle plate is lower at the place where the product plate is larger in heat transfer Idsat or whether the resistance corresponding to the baffle plate is higher at the place where the product plate is smaller in Idsat is checked, if the temperature distribution of the SMT RTA affects the distribution of the Idsat in the product plate, the thermal budget of different areas in the product plate needs to be adjusted, namely, the temperature of different annular areas of the SMT RTA heating lamp group needs to be manually adjusted. The existing SMT RTA adjustment method can only aim at the whole batch (lot) of products, and cannot dynamically adjust different silicon chips in the same batch, so that uniformity of device performance between chips cannot be improved.
In general, in the field of semiconductor integrated circuit fabrication, a silicon wafer corresponds to a wafer composed of a silicon substrate, a plurality of products can be formed on the same silicon wafer, and performance differences of product devices on the same silicon wafer correspond to on-chip differences; a plurality of silicon chips are placed in the same silicon chip box to form a batch of silicon chips, and the difference of products among the silicon chips in the same batch corresponds to the difference among the chips; the difference in product between different batches corresponds to the difference between batches.
Disclosure of Invention
The invention aims to provide a PMOS manufacturing method which can realize timely and dynamic adjustment of PMOS products of a wafer and can improve the uniformity of saturated source leakage current in the chips, among the chips and among batches of the products.
In order to solve the technical problems, the method for manufacturing the PMOS provided by the invention comprises the following steps:
forming a PMOS grid structure on a wafer, forming embedded germanium-silicon epitaxial layers on two sides of the grid structure, wherein the embedded germanium-silicon epitaxial layers are formed in grooves, and T2G is the interval between the tip of the embedded germanium-silicon epitaxial layers and the grid structure; the wafer is composed of a semiconductor substrate, a plurality of PMOS are integrated on the wafer, and a channel region is formed on the surface of the semiconductor substrate covered by the grid structure.
And step two, measuring the on-chip distribution of the T2G on the wafer.
And thirdly, according to the temperature distribution of the heat treatment process of the distributed stress memory technology in the chip of the T2G, the temperature of the heat treatment process corresponding to the area with larger T2G is higher, and the temperature of the heat treatment process corresponding to the area with smaller T2G is lower, the influence of the temperature of the heat treatment process on the stress of the channel region is utilized to compensate the influence of the T2G on the stress of the channel region, so that the difference of the stress of the channel region in each area on the wafer is reduced and all the stress values are satisfied.
And step four, carrying out the heat treatment process according to the set temperature distribution.
The method is further improved in that before the second step, a T2G target value, a qualified interval and a thermal budget tolerance interval are set according to the PMOS process requirement, and the thermal budget tolerance interval is located in the qualified interval.
In the second step, the method comprises the steps of calculating an on-chip average value of the T2G, and if the on-chip average value exceeds the qualified interval, directly scrapping the wafer in the second step.
And if the on-chip average value is in the qualified interval, performing a subsequent step III.
In a further improvement, in the second step, the T2G on the wafer has a feature of being distributed in a ring shape, and the wafer is divided into a plurality of ring-shaped areas.
In the third step, the temperature distribution of the heat treatment process is set according to each annular region.
In a further improvement, the temperature setting step of the heat treatment process corresponding to each annular region includes:
If the T2G of the annular region is located in the thermal budget tolerance zone, the temperature of the heat treatment process is kept to be an initial value, and the initial value is a temperature set value of the heat treatment process corresponding to the time when the T2G is equal to the T2G target value.
If the T2G of the annular region is below a lower limit of the thermal budget tolerance interval, the temperature of the thermal treatment process is reduced based on the initial value.
If the T2G of the annular region is higher than the upper limit value of the thermal budget tolerance interval, the temperature of the heat treatment process is increased on the basis of the initial value.
A further improvement is that the heat treatment process is rapid thermal annealing.
A further improvement is that the rapid thermal annealing of the heat treatment process adopts a lamp set for heating, the lamp set consists of a plurality of bulbs, and the on and off of each bulb is independently controlled by a control signal; the heating area of the lamp set is larger than or equal to the position area of the wafer; the temperature distribution of the heat treatment process is determined by controlling the number of turns on of the bulb in the region corresponding to the temperature.
A further improvement is that the bulbs in the lamp set are distributed in a ring shape.
The further improvement is that the annular area is a strip-shaped circular ring taking the circle center of the wafer as the circle center.
Further improvements are that the T2G is measured by OCD.
The upper limit of the qualified interval is the T2G target value plus 5nm, and the lower limit of the qualified interval is the T2G target value minus 5nm.
The upper limit of the thermal budget tolerance interval is the T2G target value plus 2nm, and the lower limit of the thermal budget tolerance interval is the T2G target value minus 2nm.
A further improvement is that the T2G target value is 45nm.
The further improvement is that in the first step, the gate structure is formed by overlapping a gate dielectric layer and a polysilicon gate, and the forming step of the gate structure comprises the following steps:
and forming the gate dielectric layer and the first polysilicon layer on the surface of the wafer in sequence.
And photoetching to define a forming area of the gate structure, and etching the first polysilicon layer to form the polysilicon gate.
The further improvement is that the gate dielectric layer is a gate oxide layer or the gate dielectric layer is a high dielectric constant layer.
The method is further improved in that after the grid structure is formed, a step of forming a side wall on the side face of the grid structure is further included.
The further improvement is that the groove is formed in the semiconductor substrate of the two layers of the side wall of the grid structure in a self-aligned mode through an etching process.
In a further improvement, the grooves are sigma-type grooves, and the forming step comprises:
And performing dry etching to form a U-shaped groove.
And continuing to etch the U-shaped groove by adopting TMAH etching liquid to form the sigma-type groove.
And the step of filling the embedded germanium-silicon epitaxial layer in the sigma-type groove is further included after the sigma-type groove is formed.
In the prior art, idsat in-chip distribution measurement is needed to be carried out on the formed PMOS product, then, temperature distribution of the heat treatment process of the stress memory technology is compared with temperature distribution of the resistor in-chip distribution obtained by measuring the shift control chip, and setting of SMT RTA temperature distribution of the PMOS product of the same batch of unfinished PMOS product can be realized only by measuring the finished PMOS product, but the Idsat of the finished product is not needed to be measured, after the embedded germanium silicon epitaxial layer is formed, in-chip distribution of T2G on a wafer is carried out before the heat treatment process of the SMT, and temperature distribution of the heat treatment process of the stress memory technology is set by the in-chip distribution of the T2G.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a flow chart of a method of manufacturing a PMOS according to an embodiment of the present invention;
Fig. 2 is a diagram showing a bulb distribution of a lamp set in a rapid thermal annealing process according to an embodiment of the present invention.
Detailed Description
FIG. 1 is a flow chart of a method for manufacturing PMOS according to an embodiment of the invention; the manufacturing method of the PMOS comprises the following steps:
forming a PMOS grid structure on a wafer, forming embedded germanium-silicon epitaxial layers on two sides of the grid structure, wherein the embedded germanium-silicon epitaxial layers are formed in grooves, and T2G is the interval between the tip of the embedded germanium-silicon epitaxial layers and the grid structure; the wafer is composed of a semiconductor substrate, a plurality of PMOS are integrated on the wafer, and a channel region is formed on the surface of the semiconductor substrate covered by the grid structure.
In the embodiment of the invention, the gate structure is formed by overlapping a gate dielectric layer and a polysilicon gate, and the forming steps of the gate structure include:
and forming the gate dielectric layer and the first polysilicon layer on the surface of the wafer in sequence.
And photoetching to define a forming area of the gate structure, and etching the first polysilicon layer to form the polysilicon gate.
The gate dielectric layer is a gate oxide layer or a high dielectric constant layer.
After the grid structure is formed, the method further comprises the step of forming a side wall on the side face of the grid structure.
And the groove is formed in the semiconductor substrate of the two side wall layers of the grid structure in a self-aligned mode through an etching process. The groove is a sigma-type groove, and the forming step comprises the following steps:
And performing dry etching to form a U-shaped groove.
And continuing to etch the U-shaped groove by adopting TMAH etching liquid to form the sigma-type groove.
And the step of filling the embedded germanium-silicon epitaxial layer in the sigma-type groove is further included after the sigma-type groove is formed.
And step two, measuring the on-chip distribution of the T2G on the wafer.
In the second embodiment of the present invention, the step two includes calculating an on-chip average value of the T2G, and if the on-chip average value exceeds the qualified interval, directly discarding the wafer in the step two.
And if the on-chip average value is in the qualified interval, performing a subsequent step III.
In the embodiment of the invention, before the second step, setting a T2G target value, a qualified interval and a thermal budget tolerance interval according to the process requirement of the PMOS, where the thermal budget tolerance interval is located in the qualified interval, these setting steps may be performed after the first step, may be performed before the first step, or may be performed in the same batch of PMOS products, where the T2G target value, the qualified interval and the thermal budget tolerance interval are performed when the first wafer is manufactured, and the set T2G target value, the qualified interval and the thermal budget tolerance interval may be directly adopted in the manufacturing process of each subsequent wafer, and the specific situation may be set according to the actual situation.
The T2G is measured by OCD.
In a preferred embodiment, the T2G target value, the pass interval and the thermal budget tolerance interval can employ the following parameters:
The upper limit of the qualified interval is the T2G target value plus 5nm, and the lower limit of the qualified interval is the T2G target value minus 5nm.
The upper limit of the thermal budget tolerance interval is the T2G target value plus 2nm, and the lower limit of the thermal budget tolerance interval is the T2G target value minus 2nm.
The T2G target value is 45nm.
In the second step, the T2G on the wafer has a feature of being distributed in a ring shape, and the wafer is divided into a plurality of ring-shaped areas. The annular region is a band-shaped ring taking the circle center of the wafer as the circle center.
And thirdly, according to the temperature distribution of the heat treatment process of the distributed stress memory technology in the chip of the T2G, the temperature of the heat treatment process corresponding to the area with larger T2G is higher, and the temperature of the heat treatment process corresponding to the area with smaller T2G is lower, the influence of the temperature of the heat treatment process on the stress of the channel region is utilized to compensate the influence of the T2G on the stress of the channel region, so that the difference of the stress of the channel region in each area on the wafer is reduced and all the stress values are satisfied.
In the third embodiment of the present invention, the temperature distribution of the heat treatment process is set according to each annular region. The temperature setting step of the heat treatment process corresponding to each annular region comprises the following steps:
If the T2G of the annular region is located in the thermal budget tolerance zone, the temperature of the heat treatment process is kept to be an initial value, and the initial value is a temperature set value of the heat treatment process corresponding to the time when the T2G is equal to the T2G target value.
If the T2G of the annular region is below a lower limit of the thermal budget tolerance interval, the temperature of the thermal treatment process is reduced based on the initial value.
If the T2G of the annular region is higher than the upper limit value of the thermal budget tolerance interval, the temperature of the heat treatment process is increased on the basis of the initial value.
And step four, carrying out the heat treatment process according to the set temperature distribution.
In the embodiment of the invention, the heat treatment process is rapid thermal annealing.
The rapid thermal annealing of the heat treatment process adopts a lamp set for heating, the lamp set consists of a plurality of bulbs, and the on and off of each bulb is independently controlled by a control signal; the heating area of the lamp set is larger than or equal to the position area of the wafer; the temperature distribution of the heat treatment process is determined by controlling the number of turns on of the bulb in the region corresponding to the temperature.
The bulbs in the lamp set are distributed in a ring shape.
As shown in fig. 2, the bulb distribution diagram of the lamp set in the rapid thermal annealing process according to the embodiment of the present invention; in fig. 2, the group 200 is formed by densely distributing a plurality of bulbs 201, and a plurality of bulbs 201 further form an annular distribution structure, and the annular distribution structure is described as follows:
Lines indicated by arrow lines of the reference numeral 202 correspond to boundary lines of the annular distribution of the bulb 201, and in fig. 2, the bulbs 201 are further numbered according to the annular distribution area in which the bulbs 201 are located, for example: the bulbs 201 of the innermost annular distribution areas are respectively numbered from 001 to 002 to 007;
The bulbs 201 of the annular distribution area of the outer layer are respectively numbered from 101 to 102 to 118;
The number of the lamp bulbs 201 in the annular distribution area of the outer layer is 2 in percentage, namely the distribution is numbered from 201, 202 to 230;
and so on until all numbering of the bulbs 201 of the annular distribution areas of the layers is complete.
Wherein, after the number of hundred digits is more than 9, the numbers are respectively denoted by A, B, C, D and E.
By numbering each of the bulbs 201, it is possible to realize individual control of each of the bulbs 201, and at the time of performing the rapid thermal annealing, a profile composed of the bulbs 201 that are turned on is realized, the profile composed of the bulbs 201 that are turned on being determined by the set temperature profile and an actual temperature profile that matches the set temperature profile is formed in the rapid thermal annealing.
In fig. 2, the circle indicated by reference 203 corresponds to the inner edge of the chamber body of the rapid thermal annealing process chamber.
The circle indicated by reference 204 corresponds to the position of the edge ring of the rapid thermal anneal process chamber.
The circle indicated by reference 205 corresponds to the location of the wafer in the process chamber of the rapid thermal anneal. It can be seen that the extent of the lamp assembly 200 is greater than the extent of the wafer.
In fig. 2, the positions where a plurality of temperature probes are arranged are also marked, as shown by marks 1, S, 2,3, 4, E, 5, 6 and 7, respectively, and the temperatures at the corresponding positions can be obtained by testing the temperature probes.
In the embodiment of the invention, the T2G distribution non-uniformity is utilized to influence the non-uniformity of the Idsat of the PMOS, so that the temperature distribution of the heat treatment process of the SMT is not required to be set by measuring the Idsat of the PMOS product, but the heat treatment distribution of the SMT is directly set by measuring the T2G distribution. The distribution of T2G is not uniform and is related to the process of forming the embedded sige epitaxial layer, which is formed in a recess, typically a sigma-type recess. The sigma type grooves are usually formed by dry etching and wet etching with TMAH, so that the dimensional structure of the grooves inevitably changes, i.e. the dimensions of the grooves in different areas deviate to a certain extent. This makes the T2G distribution uneven. Since the change of the carrier mobility of the channel region is determined by the change of the stress of the channel region, when T2G is different, the effect of the embedded sige epitaxial layer on the stress of the channel region is different: if T2G is smaller, the embedded germanium-silicon epitaxial layer is closer to the channel region, so that the stress influence on the channel region is larger, and the Idsat of the device is larger finally; conversely, when T2G is larger, the stress effect of the embedded sige epi layer on the channel region becomes smaller, so that Idsat becomes smaller.
Therefore, compared with the prior art, the Idsat in-chip distribution measurement is needed for the formed PMOS product, and then the temperature distribution of the SMT RTA temperature distribution is different from the temperature distribution of the resistance chip obtained by the control chip measurement, the prior art can only realize the temperature distribution of the SMT RTA of the PMOS product of the same batch of unfinished PMOS product by measuring the finished PMOS product, the Idsat in-chip distribution of the T2G on the wafer is needed before the SMT heat treatment process is carried out after the embedded germanium silicon epitaxial layer is formed, and the temperature distribution of the heat treatment process of the stress memory technology is set by the T2G in-chip distribution.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (17)
1. A method for manufacturing PMOS, comprising the steps of:
Forming a PMOS grid structure on a wafer, forming embedded germanium-silicon epitaxial layers on two sides of the grid structure, wherein the embedded germanium-silicon epitaxial layers are formed in grooves, and T2G is the interval between the tip of each embedded germanium-silicon epitaxial layer positioned on the side face of each groove and the side face of the adjacent grid structure; the wafer consists of a semiconductor substrate, a plurality of PMOS are integrated on the wafer, and a channel region is formed on the surface of the semiconductor substrate covered by the grid structure;
measuring the on-chip distribution of the T2G on the wafer;
Thirdly, according to the temperature distribution of the heat treatment process of the distributed stress memorization technology in the chip of the T2G, the temperature of the heat treatment process corresponding to the area with larger T2G is higher, and the temperature of the heat treatment process corresponding to the area with smaller T2G is lower, the influence of the temperature of the heat treatment process on the stress of the channel region is utilized to compensate the influence of the T2G on the stress of the channel region, so that the difference of the stress of the channel region in each area on the wafer is reduced and all the stress meets the requirement value;
and step four, carrying out the heat treatment process according to the set temperature distribution.
2. The method for manufacturing PMOS according to claim 1, wherein: before the second step, setting a T2G target value, a qualified interval and a thermal budget tolerance interval according to the PMOS process requirement, wherein the thermal budget tolerance interval is positioned in the qualified interval.
3. The method for manufacturing PMOS according to claim 2, wherein: step two, calculating an on-chip average value of the T2G, and if the on-chip average value exceeds the qualified interval, directly scrapping the wafer in the step two;
and if the on-chip average value is in the qualified interval, performing a subsequent step III.
4. The method for manufacturing PMOS as defined in claim 3, wherein: in the second step, the T2G on the wafer has the characteristic of being distributed in a ring shape, and the wafer is divided into a plurality of ring-shaped areas;
In the third step, the temperature distribution of the heat treatment process is set according to each annular region.
5. The method for manufacturing PMOS according to claim 4, wherein: the temperature setting step of the heat treatment process corresponding to each annular region comprises the following steps:
if the T2G of the annular region is located in the thermal budget tolerance zone, the temperature of the heat treatment process is kept to be an initial value, and the initial value is a temperature set value of the heat treatment process corresponding to the time when the T2G is equal to the T2G target value;
If the T2G of the annular region is lower than the lower limit value of the thermal budget tolerance interval, reducing the temperature of the heat treatment process on the basis of the initial value;
if the T2G of the annular region is higher than the upper limit value of the thermal budget tolerance interval, the temperature of the heat treatment process is increased on the basis of the initial value.
6. The method of manufacturing a PMOS as claimed in any one of claims 1 to 5, characterized in that: the heat treatment process is rapid thermal annealing.
7. The method for manufacturing PMOS according to claim 6, wherein: the rapid thermal annealing of the heat treatment process adopts a lamp set for heating, the lamp set consists of a plurality of bulbs, and the on and off of each bulb is independently controlled by a control signal; the heating area of the lamp set is larger than or equal to the position area of the wafer; the temperature distribution of the heat treatment process is determined by controlling the number of turns on of the bulb in the region corresponding to the temperature.
8. The method for manufacturing PMOS according to claim 7, wherein: the bulbs in the lamp set are distributed in a ring shape.
9. The method for manufacturing PMOS according to claim 4, wherein: the annular region is a band-shaped ring taking the circle center of the wafer as the circle center.
10. The method for manufacturing PMOS according to claim 2, wherein: the T2G is measured by OCD.
11. The method for manufacturing PMOS according to claim 10, wherein: the upper limit of the qualified interval is the T2G target value plus 5nm, and the lower limit of the qualified interval is the T2G target value minus 5nm;
The upper limit of the thermal budget tolerance interval is the T2G target value plus 2nm, and the lower limit of the thermal budget tolerance interval is the T2G target value minus 2nm.
12. The method for manufacturing PMOS according to claim 11, wherein: the T2G target value is 45nm.
13. The method for manufacturing PMOS according to claim 1, wherein: in the first step, the gate structure is formed by overlapping a gate dielectric layer and a polysilicon gate, and the forming step of the gate structure comprises the following steps:
Sequentially forming the gate dielectric layer and the first polysilicon layer on the surface of the wafer;
And photoetching to define a forming area of the gate structure, and etching the first polysilicon layer to form the polysilicon gate.
14. The method for manufacturing PMOS according to claim 13, wherein: the gate dielectric layer is a gate oxide layer or a high dielectric constant layer.
15. The method for manufacturing PMOS according to claim 13, wherein: after the grid structure is formed, the method further comprises the step of forming a side wall on the side face of the grid structure.
16. The method for manufacturing PMOS according to claim 15, wherein: and the groove is formed in the semiconductor substrate of the two side wall layers of the grid structure in a self-aligned mode through an etching process.
17. The method for manufacturing PMOS according to claim 16, wherein: the groove is a sigma-type groove, and the forming step comprises the following steps:
performing dry etching to form a U-shaped groove;
continuing to etch the U-shaped groove by adopting TMAH etching liquid to form the sigma-type groove;
And the step of filling the embedded germanium-silicon epitaxial layer in the sigma-type groove is further included after the sigma-type groove is formed.
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| US9324622B2 (en) * | 2012-08-15 | 2016-04-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
| US10892328B2 (en) * | 2019-03-04 | 2021-01-12 | International Business Machines Corporation | Source/drain extension regions and air spacers for nanosheet field-effect transistor structures |
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| TW421832B (en) * | 1999-09-23 | 2001-02-11 | Applied Materials Inc | Method for adjusting the temperature distribution on the wafer surface in a thermal treatment |
| CN1797783A (en) * | 2004-12-28 | 2006-07-05 | 富士通株式会社 | Semiconductor device and fabrication method thereof |
| CN105720090A (en) * | 2014-12-23 | 2016-06-29 | 台湾积体电路制造股份有限公司 | Improved transistor channel |
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