TW201513266A - Wafer, method for forming a test structure and method for forming a semiconductor structure - Google Patents

Abstract

A method for forming a semiconductor structure is disclosed, comprising: forming a semiconductor device on a wafer having a substrate; and forming a test key on the substrate and in a scribe line of the wafer, comprising: forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer; and forming a plurality of test pads from a semiconductor material, the plurality of test pads formed on the substrate and separated by at least one of the plurality of STIs, at least a first test pad of the plurality of test pads having physical characteristics related to a portion of the semiconductor device.

Description

Wafer, method of forming test structure and method of fabricating semiconductor structure

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a test cell and a method of fabricating the same.

Semiconductor devices are widely used in applications of various electronic devices, such as personal computers, cell phones, digital cameras, and other electronic devices. A semiconductor device is generally fabricated by depositing a material of an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and patterning various layers of material using lithography techniques to form circuit components and cells.

The semiconductor industry continues to improve the integration of various electronic components (such as transistors, diodes, capacitors, etc.) by reducing the minimum pattern size, allowing more components to be integrated into specific areas. As the grain size shrinks and the number of components increases, the reliability of a single component such as a transistor becomes more critical. For example, a wafer test can be performed before and between the formation of layers and structures thereon.

The present invention provides a method of fabricating a semiconductor structure, comprising: forming a semiconductor device on a wafer, wherein the wafer has a substrate; and forming a test key on the substrate of the wafer and the cutting line, comprising: forming a plurality of Shallow trench Separating the structure on the substrate of the wafer and in the dicing line; forming a plurality of test pads including a semiconductor material, the test pads being formed on the substrate and separated by at least one of the shallow trench isolation structures, at least one of the test pads A first test pad has physical properties associated with a portion of the semiconductor device.

The present invention provides a method of forming a test structure, comprising: forming a plurality of shallow trench isolation structures on a substrate of a wafer and a dicing line of the wafer; forming a test key on the substrate of the wafer and cutting the wafer In the line, forming the test key comprises: forming at least one test key group, having a plurality of test key series, each test key series having a plurality of test pads formed of a semiconductor material, in at least one test key group, each test The key series has a first physical characteristic that is different from the first physical characteristic of the other test key series.

The present invention provides a wafer comprising: at least one dicing street defined on one of the substrates of the wafer, at least one scribe line separating the die regions; and at least one test key series in at least one scribe line, at least one test key series The method includes: a plurality of test pads, each test pad is separated from another test pad by a shallow trench isolation structure; wherein each test pad in each of the at least one test key series has at least one fin, and at least one test in the test key series The mat has a different number of fins.

100‧‧‧ wafer

102‧‧‧ grain

104‧‧‧Test key

106‧‧‧ cutting line

108‧‧‧Test key series

110‧‧‧Test pad

110a-110n‧‧‧ test pad

112‧‧‧Fins

202a-202b‧‧‧Test Key Group

204a-204d‧‧‧ test key series

300‧‧‧ unique test button

302a-302d‧‧‧ test pad

402‧‧‧Base

404‧‧‧Shallow trench isolation

406‧‧‧Material section

408‧‧‧Base surface

410‧‧‧Test pad area

412‧‧‧ Epitaxial

414‧‧‧ top surface of the epitaxial layer

416‧‧‧ mask

418‧‧‧impedance

420‧‧‧planting

422‧‧‧Doped test pad

424‧‧‧Undoped test pads

502‧‧‧ epitaxial growth test pad

504‧‧‧Second epitaxial test pad

602‧‧‧ epitaxial test pad

604‧‧‧Doped test pad

700‧‧‧ method

702, 720, 724, 726, 728, 740, 742, 744, 746, 760, 762, 764 ‧ ‧ steps

800‧‧‧ system

802‧‧‧ computer

804‧‧‧ Probe Controller

806‧‧‧ probe

808‧‧‧ data receiver

Figures 1A through 1C show the configuration of an embodiment test pad.

Figure 2 shows a top view of an embodiment test key.

Figure 3 shows a top view of a single test key of an embodiment.

4A through 4H are cross-sectional views showing an intermediate stage of forming a selective doping test pad in an embodiment.

5A through 5J are cross-sectional views showing an intermediate stage of forming a test pad having different epitaxial conditions in an embodiment.

6A through 6D are cross-sectional views showing an intermediate stage of forming a selective doping test pad process in an embodiment.

Figure 7 is a flow chart showing an embodiment of a method of forming and using test keys on a substrate.

Figure 8 is a block diagram showing any embodiment of a system for testing wafers with test keys.

The manufacture and use of the proposed embodiments are discussed in detail below. However, it should be understood that the present disclosure provides many applicable concepts that can be implemented in various specific contexts. The specific embodiments discussed are merely illustrative of specific methods for making and using the described grain level test keys, and do not limit the scope of the present disclosure.

Embodiments will be described in a specific hereinafter by preparing and using test keys, for example, testing and cutting a die or wafer after fabrication of the integrated circuit. However, other embodiments of the invention are also applicable to substrates, structures or devices or any type of integrated circuit device or combination of components.

Embodiments of the present invention discuss variations of the embodiments with reference to FIGS. 1A through 7. In the various figures and exemplary embodiments of the invention, the same reference numerals are used to designate the same. In addition, the drawings are illustrative, and are not intended to limit the invention. It should be noted that for the sake of simplicity, not all unit symbols are included in each subsequent figure. Rather, the unit symbols most relevant to the description of the various figures are included in the figures.

The embodiments described herein relate to the formation and testing of wafer-level test keys whose physical properties are related to the physical characteristics of the semiconductor device (formed on the die of the wafer). In one embodiment, the test pads are formed using the same process of forming a semiconductor device that can be tested and tested without contaminating or interfering with the fabrication device. The test pad can also be formed in the scribe line of the wafer, so the test pad can be removed while the cut is being made. The test pads are placed on the fabricated wafer instead of using sacrificial wafers to reduce wafer-to-wafer variations that may not be detected by the test wafer. Test keys having one or more test pads can also test for example strain relaxation, dopant activation and deactivation or similar physical properties.

1A is a top view showing a wafer 100 having a plurality of dies, and the die 102 includes test keys 104. The die 102 is disposed on the wafer 100 and the die 102 is separated by a cut line 106 or a scribe line. Although only a few of the dies 102 are shown in the drawings for clarity, any number of dies may be included on the wafer or workpiece. The dies 102 are separated on the wafer 100 by a dicing line 106 to provide space for dicing (including mechanical dicing, laser dicing of other dicing systems) such that the dicing of the dies 102 into a single dies 102 does not cleave or damage the dies. Granule 102. The test key 104 has one or more test pads 110 and is disposed in the cutting line 106 so that the test keys 104 can be removed while the wafer 100 is being cut. Setting the test key 104 in the dicing line 106 allows the test key 104 to be placed on the wafer 100 without occupying the space of the die 102.

Figure 1B shows the test button 104 in one embodiment. The test button 104 has one or more test key series 108, and each test key series 108 has a series of test pads 110a-110n that share at least one feature. For example, the test pads 110a-110n of the first test key series 108 may have a first The epitaxial property, the test pads 110a-110n of the second test key series 108 may have a second epitaxial property. In another example, the test pads 110a-110n of the first test key series 108 can have similar first doping profiles, and the test pads 110a-110n of the second test key series 108 can have similar second doping profiles.

The test pads 110a-110n are formed as part of the substrate of the wafer 100 or formed in the wafer 100. In addition, the test pads 110a-110n may be formed in a partial process for fabricating the integrated circuit structure of the die. Forming the test pads 110a-110n and the die 102 using the same process results in physical properties of the test pads 110a-110n similar to those of the die 102 structure. Therefore, test pads 110a-110n can be used to test the characteristics of wafer 100 during the process. For example, test pad 110 can be formed in a germanium substrate with a doping profile that is the same as the source or drain of the transistor in die 102. In another example, test pad 110 has one or more epitaxial regions, fins, or the like that are associated with one or more patterns or structures in die 102.

Figure 1C is a schematic diagram showing a test key series 108 of an embodiment. The test key series 108 has a series of different test pads 110a-110d. For example, test pads 110a-110d can be fins 112 of different sizes. For example, test pad 110a can have fins or all (or substantially all) surfaces of test surfaces having specific physical properties. In this example, the test surface of the first test pad 110a can be a single large size fin. The second test pad 110b can have relatively narrow fins 112, while the third test pad 110c can have fewer, wider fins 112, and the fourth test pad 110d can have fewer, wider fins 112. The width and length of the fins 112 can range from a few nanometers to a few microns. In one embodiment, the fins 112 have a width and length between about 2 nm and about 3 [mu]m, while the fins 112 have a length that is at least twice the width of the fins 112. In one embodiment, the fins 112 have physical properties associated with the structure of the die 102 that can form a crystal The process of the granular structure is tested without disturbing or contaminating the grain structure.

In a single test key series, the fins 112 of the second, third, and fourth test pads 110b-110d have one or more physical characteristics similar or identical to the first test pad 110a. For example, test pads 110a-110d can have fins 112 including germanium formed using an epitaxial growth process. In addition, the test surface or fin 112 can be formed from a material or process to impart a predetermined strain on the material. In this example, the test surface or fins 112 may be formed by epitaxially grown SiGe over a single substrate to create a strained region. The fins 112 of the test pads 110a-110n thus comprise a different semiconductor compound than the substrate, and the test pads 110a-110n may all have similar physical properties. In another example, gallium arsenide or other semiconductor layers can be epitaxially grown over germanium or other substrates (the lattice constant does not match the strain of the fins 112). Due to the strain of fins 112 of different sizes, the layout of the different fins 112 reflects the different electron or hole mobility in the fin material.

The test pads 110a-110n are sized to allow for contact type testing or non-contact damage, or damage testing. Contact type testing such as 4-point probe (4PP), spread resistance measurement (Spreading) Resistance Profiling (SRP), damage testing such as Secondary ion mass spectrometer (SIMS). In one embodiment, the test pad has a width of at least about 50 [mu]m and a length of at least about 50 [mu]m. The depth of the test pad 110 is less than about 100 nm, and in one embodiment, the depth of the test pad 110 is between about 10 nm and 90 nm. The test pad 110 is also limited by the width of the cutting line, and the test pad 110 is narrower than the cutting line 106 in at least one dimension such that the test pad 110 can be removed during the die cutting process. The test key 104 is placed in the dicing line 106 so that contact type or non-defective testing can be performed during the wafer process without disturbing the final integrated circuit. For example, a 4PP The test may use a metal probe to leave metal contamination on the test pad 110, and placing the test key 104 in the cutting line 106 limits contamination to the area of the cutting line 106. Similarly, SIMS testing can cause crystal damage to the surface when making samples. Setting the test key 104 in the cutting line 106 prevents damage caused by the test key 104 without affecting the final device of the die 102.

Figure 2 shows a top view of an embodiment test key 104 with test key 104 having test key groups 202a, 202b. Test key 104 may have one or more test key groups 202a, 202b, each test key group 202a, 202b having one or more test key series 204a-204d. Each test key series 204a can have one or more test pads 110a-110d. Different test key groups 202a, 202b, different test key series 204a-204d and different test pads 110a-110d can be used to define different physical property variables, such as epitaxial layer type, strain, doping type or concentration , fin size or other useful characteristics. In one embodiment, the first test pads 110a-110d of the first test key group 202a have a first epitaxial layer type, and the test pads 110a-110d of the second test key group 202b have a second epitaxial layer type. state.

In addition, the test pads 110a-110d of the various test key series 204a-204d have different doping profiles. For example, the first test key series 204a does not have doping or implantation, and the second, third, and fourth test key series 204b, 204c, 204d have different doping concentrations. The test pads 110a-110d in the test key series 204a-204d have various fin 112 configurations, the first test pad has a single fin, and the second, third, and fourth test pads 110b, 110c, 110d have fins 112 of various widths. In some embodiments, test pads 110a-110d have at least one fin 112, wherein each test pad 110a-110d has a different number of fins 112. In an embodiment, the fins 112 are sized such that the 4PP probe can contact a plurality of fins to advance The test is performed and the test results are adjusted to test the plurality of fins 112 in the test pads 110a-110d while the probes are being used.

Figure 3 shows a top view of an embodiment unique test key 300. This unique test key 300 has test pads 302a-302d of different physical characteristics. In this unique test pad 300, the test pads 302a-302d can be selected to replicate a particular pattern of structures in the die 102, such as fins in a fin field effect transistor (FinFET) or the like. structure. The test key 300 in the dicing line 106 can have a replicated pattern in the die 102, and the test for the test key 300 does not contaminate the actual die 102, and the test key 300 can provide device characteristics on the wafer 100 during the process. Accurate test information. For example, for a die 102 having a FinFET, a fin 112 can be fabricated in the test key 300, and the epitaxial profile, size, or doping profile of the fin 112 is similar to an actual FinFET fin. The test key 300 can be tested at various stages of the device process to determine that the process is proceeding correctly and that the test does not interfere with or contaminate the FinFET. For example, a P-channel FinFET can have a fin that can be 5 μm in length and 200 nm in width, and can include SiGe, fabricated via selective epitaxy, and subsequently doped with boron implants. The test pad 302a can have fins 112 similar to those fabricated and implanted in the same procedure as the FinFET device, or can be fabricated in separate processes. In addition, other test pads 302b-302d having different physical properties may also be formed. For example, test pads 302b-302d having higher doping or narrower fins 112 can be fabricated to test various similar FinFET devices to determine if the process technology is producing a particular structure that can be used. The test pads 302a-302d of the test key 300 produced will be subjected to the same process as the FinFET. For example, implant dopants to form a source or drain in the FinFET that activates the test bond 300 so that annealing or drive in heat is ensured during testing The process does not deactivate, diffuse, or otherwise fail the channel dopant due to the thermal process. Similarly, strain, impedance, carrier mobility, or the like can be tested in test key 300 to ensure that subsequent device units do not cause FinFET failure. When test key 300 as shown in FIG. 3 has test pads 302a-302d having repeating or similar characteristics for a single target FinFET, test key 300 may have additional test pads 110 that repeat other FinFETs, or may have multiple test pads 110 , copying a single device or a type of device, testing with different test pads or testing under the same conditions at different stages of the process.

4A through 4H are cross-sectional views showing an intermediate stage of forming a selective doping test pad 110 in an embodiment. Although the system and method of making test pad 110 are described in the drawings, the description herein is not limited to making a single test pad and is not limited to the structure of test pad 110, such as single or multiple fins 112 or other structures.

Figure 4A shows a cross-sectional view of the initial stage of forming a selectively doped test pad. First, one or more shallow trench isolations (STIs) are formed in a substrate 402. Substrate 402 can be substrate 402 of wafer 100, an epitaxial layer, or a semiconductor on insulator or similar layer. The base pad portion 406 is disposed between the STIs 404 with the body portion of the substrate 402 under the STI 404 and the pad portion 406 of the substrate 402. In one embodiment, the STI 404 is formed by masking and etching the substrate 402, and then the etched trench is filled with an insulating material such as hafnium oxide, tantalum carbide, glass, tantalum nitride or the like. The STI 404 material can be deposited by, for example, chemical vapor deposition, plasma assisted chemical vapor deposition, spin coating, or the like. A planarization step, such as chemical mechanical polishing, is performed on the STI 404 to align the surface of the STI with the substrate surface 408.

Figure 4B shows a cross-sectional view of the formation of test pad region 410. The substrate surface 408 is recessed or lowered to be below the top surface of the STI. For example, substrate 402 is selectively etched or a similar process is performed to form test pad region 410. In an embodiment, the substrate 402 is lowered to a predetermined depth corresponding to the desired fin height. For example, the height of the fins 112 of a test key 104 (see FIG. 1B-3) may be between about 10 nm and about 90 nm, so the substrate surface 408 is between about 10 nm and about 90 nm below the top surface of the STI 404.

Figure 4C shows a cross-sectional view of the formation of the epitaxial layer 412. An epitaxial growth technique is performed, for example, to form an epitaxial layer 412 over the recessed substrate. Epitaxial layer 412 has an epitaxial layer top surface 414 located on or above the top surface of STI 404. In one embodiment, the epitaxial layer 412 is SiGe, but the epitaxial layer 412 can comprise any suitable material including, but not limited to, tantalum, niobium carbide, gallium arsenide, or the like. Moreover, although the epitaxial layer 412 described herein is formed by an epitaxial process, the epitaxial layer 412 can also be formed using any suitable deposition or formation process. For example, the substrate 402 can be an insulator, and the epitaxial layer 412 can be deposited by chemical vapor deposition or the like.

Figure 4D shows a cross-sectional view of the reduced epitaxial layer 412. The epitaxial layer 412 is planarized or lowered such that the top surface of the epitaxial layer is slightly horizontal or aligned with the top surface 414 of the STI 404.

Figure 4E shows a cross-sectional view of the masking epitaxial layer 412 for implantation. A mask 416 is formed over the epitaxial layer 412 and an impedance 418 is formed over the mask 416. The mask 416 reduces the amount of subsequent thermal process strain relaxation and dopant diffusion. In one embodiment, the impedance 418 is formed by performing an upper resist layer, exposure, and development, but in other embodiments may be an additional mask patterning junction. Structure. The impedance 418 can cover one or more test pad regions 410 to avoid contamination of other test pad regions 410 as the implant progresses.

Figure 4F shows a cross-sectional view of the implanted portion of the epitaxial layer 412. A implantation step 420 can be performed on portions of the epitaxial layer 412 to form a doped test pad 422. For example, boron can be implanted in test pad 422 to produce P-type doping.

Figure 4G shows a cross-sectional view of the removed impedance 418. In an embodiment, when the impedance 418 is a photoresist mask, the impedance 418 can be removed, such as by ashing and cleaning. In another embodiment where the impedance 418 is a hard mask, the impedance 418 can be removed by etching, grinding, or other suitable process. When the mask 416 is positioned over the implanted test pad 422, the implanted test pad 422 can also be thermally activated, annealed, or otherwise.

Figure 4H shows a cross-sectional view of the removal mask 416. The mask 416 is removed using grinding, chemical mechanical polishing, etching, or other suitable process. The remaining epitaxial layer 412 acts as an undoped test pad 424, and the doped test pad 422 and the undoped test pad 424 are separated by an STI 404.

5A through 5J are cross-sectional views showing an intermediate stage of forming a test pad 110 having different epitaxial characteristics in an embodiment. Figure 5A shows a cross-sectional view of a substrate 402 masked to form various epitaxial property test pads. First, one or more shallow trench isolation structures 404 are formed in a substrate 402 as described in FIG. 5A. A mask 416 is formed over the substrate 402 to form an impedance 418 over the mask 416. The mask 416 can serve as a hard mask for defining an area of subsequent epitaxial growth. The mask 416 is etched to expose one or more test pad regions 410.

Figure 5B shows a cross-sectional view of the removed impedance 418. The mask 416 is patterned via, for example, etching and the impedance 418 is removed. Can be ashed and cleaned, for example, The resist 418 is removed by selective etching, grinding, or other suitable process. The mask 416 is patterned to cover at least one region where the test pad 110 is formed to selectively test the pad region 410 for selective etching and epitaxial growth of the test pad.

Figure 5C shows a cross-sectional view of the formation of test pad region 410. The surface 408 of the substrate is lowered or recessed below the top surface of the STI 404. The substrate 402 is selectively etched or lowered as described in FIG. 4B to produce a test pad region 410. In the illustrated embodiment, a single test pad region 410 is fabricated and the second test pad region is lowered and an epitaxial growth test pad 502 is filled in a subsequent step (see, for example, Figures 5D-5F). This individual epitaxially grown test pad allows different test pads to be formed with different epitaxial properties.

Figure 5D shows a cross-sectional view of an epitaxial layer 502 formed in a single test pad region 410. Although the graph shows that the epitaxial layer 502 is located in a single test pad region 410, it will be appreciated that the plurality of test pad regions 410 can be lowered and filled into the epitaxial layer 502 in a single step. The epitaxial layer 502 can be formed in the manner described in the above FIG. 4C. In one embodiment, the epitaxial layer is SiGe, however the epitaxial layer 412 can comprise any suitable material including, but not limited to, tantalum, niobium carbide, gallium arsenide or the like.

Figure 5E shows a cross-sectional view of the reduced epitaxial layer 412. The mask 416 is removed, for example, by chemical mechanical polishing or a suitable process, and the epitaxial test pad 502 is planarized. The top surface of the formed epitaxial layer is substantially aligned with the top surface of the STI 404.

Figures 5F through 5I show cross-sectional views of forming a separate second epitaxial test pad 504. A mask 416 is formed, and the masks 416 of the 5F and 5G patterns are patterned using the methods of 5A to 5B. As shown in Figure 5H, by reducing substrate formation The second test pad region 410, and as shown in FIG. 5I, grows a second epitaxial test pad 504 in the second test pad region 410. In an embodiment, the second epitaxial test pad 504 has different characteristics than the first epitaxial test pad 502.

Figure 5J shows a cross-sectional view of the removal mask 416 and the reduction of the second epitaxial test pad 504. The second epitaxial test pad 504 is lowered such that its top surface is substantially aligned with the top surface of the STI 404. In one embodiment, chemical mechanical polishing, grinding or other suitable process removal mask 416 is performed and the second epitaxial test pad 504 is lowered. The structure is formed such that the first epitaxial test pad 502 and the second epitaxial test pad 504 are separated by STI, and the first epitaxial test pad 502 and the second epitaxial test pad 504 have different compositions, materials or other characteristics.

6A through 6D are cross-sectional views showing an intermediate stage of implanting a test pad with an implant scanner in an embodiment. Figure 6A shows a cross-sectional view of the initial structure with test pad 602. Epitaxial test pads 602 can be disposed between STIs 404, and in one embodiment, can be fabricated using the procedures discussed in Figures 5A-5J.

Figure 6B shows a cross-sectional view of the implant 420 with an implant scanner. First, a mask 416 is placed over the epitaxial test pad 602. One or more epitaxial test pads 602 can be implanted using an implanter to form a doped test pad 604. As shown in FIG. 6C, the implanter 602 is moved over a different epitaxial test pad 602 and a implant 420 is placed on the additional test pad 602. In an embodiment, the implanter can implant the epitaxial test pads with different dopants, doping them to different concentrations, or generate doping test pads 604 having different doping profiles with different implant parameters. . The implanter can implant one or more different die 102 structures to form a doped test pad 604 whose doping profile is related to the doping profile of the die 102 structure.

The test pad fabrication procedures described herein with respect to Figures 4A through 6D should be understood to be non-limiting and not considered separately. For example, the test pad 110 fabrication procedure for Figures 5A through 5J can be used to form test pads 110 having different epitaxial characteristics, and thereafter, the test pads can be shaded and implanted as described in Figures 4A through 4H, Or doping with the implant scanner described in Figures 6A through 6D.

Figure 7 is a flow diagram showing an embodiment of a method 700 of forming and using test keys on a substrate. In step 702, an STI is formed, and then one or more epitaxial pads are formed between the STIs in step 720. In step 724, a test pad region is formed by patterning a mask over the substrate to form an epitaxial pad as desired, and subsequently recessing the substrate in step 724. An epitaxial layer is formed in the test pad region in step 726, and the epitaxial layer is subsequently lowered in step 728.

The test pad is implanted in step 740. A test pad is implanted in step 742 by forming a mask, and in step 744, the mask is masked and etched as needed. In step 746, the pad regions are implanted with dopants to form a test pad. An additional wafer process is performed in step 760. In an embodiment, this additional process is, for example, annealing, dopant activation, or other semiconductor device fabrication process. The test pads can be tested for contact or non-contact type in step 762 to measure dopant activation, strain, or to measure characteristics of the semiconductor region using other test procedures. The additional wafer processing steps in step 760 and the additional pad testing steps in step 762 can be performed sequentially. The wafer can be cut or split in step 764.

Figure 8 is a block diagram showing any embodiment of a system 800 for testing wafers having test keys. A computer 802, processor or other controller issues a signal to the probe to move the probe 806 to contact the wafer 100. The computer 802 can have instructions to control a particular probe or set of probes to test a crystal having a particular layout circle. The probe controller 804 can also control the alignment of the probe 806 with the wafer 100 by moving the probe 806 or the wafer 100 to bring the probe 806 into contact with a particular test key or test pad. A data receiver 808 can read data from the probe after the probe contacts the test button and transmit the data to the computer 802. The computer can receive the read data from the data receiver 808 and can generate one or more reports by comparing the data from a particular wafer and a predetermined or expected data set. For example, reading from a wafer can be compared to a set of acceptable tolerances, and if the reading is outside the acceptable tolerance range, a report or alert is generated.

Forming a wafer with a test pad in accordance with an embodiment such that testing of the semiconductor device or structure does not contaminate or interfere with die operation or subsequent processing. A plurality of test pads having different physical properties (eg, fin structures) may be formed in the test key series, or the test pads in the test key series may have different physical properties such as doping. The test key group can have multiple test key series, wherein different test key groups have different physical characteristics, such as epitaxial characteristics or layer patterns.

A method according to an embodiment includes forming a semiconductor device on a wafer having a substrate and forming a test key on the substrate and in a dicing line of the wafer, the test key having a plurality of test pads, At least one of the first test pads of the test pads has physical properties associated with a portion of the semiconductor device. At least one epitaxial region is formed in the substrate, and the test pads are formed from the at least one epitaxial region. The method further includes forming at least one shallow trench isolation structure in the substrate. Forming at least one test pad between the shallow trench isolation structures. Forming a second test pad of the test pads in the substrate, the second test pad having at least one physical property different from the first test pad. The first test pad has a first epitaxial property, and the second test pad has a second epitaxial property that is different from the first epitaxial property. First test pad and second The test pad includes a semiconductor compound that is different from the semiconductor compound of the substrate. The first test pad has a first doping characteristic, the second test pad has a second doping characteristic, and the second doping characteristic is different from the first doping characteristic.

According to an embodiment, forming a test key includes forming a plurality of STIs on a substrate of the wafer and a dicing line of the wafer, and forming a test key on the substrate of the wafer and the dicing line of the wafer. Forming the test key includes forming at least one test key group, having a plurality of test key series, each test key group having a plurality of test pads, each test key series having a first physical characteristic different from the at least one first test The first physical property of the other test key series of the key group.

In accordance with an embodiment, a wafer includes at least one scribe line defined on a substrate of the wafer, the at least one scribe lane separating the die regions, and the at least one test key series is located in at least all of the channels. The at least one test key series includes a plurality of test pads, and each test pad is separated from the other test pad by a shallow trench isolation structure. Each test pad in each test key series has at least one fin, and each test pad in the test key series has a different number of fins.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified, replaced and retouched without departing from the spirit and scope of the invention. . Further, the scope of the present invention is not limited to the processes, machines, manufacture, compositions, devices, methods and steps in the specific embodiments described in the specification, and any one of ordinary skill in the art may disclose the invention. The present disclosure understands the processes, machines, manufactures, compositions, devices, methods, and steps that are presently or in the future that can be used in the present invention as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein. in. Therefore, the protection model of the present invention It should be interpreted in a broader context or meaning.

100‧‧‧ wafer

104‧‧‧Test key

106‧‧‧ cutting line

108‧‧‧Test key series

110a-110n‧‧‧ test pad

Claims (15)

A method of fabricating a semiconductor structure, comprising: forming a semiconductor device on a wafer, wherein the wafer has a substrate; and forming a test key on the substrate of the wafer and the cutting line, comprising: forming a plurality of shallow a trench isolation structure on the substrate of the wafer and the dicing line; and forming a plurality of test pads including a semiconductor material, the test pads being formed on the substrate, and at least one of the shallow trench isolation structures Separating, at least one of the first test pads of the test pads has physical properties associated with a portion of the semiconductor device. The method of fabricating a semiconductor structure according to claim 1, wherein the forming the test key comprises forming at least one epitaxial region in the substrate, the test pads being formed by the at least one epitaxial region, and forming the test The bond further includes forming the test pads from a semiconductor material, the lattice of the semiconductor material not matching the material of the substrate. The method of fabricating the semiconductor structure of claim 1, further comprising forming a second test pad of the test pads, the at least one physical property of the second test pad being different from the first test pad. The method for fabricating a semiconductor structure according to claim 3, wherein the first test pad has a first epitaxial property, and the second test pad has a second epitaxial property, the first epitaxial property and The second epitaxial property is different. The method for fabricating a semiconductor structure according to claim 3, wherein the first test pad and the second test pad are formed of a semiconductor compound, The semiconductor compound is different from the semiconductor compound of the substrate. The method for fabricating a semiconductor structure according to claim 3, wherein the first test pad has a first doping characteristic, and the second test pad has a second doping characteristic, the first doping characteristic and The second doping characteristics are different. A method of forming a test structure, comprising: forming a plurality of shallow trench isolation structures on a substrate of a wafer and a dicing line of the wafer; and forming a test key on the substrate of the wafer and the wafer In the cutting line, forming the test key comprises: forming at least one test key group, having a plurality of test key series, each test key series having a plurality of test pads formed of a semiconductor material, in the at least one test key group Each test key series has a first physical characteristic that is different from the first physical characteristic of the other test key series. The method of forming a test structure according to claim 7, wherein the forming the at least one test key group comprises forming each test pad in each test key series having at least one fin, in a test key series Each test pad of some test pads has a different number of fins. The method of forming a test structure according to claim 7, wherein forming the at least one test key group comprises forming at least one fin in each test pad in each test key series, wherein each of the test key groups The test pad has the same first physical characteristic, wherein forming the at least one test key group includes forming a first test key group and a second test key group, the first test key group having a first physical characteristic, The second physical characteristic is different from the second test key group. The method of forming a test structure according to claim 9, wherein the first physical property is a doping degree, and the second physical property is an epitaxial property, wherein forming the first test key group includes The crystal layer forms each test pad, and each test pad is separated by a shallow trench isolation structure. A wafer comprising: at least one scribe line defined on a substrate of the wafer, the at least one scribe line separating the die regions; and at least one test key series in the at least one scribe line, the at least one test button The series includes: a plurality of test pads, each test pad of the test pads is separated from another test pad by a shallow trench isolation structure; wherein each test pad of each of the at least one test key series has at least one fin, a test Each test pad of the test pads in the key series has a different number of fins. The wafer of claim 11, wherein each test pad in each test key series is formed from a compound different from the compound of the substrate. The wafer of claim 11, further comprising at least one semiconductor device, wherein in a die region, a first test pad of the test pads of each test key series has a physical characteristic, and the at least One of the semiconductor devices is structurally related. The wafer of claim 11, wherein the wafer has at least two test key series, and the test pads of one of the test key series have a doping profile different from at least one other test key series. Doping of test pads profile. The wafer of claim 11, wherein the wafer has at least two test key series, and one of the test key series has an epitaxial property different from at least one other test key series. The epitaxial properties of the test pads.