KR101696453B1 - Liquid Crystal Display - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of displaying a usage time.

The liquid crystal display device includes a liquid crystal display panel in which a plurality of data lines and gate lines are crossed, and a plurality of liquid crystal cells are formed in each of the crossing regions; Counts an input synchronizing signal, generates OSD data for actual use time of the liquid crystal display panel on the basis of the count value, generates input OSD data in the corresponding position in response to a display control signal input from the user, A display data processing circuit replacing the display data processing circuit; And a panel driving circuit for driving the data lines and the gate lines so that the OSD data is displayed on the liquid crystal display panel as a usage time indicating image.

Description

[0001] Liquid crystal display [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of displaying a usage time.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix form, and a driving circuit for driving the liquid crystal display panel.

The liquid crystal display panel includes a thin film transistor (TFT) for driving the liquid crystal cell Clc at the intersection of the gate line GL and the data line DL and the intersection of the gate line GL and the data line GL, Thin Film Transistor (hereinafter referred to as "TFT"). A storage capacitor Cst for holding the voltage of the liquid crystal cell Clc is formed in the liquid crystal display panel. The liquid crystal cell Clc includes a pixel electrode, a common electrode, and a liquid crystal layer. An electric field is applied to the liquid crystal layer of the liquid crystal cells Clc by the data voltage applied to the pixel electrode and the common voltage Vcom applied to the common electrode. And the amount of light passing through the liquid crystal layer is controlled by this electric field, thereby realizing an image.

Like all electronic products, these liquid crystal displays also have quality assurance deadlines at the time of shipment. However, the usual quality assurance is determined by a one-year or two-year fixed-term basis based on the date of manufacture, not actual use time. As a result, there is a great risk of friction between the consumer and the manufacturer with respect to the product guarantee time in the absence of objective information on the use time of the liquid crystal display device.

Accordingly, it is an object of the present invention to provide a liquid crystal display device capable of displaying actual use time.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal display panel in which a plurality of data lines and gate lines are crossed and a plurality of liquid crystal cells are formed in each of the crossing regions; Counts an input synchronizing signal, generates OSD data for actual use time of the liquid crystal display panel on the basis of the count value, generates input OSD data in the corresponding position in response to a display control signal input from the user, A display data processing circuit replacing the display data processing circuit; And a panel driving circuit for driving the data lines and the gate lines so that the OSD data is displayed on the liquid crystal display panel as a usage time indicating image.

The input sync signal is a vertical sync signal input through the system board.

The liquid crystal display further comprises a timing controller for controlling an operation timing of the panel driving circuit; The display data processing circuit is embedded in the timing controller.

Wherein the display data processing circuit includes: a synchronization signal counting unit for counting the vertical synchronization signal to generate count information; A storage unit for continuously storing and updating the count information from the synchronous signal counting unit in units of predetermined coefficients; An OSD generating unit for generating the OSD data corresponding to the updated count information; And replacing the input image data with the OSD data corresponding to a first position at which the OSD data is to be displayed and replacing the replaced OSD data with input image data to be displayed at a second position other than the first position, And a data processing unit for supplying the data to the panel drive circuit.

The usage time indication image is displayed in a bar form and the OSD data is generated in such a direction that the bar usage time indication image becomes longer and longer as the updated count information is increased.

Wherein the display data processing circuit includes: a synchronization signal counting unit for counting the vertical synchronization signal to generate count information; A frequency determination unit for determining an input frame frequency; A storage unit for calculating actual use time information with reference to count information from the synchronous signal counting unit and frequency information from the frequency determining unit, and continuously storing and updating the time information; An OSD generation unit for generating the OSD data corresponding to the updated time information; And replacing the input image data with the OSD data corresponding to a first position at which the OSD data is to be displayed and replacing the replaced OSD data with input image data to be displayed at a second position other than the first position, And a data processing unit for supplying the data to the panel drive circuit.

Wherein the frequency determining unit determines the input frame frequency using the number of reference clocks included in adjacent vertical synchronizing signals; The number of reference clocks is predetermined based on a specific frame frequency.

The use time indication image is displayed in numeric and character form.

The data processing unit supplies the input image data to the panel driving circuit as it is when the display control signal is not inputted from the user.

The liquid crystal display device according to the present invention can display the usage time of the liquid crystal module on the screen when a display control signal is inputted from a user, thereby enabling quality assurance with practical use time instead of periodic guarantee. Based on this, the liquid crystal display device according to the present invention can greatly contribute to the improvement of the reliability with respect to the guarantee time of the liquid crystal module. Also, when the liquid crystal module is repaired, the set maker can easily grasp the remaining service life of the component.

Further, since the liquid crystal display device according to the present invention incorporates the display data processing circuit for displaying the usage time of the liquid crystal module on the screen in the liquid crystal module, as compared with the case where the display data processing circuit is mounted on the system board, Can be accurately reflected in the actual use time up to the use time in the test step. When the display data processing circuit is built in the liquid crystal module, it is advantageous in terms of circuit simplification and manufacturing cost as compared with mounting the display data processing circuit on the system board.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 2 to 7. FIG.

2 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

2, a liquid crystal display according to the present invention includes a timing controller 11, a data driving circuit 12, a gate driving circuit 13, a module power source 15, a liquid crystal display panel 16, (17), and a system board (14). The data driving circuit 12 and the gate driving circuit 13 constitute a panel driving circuit.

The timing controller 11 includes a display data processing circuit 111 and a control signal generating circuit (not shown).

The display data processing circuit 111 counts the synchronization signal input from the system board 14 and generates OSD (On Screen Display) data (DATA_OSD) for the actual use time based on the count value, (DATA_RGB) with the OSD data (DATA_OSD) at the corresponding position in response to the display control signal (DCS) from the user input via the input / output interface (14). The display data processing circuit 111 supplies the OSD data (DATA_OSD) together with the image data (DATA_RGB) to the data driving circuit 12 in a mini-LVDS (Low Voltage Differential Signaling) interface standard. The display data processing circuit 111 generates and processes the OSD data (DATA_OSD) itself so that the actual usage time for the liquid crystal module can be displayed in various forms. The display data processing circuit 111 will be described later in detail with reference to FIG. 3 to FIG.

The control signal generation circuit receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock signal CLK from the system board 14. The control signal generating circuit includes a data control signal SDC for controlling the operation timing of the data driving circuit 12 using the timing signals Vsync, Hsync, DE and CLK and a data control signal SDC for controlling the operation timing of the gate driving circuit 13 A gate control signal GDC for controlling the gate control signal GDC. The control signal generating circuit generates a gate control signal GDC (i) so that data input at a frame frequency of 60 Hz can be displayed in the pixel array of the liquid crystal display panel 16 at a frame frequency of 60 x i (i is a positive integer of 2 or more) And the data control signal SDC can be multiplied by 60 x i Hz.

The data control signal SDC includes a source start pulse SSP, a source sampling clock SSC, a source output enable SOE, a polarity control signal POL, . The source start pulse SSP controls the data sampling start timing of the data driving circuit 12. The source sampling clock SSC is a clock signal for controlling the sampling operation of data in the source drive ICs of the data driving circuit 12 on the basis of the rising or falling edge. The polarity control signal POL inverts the polarity of the data voltage output from the data driving circuit 12 in a period of N (N is a positive integer) horizontal period. The source output enable signal SOE controls the output timing of the data driving circuit. Each of the source drive ICs generates a charge share voltage or a common voltage Vcom in response to the pulse of the source output enable signal SOE when the polarity of the data voltage supplied to the data lines D1 to Dm is changed, To the data lines D1 to Dm and supplies the data voltages to the data lines during the row logic period of the source output enable signal SOE. The charge sharing voltage may be an average voltage of neighboring data lines to which data voltages of opposite polarities are supplied.

The gate control signal GDC includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like. The gate start pulse (GSP) controls the timing of the first gate pulse. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate drive circuit 13. [

The system board 14 is connected to a broadcast receiving circuit and an external video source interface circuit and supplies image data (DATA_RGB) input from the source circuit to a Low Voltage Differential Signaling (LVDS) interface or a Transmission Minimized Differential Signaling To the timing controller (11). The system board 14 transmits a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK to the timing controller 11. The system board 14 is provided with a graphics processing circuit such as a scaler for processing the resolution of image data (DATA_RGB) input from a broadcast receiving circuit or an external video source to the resolution of the liquid crystal display panel 16, And a power supply circuit for generating a voltage Vin to be supplied. The scaler transmits a display control signal DCS input from the user to the timing controller 11 through a user interface. The user interface may be implemented by a keyboard, a mouse, an OSD button, or the like.

The data driving circuit 12 includes a plurality of source drive ICs. Each of the source drive ICs samples and latches image data (DATA_RGB) and / or OSD data (DATA_OSD) input from the timing controller 11 in response to a data control signal SDC from the timing controller 11, System data. Each of the source drive ICs converts the data converted into the parallel data transmission scheme into an analog gamma compensation voltage using the positive / negative polarity gamma reference voltages V _GMAO1 to V _GMAO10 from the module power supply unit 15, Polarity analog video data voltage to be charged to the positive polarity / negative polarity. Each of the source drive ICs inverts the polarity of the positive / negative analog video data voltage under the control of the timing controller 11 and supplies the data voltage to the data lines D1 to Dm.

The gate drive circuit 13 includes a plurality of gate drive ICs. Each of the gate drive ICs includes a shift register for sequentially shifting the gate drive voltage in response to the gate control signal GDC from the timing controller 11 to sequentially supply gate pulses (or scan pulses) to the gate lines do.

The liquid crystal display panel 16 includes an upper glass substrate and a lower glass substrate opposed to each other with a liquid crystal layer interposed therebetween. The liquid crystal display panel 16 includes a pixel array for displaying image data (DATA_RGB) and / or OSD data (DATA_OSD). The pixel array includes TFTs formed at intersections of the data lines D1 to Dm and the gate lines G1 to Gn and pixel electrodes 1 connected to the TFTs. The pixel array includes a plurality of pixels each including an R liquid crystal cell, a G liquid crystal cell, and a B liquid crystal cell. The liquid crystal cell Clc is driven by the voltage difference between the pixel electrode 1 for charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied and the light emitted from the backlight unit 17 And displays the display image corresponding to the image data (DATA_RGB) and / or the use time indication image corresponding to the OSD data (DATA_OSD) by adjusting the transmission amount.

On the upper glass substrate of the liquid crystal display panel 16, a black matrix, a color filter, and a common electrode are formed. The common electrode 2 is formed on the upper glass substrate in the vertical field driving mode such as the TN mode and the VA mode and is formed on the lower glass substrate together with the pixel electrode 1 in the horizontal electric field driving method such as the IPS mode and the FFS mode .

On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 16, an alignment film for attaching a polarizing plate and setting a pre-tilt angle of the liquid crystal is formed.

The liquid crystal mode of the liquid crystal display panel 16 applicable to the present invention can be implemented not only in the TN mode, the VA mode, the IPS mode, and the FFS mode, but also in any liquid crystal mode. Further, the liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, a reflective liquid crystal display device, and the like. In the transmissive liquid crystal display device and the transflective liquid crystal display device, the backlight unit 17 is required. The backlight unit 17 may be implemented as a direct type backlight unit or an edge type backlight unit.

The module power supply unit 15 adjusts the voltage Vin input from the power supply circuit of the system board 14 to generate the driving voltages of the liquid crystal display panel 16. The driving voltage of the liquid crystal display panel 16 are a gate low voltage of less than the high-potential power supply voltage (Vdd) less than 8V, the logic power supply voltage (Vcc), 15V or more gate high voltage (V _GH) of about 3.3V, -3V ( and generates a V _GL), 7V ~ common voltage (Vcom), the positive / negative gamma reference voltages (V _GMA1 ~V _GMA10) between 8V and the like.

Fig. 3 shows an example of the display data processing circuit 111. Fig.

3, the display data processing circuit 111 includes a synchronization signal counting section 1111, a storage section 1112, an OSD generation section 1113, and a data processing section 1114. [

The sync signal counting unit 1111 counts a vertical sync signal Vsync input from the system board 14, including a counter, to generate count information CI.

The storage unit 1112 includes a memory and continuously stores and updates (increments) the count information CI from the synchronization signal counting unit 1111 in units of a predetermined coefficient. For example, when the predetermined coefficient unit is "100 ", the storage unit 1112 gradually increases the register value of the memory every time the input count information CI is incremented by" 100 ".

The OSD generating unit 1113 generates OSD data (DATA_OSD) for the actual use time of the liquid crystal module in response to the update count information (UCI) from the storage unit 1112. [ The OSD data (DATA_OSD) is variable depending on the update count information (UCI). For example, the OSD data (DATA_OSD) may be generated so that the use time indication bar of high gradation as shown in FIG. 4A is displayed for an increasingly long time in response to the increase of the update count information (UCI). The OSD data (DATA_OSD) can be generated so that the low-gradation auxiliary bar is additionally displayed on both sides of the usage time indicator bar as shown in FIG. 4B so that the use time indicator bar of FIG. 4A can be more easily identified.

The data processing unit 1114 processes the OSD data (DATA_OSD) from the OSD generating unit 1113 and the input image data (DATA_RGB) from the system board 14 differently depending on whether the display control signal DCS is input or not. When the display control signal DCS is input from the user, the data processing unit 1114 replaces the input image data (DATA_RGB) with the OSD data (DATA_OSD) corresponding to the first position at which the OSD data (DATA_OSD) is to be displayed. Then, the input OSD data (DATA_OSD) is supplied to the data driving circuit 12 together with the input image data (DATA_RGB) for the second position other than the first position. 4A and 4B, the use time indication image by the OSD data (DATA_OSD) is displayed at the first position of the liquid crystal display panel 16 and the use time indication image by the OSD data (DATA_OSD) is displayed at the second position of the liquid crystal display panel 16 DATA_RGB) is displayed. On the other hand, when the display control signal DCS is not inputted, the data processing unit 1114 supplies the input image data (DATA_RGB) directly to the data driving circuit 12. Thus, the use time indication image is not displayed on the liquid crystal display panel 16.

Fig. 5 shows another example of the display data processing circuit 111. Fig.

5, the display data processing circuit 111 includes a sync signal counting unit 1121, a frequency determining unit 1122, a storage unit 1123, an OSD generating unit 1124, and a data processing unit 1125 do.

The sync signal counting unit 1121 counts a vertical sync signal Vsync input from the system board 14, including a counter, to generate count information CI.

The frequency determining unit 1122 includes an oscillator for generating a reference clock OSC and a plurality of reference clocks OSC between the adjacent vertical synchronizing signals Vsync input from the system board 14 as shown in FIG. ) Is included in the input frame frequency (F). Here, the number of reference clocks OSC included in the vertical synchronization signal Vsync may be set to be predetermined based on a specific frame frequency. Accordingly, even if the interval between the vertical synchronization signals Vsync is changed and the number of the reference clocks OSC included therein changes, the frame frequency at this time can be easily determined. For example, when the frame frequency when the number of the reference clocks OSC included in the adjacent vertical synchronizing signals Vsync is 200 is set to 60 Hz, the reference clocks OSC included in the vertical synchronizing signals Vsync ) Is 100, the frame frequency can be determined to be 120 Hz.

The storage unit 1123 stores the actual use time information of the liquid crystal module, including the memory, with reference to the count information CI from the synchronizing signal counting unit 1121 and the frequency information F from the frequency determining unit 1122 And continuously stores and updates (increases) the time information. For example, the storage unit 1123 updates the register value of the memory so that the use time increases by one second every time the count information CI becomes " 60 " corresponding to the frequency information F of 60 Hz.

The OSD generation unit 1124 generates OSD data (DATA_OSD) corresponding to the update time information (UTI) from the storage unit 1123. The OSD data (DATA_OSD) is variable depending on the update time information (UTI). For example, the OSD data (DATA_OSD) can be generated so as to display the use time indication image as shown in Fig. 7 corresponding to the increase of the update time information (UTI).

The data processing unit 1125 processes the OSD data (DATA_OSD) from the OSD generation unit 1124 and the input image data (DATA_RGB) from the system board 14 differently depending on the presence or absence of the input of the display control signal DCS. When the display control signal DCS is input from the user, the data processing unit 1125 replaces the input image data (DATA_RGB) with the OSD data (DATA_OSD) corresponding to the first position at which the OSD data (DATA_OSD) is to be displayed. Then, the input OSD data (DATA_OSD) is supplied to the data driving circuit 12 together with the input image data (DATA_RGB) for the second position other than the first position. 7, the use time indication image in numeric and character form by the OSD data (DATA_OSD) is displayed at the first position of the liquid crystal display panel 16, and at the second position of the liquid crystal display panel 16, The display image by the data (DATA_RGB) is displayed. On the other hand, when the display control signal DCS is not input, the data processing unit 1125 supplies the input image data (DATA_RGB) directly to the data driving circuit 12. Thus, the use time indication image is not displayed on the liquid crystal display panel 16.

As described above, the liquid crystal display device according to the present invention can display the usage time of the liquid crystal module on the screen when a display control signal is inputted from a user, thereby enabling quality assurance with actual use time instead of periodical guarantee. Based on this, the liquid crystal display device according to the present invention can greatly contribute to the improvement of the reliability with respect to the guarantee time of the liquid crystal module. Also, it enables the set maker to easily grasp the remaining life of parts when maintenance and repair of the liquid crystal module is performed.

Further, since the liquid crystal display device according to the present invention incorporates the display data processing circuit for displaying the usage time of the liquid crystal module on the screen in the liquid crystal module, as compared with the case where the display data processing circuit is mounted on the system board, Can be accurately reflected in the actual use time up to the use time in the test step. When the display data processing circuit is built in the liquid crystal module, it is advantageous in terms of circuit simplification and manufacturing cost as compared with mounting the display data processing circuit on the system board.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a circuit diagram showing a pixel equivalently in a liquid crystal display device;

2 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

3 is a block diagram showing an example of a display data processing circuit;

FIGS. 4A and 4B are views showing an image implemented by data processed in FIG. 3; FIG.

5 is a block diagram showing another example of the display data processing circuit;

FIG. 6 is a waveform diagram for explaining a principle of determining an input frame frequency in the frequency determination unit of FIG. 5;

FIG. 7 is a view showing an image implemented by data processed in FIG. 5; FIG.

Description of the Related Art

11: timing controller 12: data driving circuit

13: gate drive circuit 14: system board

15: module power supply unit 16: liquid crystal display panel

17: backlight unit 111: display data processing circuit

Claims (9)

A liquid crystal display panel in which a plurality of data lines and gate lines are crossed, a plurality of liquid crystal cells are formed in each of the crossing areas, and OSD (On Screen Display) data for input image data and actual usage time are displayed; The OSD control unit counts the vertical synchronization signal input through the system board and generates the OSD data of the liquid crystal display panel on the basis of the count value, A display data processing circuit for replacing the input image data corresponding to the position with the OSD data; Wherein the OSD data is displayed at a first position of the liquid crystal display panel as a use time indication image and the input image data is displayed at a second position other than the first position of the liquid crystal display panel, A panel driving circuit for driving the plurality of pixels; And And a timing controller for controlling the operation timing of the panel driving circuit. delete The method according to claim 1, Wherein the display data processing circuit is incorporated in the timing controller. The method according to claim 1, Wherein the display data processing circuit comprises: A synchronization signal counting unit for counting the vertical synchronization signal to generate count information; A storage unit for continuously storing and updating count information from the synchronous signal counting unit in units of predetermined coefficients; An OSD generating unit for generating the OSD data corresponding to the updated count information; And The OSD data is replaced with the OSD data in correspondence with the first position at which the OSD data is to be displayed and the replaced OSD data together with the input image data to be displayed at the second position other than the first position, And a data processor for supplying the data to the driving circuit. 5. The method of claim 4, Wherein the use time indication image is displayed in a bar form, Wherein the OSD data is generated in such a direction that the bar-shaped usage time indication image becomes longer and longer as the updated count information is increased. The method according to claim 1, Wherein the display data processing circuit comprises: A synchronization signal counting unit for counting the vertical synchronization signal to generate count information; A frequency determination unit for determining an input frame frequency; A storage unit for calculating actual use time information with reference to count information from the synchronous signal counting unit and frequency information from the frequency determining unit, and continuously storing and updating the time information; An OSD generation unit for generating the OSD data corresponding to the updated time information; And The OSD data is replaced with the OSD data in correspondence with the first position at which the OSD data is to be displayed and the replaced OSD data together with the input image data to be displayed at the second position other than the first position, And a data processor for supplying the data to the driving circuit. The method according to claim 6, Wherein the frequency determining unit determines the input frame frequency using the number of reference clocks included in adjacent vertical synchronizing signals; Wherein the number of reference clocks is predetermined based on a specific frame frequency. The method according to claim 6, Wherein the usage time indicating image is displayed in numeric and character form. The method according to claim 4 or 6, Wherein the data processing unit supplies the input image data to the panel drive circuit as it is when the display control signal is not input from the user.

Images