KR101684149B1 - Method for extracting accurate mobility by using conductive length factor based on effective inversion charges of metal-oxide-semiconductor transistor and apparatus thereof - Google Patents

Method for extracting accurate mobility by using conductive length factor based on effective inversion charges of metal-oxide-semiconductor transistor and apparatus thereof Download PDF

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KR101684149B1
KR101684149B1 KR1020150099657A KR20150099657A KR101684149B1 KR 101684149 B1 KR101684149 B1 KR 101684149B1 KR 1020150099657 A KR1020150099657 A KR 1020150099657A KR 20150099657 A KR20150099657 A KR 20150099657A KR 101684149 B1 KR101684149 B1 KR 101684149B1
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capacitance
transistor
channel
intrinsic
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최양규
배학열
김충기
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한국과학기술원
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
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    • G01R31/2637—Circuits therefor for testing other individual devices

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Abstract

The present invention relates to a method for extracting accurate intrinsic mobility of a metal-oxide-semiconductor (MOS) transistor having a floating substrate structure. The method for extracting the accurate intrinsic mobility of the MOS transistor having the floating substrate structure comprises: a step of measuring capacitance of the transistor depending on gate voltage of the transistor including a gate area, a source area, and a drain area; a step of obtaining a coefficient of an inverse charge layer in a channel area according to the gate voltage of the transistor by using the measured capacitance of the transistor; a step of calculating an intrinsic channel length, in which capacitance is formed in the channel area between the source area and the drain area depending on channel conductivity generated by the gate voltage, in the channel area based on the obtained coefficient of the inverse charge layer; and a step of extracting the intrinsic mobility by using the calculated intrinsic channel length.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for correcting a length of an inversion charge layer depending on a gate voltage in a MOS transistor having a floating substrate structure to accurately extract an intrinsic mobility. OXIDE-SEMICONDUCTOR TRANSISTOR AND APPARATUS THEREOF}

The present invention relates to a device for extracting accurate intrinsic mobility from a MOS (Metal-Oxide-Semi conductor) -based three-terminal (gate region, source region and drain region) transistor having a floating substrate structure, Specifically, in the MOS transistor of the floating substrate structure in which a voltage can not be applied to the substrate, the length of the reverse charge layer depending on the gate voltage is corrected to extract the intrinsic mobility.

Mobility in a MOS transistor using a silicon substrate is one of the important indexes for determining semiconductor device characteristics. In particular, if the substrate is made of silicon-germanium (SiGe), the hole mobility of the transistor can be improved.

In order to analyze the performance of such a transistor, the conventional mobility extraction technique in extracting the mobility is performed by measuring the split CV (split CV)

Figure 112015067932816-pat00001
And extracts the mobility by performing normalization on the calculated area based on the metallurgical channel length and the metallurgical channel width.

However, in the conventional mobility extracting technique, the physical channel length based on the normalization reflects only the physical total area regardless of the gate voltage, so that the extracted mobility is inaccurate.

Thus, in this specification, a technology for accurately extracting the mobility by considering the area of the inversion charge layer in accordance with the gate voltage in the channel region between the source region and the drain region of the transistor is proposed.

Embodiments of the present invention provide a method and apparatus for extracting the intrinsic mobility by considering the area of the inverse charge layer according to the gate voltage in the channel region between the source region and the drain region of the transistor.

Specifically, the embodiments of the present invention acquire the coefficients of the inverse charge layer according to the gate voltage in the channel region between the source region and the drain region of the transistor, and then calculate the intrinsic channel length based on the coefficients of the obtained inverse charge layer Thereby extracting the intrinsic mobility using the calculated intrinsic channel length.

The method for extracting the intrinsic mobility of a metal-oxide-semiconductor (MOS) transistor having a floating substrate structure according to an embodiment of the present invention includes the steps of: Measuring a capacitance; Obtaining a coefficient of an inversion charge layer in a channel region according to a gate voltage of the transistor using the capacitance of the transistor; The intrinsic channel length in the channel region based on the obtained coefficient of the inverse charge layer, the length in which the capacitance of the channel region between the source region and the drain region is formed according to the channel conductivity by the gate voltage ; And extracting the intrinsic mobility using the calculated intrinsic channel length.

The step of extracting the intrinsic mobility may include extracting the intrinsic mobility using the calculated intrinsic channel length instead of using the physical channel length between the source region and the drain region in the channel region .

Obtaining the coefficients of the inverse charge layer may include obtaining coefficients of the inverse charge layer using parameters related to the physical structure of the transistor.

Extracting the intrinsic mobility may further include extracting the intrinsic mobility using a further parameter associated with the physical structure of the transistor.

Wherein calculating the intrinsic channel length further comprises calculating an amount of total reversed charge in the channel region based on the intrinsic channel length, wherein extracting the intrinsic mobility comprises using the calculated total amount of inverted charge And extracting the intrinsic mobility.

Wherein obtaining the coefficient of the inverse charge layer comprises removing an overlap capacitance between the gate region and the source region and an overlap capacitance between the gate region and the drain region from a capacitance of the transistor to obtain a coefficient of the inverse charge layer Lt; / RTI >

Wherein measuring the capacitance of the transistor comprises determining an inverse charge capacitance in the channel region, an overlap capacitance between the gate region and the source region, an overlap capacitance between the gate region and the drain region, And measuring the capacitance formed by the layer.

Wherein obtaining the coefficients of the inverse charge layer comprises determining an inverse charge capacitance in the channel region, an overlap capacitance between the gate region and the source region, an overlap capacitance between the gate region and the drain region, And obtaining a coefficient of the inverse charge layer using a capacitance formed by the inversion charge layer.

Wherein measuring the capacitance of the transistor comprises: applying a signal voltage to a gate region included in the transistor; And connecting the source region and the drain region to use as a ground electrode.

An apparatus for extracting an intrinsic mobility of a metal-oxide-semiconductor (MOS) transistor having a floating substrate structure according to an embodiment of the present invention includes a gate region, a source region, and a drain region, A capacitance measuring unit for measuring a capacitance; An inverse charge layer coefficient obtaining unit that obtains a coefficient of an inversion charge layer in a channel region according to a gate voltage of the transistor using the capacitance of the measured transistor; The intrinsic channel length in the channel region based on the obtained coefficient of the inverse charge layer, the length in which the capacitance of the channel region between the source region and the drain region is formed according to the channel conductivity by the gate voltage A true channel length calculation unit; And an intrinsic mobility extractor for extracting intrinsic mobility using the calculated intrinsic channel length.

The intrinsic mobility extractor may extract the intrinsic mobility using the calculated intrinsic channel length instead of using the physical channel length between the source region and the drain region in the channel region.

The inverse charge layer coefficient obtaining unit may obtain a coefficient of the inverse charge layer using parameters related to the physical structure of the transistor.

The intrinsic mobility extractor may further extract the intrinsic mobility using parameters related to the physical structure of the transistor.

Embodiments of the present invention can provide a method and apparatus for extracting the intrinsic mobility by considering the area of the inverse charge layer according to the gate voltage in the channel region between the source region and the drain region of the transistor.

Specifically, the embodiments of the present invention acquire the coefficients of the inverse charge layer according to the gate voltage in the channel region between the source region and the drain region of the transistor, and then calculate the intrinsic channel length based on the coefficients of the obtained inverse charge layer A method and an apparatus for extracting the intrinsic mobility using the calculated intrinsic channel length can be provided.

Therefore, the embodiments of the present invention can accurately extract the intrinsic mobility by considering the area of the inversion charge layer in accordance with the gate voltage in the channel region between the source region and the drain region of the transistor.

1 illustrates a MOS transistor according to an embodiment of the present invention.
2 is a graph illustrating the capacitance measured in a MOS transistor according to an embodiment of the present invention.
3A to 3C are diagrams illustrating a capacitance model considering an inversion charge layer in a MOS transistor according to an embodiment of the present invention.
4 is a graph showing the intrinsic channel length considering the inverse charge layer coefficient according to gate voltage in a MOS transistor according to an embodiment of the present invention.
5 is a graph showing the intrinsic mobility extracted by the method according to an embodiment of the present invention.
6 is a flowchart illustrating an intrinsic mobility extracting method according to an embodiment of the present invention.
FIG. 7 is a block diagram showing an apparatus for extracting intrinsic mobility according to an embodiment of the present invention. Referring to FIG.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to or limited by the embodiments. In addition, the same reference numerals shown in the drawings denote the same members.

Also, terminologies used herein are terms used to properly represent preferred embodiments of the present invention, which may vary depending on the user, intent of the operator, or custom in the field to which the present invention belongs. Therefore, the definitions of these terms should be based on the contents throughout this specification.

1 illustrates a MOS transistor according to an embodiment of the present invention.

Referring to FIG. 1, a MOS transistor according to an embodiment of the present invention includes a floating substrate 110, a drain region 120, a source region 130, and a gate region 140. Hereinafter, the MOS transistor will be described as a floating-body Si / SiGe MOSFET. However, the present invention is not limited thereto, and the MOS transistor may be a three-terminal (drain region 120, (E.g., gate region 130 and gate region 140).

The floating substrate 110 may be formed as a bulk substrate with a preset thickness. For example, the floating substrate 110 may be formed of silicon / silicon germanium (Si / SiGe). At this time, in the floating substrate 110,

Figure 112015067932816-pat00002
Can be formed. Such a capacitance
Figure 112015067932816-pat00003
Can be measured using the physical structure of the floating substrate 110.

The gate region 140 is formed on the stacked gate insulating layer 150 and 160 disposed between the drain region 120 and the source region 130 to have a predetermined length

Figure 112015067932816-pat00004
) And constant width (
Figure 112015067932816-pat00005
.

Here, the laminated gate insulating layers 150 and 160 are layers for electrically separating the gate region 140, the drain region 120, and the source region 130,

Figure 112015067932816-pat00006
,
Figure 112015067932816-pat00007
Lt; RTI ID = 0.0 > (
Figure 112015067932816-pat00008
,
Figure 112015067932816-pat00009
). Therefore, in the stacked gate insulating layers 150 and 160,
Figure 112015067932816-pat00010
Can be formed. Such a capacitance
Figure 112015067932816-pat00011
May be measured using the physical structure of the laminated gate insulating layer 150, For example, the capacitance formed by the stacked gate insulating layers 150 and 160
Figure 112015067932816-pat00012
The dielectric constant of the material forming the laminated gate insulating layers 150 and 160
Figure 112015067932816-pat00013
,
Figure 112015067932816-pat00014
) And thickness
Figure 112015067932816-pat00015
,
Figure 112015067932816-pat00016
). ≪ / RTI > More specifically, for example, the capacitance formed by the laminated gate insulating layers 150 and 160
Figure 112015067932816-pat00017
The dielectric constant of the material forming the laminated gate insulating layers 150 and 160
Figure 112015067932816-pat00018
,
Figure 112015067932816-pat00019
) And thickness
Figure 112015067932816-pat00020
,
Figure 112015067932816-pat00021
Quot;
Figure 112015067932816-pat00022
And
Figure 112015067932816-pat00023
Lt; / RTI >

&Quot; (1) "

Figure 112015067932816-pat00024

In this case, the gate region 140 may overlap with the drain region 120 and the source region 130, respectively (the stacked gate insulating layers 150 and 160, in which the gate region 140 is formed, 120 and the source region 130, respectively). For example, the gate region 140 includes a drain region 120 and a source region 130,

Figure 112015067932816-pat00025
The gate region 140 may be formed to overlap with the drain region 120,
Figure 112015067932816-pat00026
The source region 130,
Figure 112015067932816-pat00027
As shown in FIG.

The drain region 120 and the source region 130 are formed on the floating substrate 110 at a predetermined distance

Figure 112015067932816-pat00028
) To a predetermined width (
Figure 112015067932816-pat00029
. That is, the drain region 120 and the source region 130 have a metallurgical channel length
Figure 112015067932816-pat00030
As shown in FIG.

The intrinsic mobility of the floating substrate MOS transistor according to an embodiment of the present invention is extracted in consideration of the inversion charge layer in the channel region (the region between the drain region 120 and the source region 130) which varies depending on the gate voltage . A detailed description thereof will be given below.

2 is a graph illustrating the capacitance measured in a MOS transistor according to an embodiment of the present invention.

3A to 3C are diagrams illustrating a capacitance model considering an inversion charge layer in a MOS transistor according to an embodiment of the present invention.

4 is a graph showing the intrinsic channel length considering the inverse charge layer coefficient according to gate voltage in a MOS transistor according to an embodiment of the present invention.

5 is a graph showing the intrinsic mobility extracted by the method according to an embodiment of the present invention.

Specifically, FIG. 2 shows the capacitance between the gate region and the source region / drain region included in the MOS transistor

Figure 112015067932816-pat00031
) And the capacitance between the gate region and the commonly coupled source / drain / floating substrate region (
Figure 112015067932816-pat00032
FIG.

That is, the graph of FIG. 2 shows the capacitance

Figure 112015067932816-pat00033
). The capacitance of a transistor can be measured by applying a signal voltage to a gate region included in a transistor, and connecting a source region and a drain region to be used as a ground electrode. The capacitance of the measured transistor, as shown,
Figure 112015067932816-pat00034
) When this transistor is off
Figure 112015067932816-pat00035
In a section smaller than the voltage, the minimum value of the total capacitance (
Figure 112015067932816-pat00036
), The value in the interval of the capacitance depending on the measured gate voltage may be different depending on the configuration for measuring the capacitance.

Therefore, as can be seen from the capacitance model considering the inversion charge layer according to the gate voltage shown in FIG. 3A, the gate voltage

Figure 112015067932816-pat00037
Lt; RTI ID = 0.0 > (
Figure 112015067932816-pat00038
) Cut-off state that is less than the voltage
Figure 112015067932816-pat00039
) Does not affect the total capacitance, and therefore, the inverse charge layer coefficient in the channel region (
Figure 112015067932816-pat00040
) Is close to zero. Thus, the capacitance measured in the transistor is the sum of the capacitance of the overlapping portion between the gate region and the source region and the overlapping portion between the gate region and the drain region, as shown in Equation 2. < EMI ID =
Figure 112015067932816-pat00041
Lt; / RTI >

&Quot; (2) "

Figure 112015067932816-pat00042

In Equation 2,

Figure 112015067932816-pat00043
Quot; refers to the overlap capacitance between the gate region and the source region,
Figure 112015067932816-pat00044
Quot; implies an overlap capacitance between the gate region and the drain region.

On the other hand, it can be seen that the maximum capacitance measured in the transistor is the same regardless of the arrangement for measuring capacitance through FIG. 2, as shown in FIG. 3C,

Figure 112015067932816-pat00045
Lt; RTI ID = 0.0 > (
Figure 112015067932816-pat00046
) ≪ / RTI >
Figure 112015067932816-pat00047
), The channel region between the source region and the drain region is changed into a conductive state by a strong inversion mode, which affects the entire capacitance regardless of the measurement arrangement of the capacitance. Thus, when the gate voltage is much greater than the threshold voltage, the inverse charge layer coefficient (
Figure 112015067932816-pat00048
) Is close to 1.

Also, the gate voltage (

Figure 112015067932816-pat00049
Lt; RTI ID = 0.0 > (
Figure 112015067932816-pat00050
) Is greater than
Figure 112015067932816-pat00051
), The channel region becomes partially conductive, which can model the channel region as a capacitance, as shown in FIG. 3B. Therefore, the gate voltage (
Figure 112015067932816-pat00052
Lt; RTI ID = 0.0 > (
Figure 112015067932816-pat00053
), The capacitance of the transistor measured is determined by the capacitance formed near the source region and the drain region.

That is, the gate voltage

Figure 112015067932816-pat00054
Lt; RTI ID = 0.0 > (
Figure 112015067932816-pat00055
), The conductivity of the channel region increases as the gate voltage increases and the inverse underlayer coefficient in the channel region (
Figure 112015067932816-pat00056
) Is the inverse charge capacitance in the channel region of the total capacitance (
Figure 112015067932816-pat00057
). ≪ / RTI >

Hereinafter, the inverse charge capacitance (

Figure 112015067932816-pat00058
) Is set to be a capacitance formed on the source region side of the channel region
Figure 112015067932816-pat00059
And the capacitance formed on the drain region side
Figure 112015067932816-pat00060
And the source region and the drain region in the channel region have a symmetrical structure. Therefore, the length of the channel region where the capacitance is formed on the source region side (
Figure 112015067932816-pat00061
) And the length in which the capacitance is formed on the drain region side
Figure 112015067932816-pat00062
) Are the same.

That is, the intrinsic channel length (the length of the channel region where the capacitance is formed

Figure 112015067932816-pat00063
) Is such that when the gate voltage is much larger than the threshold voltage, a capacitance is formed across the channel region, so that the intrinsic channel length is the physical length between the source region and the drain region
Figure 112015067932816-pat00064
).

Therefore, the capacitance of the measured transistor (

Figure 112015067932816-pat00065
) Is the inverse charge capacitance (
Figure 112015067932816-pat00066
) And the overlap capacitance (
Figure 112015067932816-pat00067
), And the gate voltage (
Figure 112015067932816-pat00068
Lt; RTI ID = 0.0 > (
Figure 112015067932816-pat00069
) Is greater than
Figure 112015067932816-pat00070
), The inverse charge layer coefficient in the channel region
Figure 112015067932816-pat00071
) Can be expressed by Equation (3).

&Quot; (3) "

Figure 112015067932816-pat00072

In Equation (3)

Figure 112015067932816-pat00073
Quot; refers to the inverse charge capacitance in the channel region,
Figure 112015067932816-pat00074
Implies an overlap capacitance which is the sum of the overlap capacitance between the gate region and the source region and the overlap capacitance between the gate region and the drain region,
Figure 112015067932816-pat00075
Quot; refers to a capacitance formed by the laminated gate insulating layer.

Thus, the inverse charge layer coefficient in the channel region is determined by the capacitance of the measured transistor (the overlap capacitance between the gate and source regions, the overlap capacitance between the gate and drain regions, the inverse charge capacitance in the channel region, The capacitance formed by the current source). For example, the inverse charge layer coefficient in the channel region may vary from the capacitance of the transistor (the inverse charge capacitance in the channel region and the capacitance formed by the stacked gate insulating layer) to the overlap capacitance between the gate region and the source region and the gate capacitance between the gate and drain regions Lt; RTI ID = 0.0 > capacitance < / RTI >

At this time, the capacitance formed by the laminated gate insulating layer is expressed by the ratio of the dielectric constant and the thickness of the material forming the laminated gate insulating layer (

Figure 112015067932816-pat00076
), The inverse charge layer coefficients in the channel region can be obtained using parameters related to the physical structure of the transistor, as well as the capacitance of the transistor being measured.

The intrinsic channel length in the channel region according to the gate voltage shown in FIG. 4

Figure 112015067932816-pat00077
) Can be calculated as shown in Equation (4) based on the coefficients of the obtained inverse charge layer.

&Quot; (4) "

Figure 112015067932816-pat00078

In Equation (4)

Figure 112015067932816-pat00079
Is the inverse charge layer coefficient in the channel region,
Figure 112015067932816-pat00080
Quot; refers to the physical channel length between the source region and the drain region.

Further, the total amount of inversion charge in the channel region according to the gate voltage

Figure 112015067932816-pat00081
Can be calculated as shown in Equation (5) based on the intrinsic channel length.

Equation (5)

Figure 112015067932816-pat00082

In Equation (5)

Figure 112015067932816-pat00083
Denotes the intrinsic channel length in the channel region according to the gate voltage,
Figure 112015067932816-pat00084
Quot; means the width of the drain region or the source region,
Figure 112015067932816-pat00085
Quot; refers to the capacitance between the gate region and the source region / drain region.

Therefore, the total amount of the inverted charge according to an embodiment of the present invention can be calculated according to the area of the inversion charge layer calculated as the product of the width of the drain region or the source region and the intrinsic channel length. That is, the total amount of the inverse charge can be calculated by adding the inverse charge amount per unit area according to the gate voltage to the measurement area over the threshold voltage.

Thus, as shown in Fig. 5,

Figure 112015067932816-pat00086
Can be extracted through Equation (6) using the calculated total amount of inverse charge.

&Quot; (6) "

Figure 112015067932816-pat00087

In Equation (6)

Figure 112015067932816-pat00088
Quot; means a certain length in which a laminated gate insulating layer or a gate region is formed,
Figure 112015067932816-pat00089
Quot; means the width of the drain region or the source region,
Figure 112015067932816-pat00090
Denotes a voltage applied to the drain region,
Figure 112015067932816-pat00091
Means the drain current according to the gate voltage,
Figure 112015067932816-pat00092
Means the total amount of charge in the channel region.

In addition,

Figure 112015067932816-pat00093
May be extracted as Equation (7) using the intrinsic channel length calculated from Equations (5) and (6).

&Quot; (7) "

Figure 112015067932816-pat00094

Therefore,

Figure 112015067932816-pat00095
May be extracted by further using parameters related to the physical structure of the transistor, such as the calculated total amount of inverted charge or the calculated intrinsic channel length, as well as the width of the drain region or the source region. That is,
Figure 112015067932816-pat00096
Can be extracted according to the area of the inversion charge layer calculated as the product of the width of the drain region or the source region and the intrinsic channel length.

The intrinsic mobility extracted through Equation (6) or (7) as described above is obtained by the other method shown in Fig. 5

Figure 112015067932816-pat00097
And it has a similar value to the mobility extracted by.

6 is a flowchart illustrating an intrinsic mobility extracting method according to an embodiment of the present invention.

Referring to FIG. 6, an apparatus for extracting intrinsic mobility according to an embodiment of the present invention measures a capacitance of a transistor according to a gate voltage of a transistor including a gate region, a source region, and a drain region (610).

For example, an intrinsic mobility extraction device may be implemented by means of an inverse charge capacitance in the channel region of a transistor, an overlap capacitance between the gate region and the source region, an overlap capacitance between the gate region and the drain region, The formed capacitance can be measured.

At this time, the intrinsic mobility extracting apparatus can measure the capacitance of the transistor according to the gate voltage by applying a signal voltage to the gate region included in the transistor and connecting the source region and the drain region as a ground electrode.

Then, the intrinsic mobility extraction apparatus obtains a coefficient of the inverse charge layer in the channel region according to the gate voltage of the transistor using the measured capacitance of the transistor (620).

For example, an intrinsic mobility extraction apparatus may use an inverse charge capacitance in a channel region, an overlap capacitance between a gate region and a source region, an overlap capacitance between a gate region and a drain region, and a capacitance formed by the layered gate insulating layer The coefficient of the inverse charge layer can be obtained. More specifically, the intrinsic mobility extraction device can obtain the coefficient of the inverse charge layer by removing the overlap capacitance between the gate region and the source region and the gate region and the drain region from the capacitance of the transistor.

At this time, the intrinsic mobility extractor can obtain the coefficients of the inverse charge layer using parameters related to the physical structure of the transistor.

Then, the intrinsic mobility extracting apparatus forms a capacitance in the channel region between the source region and the drain region, according to the intrinsic channel length in the channel region - the channel conductivity by the gate voltage, based on the obtained coefficient of the inverse charge layer The length - is calculated 630.

The intrinsic mobility extractor then extracts the intrinsic mobility using the calculated intrinsic channel length (640). In other words, the intrinsic mobility extraction apparatus can extract the intrinsic mobility using the calculated intrinsic channel length instead of using the physical channel length between the source region and the drain region in the channel region.

At this time, the intrinsic mobility extracting apparatus can extract the intrinsic mobility by further using the parameters related to the physical structure of the transistor.

Here, in step 630, the intrinsic mobility extractor may calculate the total amount of reversed charges in the channel region based on the intrinsic channel length. Accordingly, in step 640, the intrinsic mobility extractor may extract the intrinsic mobility using the calculated total amount of the inverted charge.

FIG. 7 is a block diagram showing an apparatus for extracting intrinsic mobility according to an embodiment of the present invention. Referring to FIG.

7, the apparatus for extracting intrinsic mobility according to an embodiment of the present invention includes a capacitance measurement unit 710, an inverse charge layer coefficient acquisition unit 720, an intrinsic channel length calculation unit 730, (740).

The capacitance measuring unit 710 measures the capacitance of the transistor according to the gate voltage of the transistor including the gate region, the source region, and the drain region.

For example, the capacitance measuring unit 710 may be configured so that the intrinsic mobility extractor includes an inverting charge capacitance in the channel region of the transistor, an overlap capacitance between the gate region and the source region, an overlap capacitance between the gate region and the drain region, The capacitance formed by the laminated gate insulating layer can be measured.

At this time, the capacitance measuring unit 710 can measure the capacitance of the transistor according to the gate voltage by applying a signal voltage to the gate region included in the transistor, and connecting the source region and the drain region as a ground electrode.

The inverse charge layer coefficient obtaining unit 720 obtains the coefficient of the inverse charge layer in the channel region according to the gate voltage of the transistor using the capacitance of the measured transistor.

For example, the inverse charge layer coefficient obtaining unit 720 may calculate the inverse charge layer coefficient 720 by using the inverse charge capacitance in the channel region, the overlap capacitance between the gate region and the source region, the overlap capacitance between the gate region and the drain region, The coefficient of the inverse charge layer can be obtained by using the capacitance. More specifically, the inverse charge layer coefficient obtaining unit 720 obtains the coefficient of the inverse charge layer by removing the overlap capacitance between the gate region and the source region and the gate region and the drain region from the capacitance of the transistor .

At this time, the inverse charge layer coefficient obtaining unit 720 can obtain the coefficient of the inverse charge layer using parameters related to the physical structure of the transistor.

The intrinsic channel length calculation unit 730 calculates the capacitance of the channel region between the source region and the drain region according to the intrinsic channel length in the channel region and the channel conductivity due to the gate voltage based on the obtained coefficient of the inverse charge layer Calculate the length -.

The intrinsic mobility extractor 740 extracts the intrinsic mobility using the calculated intrinsic channel length. In other words, the intrinsic mobility extractor 740 can extract the intrinsic mobility using the calculated intrinsic channel length instead of using the physical channel length between the source region and the drain region in the channel region.

At this time, the intrinsic mobility extractor 740 can extract the intrinsic mobility using the parameters related to the physical structure of the transistor.

Herein, the intrinsic channel length calculation unit 730 can calculate the total amount of inverted charges in the channel region based on the intrinsic channel length. Accordingly, the intrinsic mobility extractor 740 may extract the intrinsic mobility using the calculated total amount of the inverted charges.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (13)

1. A method for extracting an intrinsic mobility of a metal-oxide-semiconductor (MOS) transistor having a floating substrate structure,
Measuring a capacitance of the transistor according to a gate voltage of the transistor including the gate region, the source region, and the drain region;
Obtaining a coefficient of an inversion charge layer in a channel region according to a gate voltage of the transistor using a capacitance of the transistor as measured by the following equation 1;
And a capacitance of a channel region between the source region and the drain region, according to the intrinsic channel length in the channel region - the channel conductivity by the gate voltage, The length of which is formed; And
Using the calculated intrinsic channel length, extracting the intrinsic mobility as shown in Equations (3) to (4) below
Lt; / RTI >
&Quot; (1) "
Figure 112016078453200-pat00107

&Quot; (2) "
Figure 112016078453200-pat00108

&Quot; (3) "
Figure 112016078453200-pat00109

&Quot; (4) "
Figure 112016078453200-pat00110

/ RTI >
In the above Equation 1,
Figure 112016078453200-pat00111
Denotes the coefficient of the inversion charge layer in the channel region,
Figure 112016078453200-pat00112
Denotes an inverse charge capacitance in the channel region,
Figure 112016078453200-pat00113
Means an overlap capacitance which is a sum of an overlap capacitance between the gate region and the source region and an overlap capacitance between the gate region and the drain region,
Figure 112016078453200-pat00114
Quot; refers to a capacitance formed by the laminated gate insulating layer included in the transistor,
In the above Equation 2,
Figure 112016078453200-pat00115
Denotes the intrinsic channel length in the channel region,
Figure 112016078453200-pat00116
Denotes an inverse charge layer coefficient in the channel region,
Figure 112016078453200-pat00117
Refers to the physical channel length between the source region and the drain region,
In Equation 3,
Figure 112016078453200-pat00118
Means the total amount of charge in the channel region,
Figure 112016078453200-pat00119
Denotes the intrinsic channel length in the channel region,
Figure 112016078453200-pat00120
Means a width of the drain region or the source region,
Figure 112016078453200-pat00121
Refers to the capacitance between the gate region and the source region / drain region,
Figure 112016078453200-pat00122
Quot; means the gate voltage,
In Equation (4) above,
Figure 112016078453200-pat00123
Refers to the intrinsic mobility,
Figure 112016078453200-pat00124
Means a certain length in which the laminated gate insulating layer or the gate region is formed,
Figure 112016078453200-pat00125
Means a width of the drain region or the source region,
Figure 112016078453200-pat00126
Denotes a voltage applied to the drain region,
Figure 112016078453200-pat00127
Means a drain current according to the gate voltage,
Figure 112016078453200-pat00128
Means a total amount of charge reversal in the channel region. The method according to claim 1,
The step of extracting the intrinsic mobility
Extracting the intrinsic mobility using the calculated intrinsic channel length instead of using a physical channel length between the source region and the drain region in the channel region, . The method according to claim 1,
The step of obtaining the coefficients of the inverse charge layer
A parameter related to the physical structure of the transistor affecting the capacitance formed by the laminated gate insulating layer, wherein the parameter comprises a ratio of the dielectric constant and thickness of the material forming the laminated gate insulating layer, Obtaining a coefficient of the charge layer
And extracting the intrinsic mobility of the MOS transistor. The method according to claim 1,
The step of extracting the intrinsic mobility
And a parameter related to a physical structure of the transistor, the parameter including an area of the inverse charge layer calculated as a product of a width of the drain region or the source region and an intrinsic channel length in the channel region, Extracting the intrinsic mobility
And extracting the intrinsic mobility of the MOS transistor. delete The method according to claim 1,
The step of obtaining the coefficients of the inverse charge layer
Removing an overlap capacitance between the gate region and the source region and an overlapping capacitance between the gate region and the drain region from the capacitance of the transistor to obtain a coefficient of the inverse charge layer, Way. The method according to claim 1,
The step of measuring the capacitance of the transistor
An inverse charge capacitance in the channel region, an overlap capacitance between the gate region and the source region, an overlap capacitance between the gate region and the drain region, and a capacitance formed by the stacked gate insulating layer included in the transistor step
And extracting the intrinsic mobility of the MOS transistor. 8. The method of claim 7,
The step of obtaining the coefficients of the inverse charge layer
An inversion charge capacitance in the channel region, an overlap capacitance between the gate region and the source region, an overlap capacitance between the gate region and the drain region, and a capacitance formed by the lamination gate insulating layer, ≪ / RTI >
And extracting the intrinsic mobility of the MOS transistor. The method according to claim 1,
The step of measuring the capacitance of the transistor
Applying a signal voltage to a gate region included in the transistor; And
Connecting the source region and the drain region to use as a ground electrode
And extracting the intrinsic mobility of the MOS transistor. 1. An apparatus for extracting intrinsic mobility of a MOS (Metal-Oxide-Semi conductor) transistor having a floating substrate structure,
A capacitance measuring unit for measuring a capacitance of the transistor in accordance with a gate voltage of a transistor including a gate region, a source region, and a drain region;
An inverse charge layer coefficient obtaining unit that obtains a coefficient of an inversion charge layer in a channel region according to a gate voltage of the transistor using a capacitance of the transistor as measured by Equation 1 below;
And a capacitance of a channel region between the source region and the drain region, according to the intrinsic channel length in the channel region - the channel conductivity by the gate voltage, A length of the channel formed by the channel length calculation unit; And
Using the calculated intrinsic channel length, an intrinsic mobility extracting unit for extracting intrinsic mobility as shown in the following Equations (3) to (4)
Lt; / RTI >
&Quot; (1) "
Figure 112016078453200-pat00129

&Quot; (2) "
Figure 112016078453200-pat00130

&Quot; (3) "
Figure 112016078453200-pat00131

&Quot; (4) "
Figure 112016078453200-pat00132

/ RTI >
In the above Equation 1,
Figure 112016078453200-pat00133
Denotes the coefficient of the inversion charge layer in the channel region,
Figure 112016078453200-pat00134
Denotes an inverse charge capacitance in the channel region,
Figure 112016078453200-pat00135
Means an overlap capacitance which is a sum of an overlap capacitance between the gate region and the source region and an overlap capacitance between the gate region and the drain region,
Figure 112016078453200-pat00136
Quot; refers to a capacitance formed by the laminated gate insulating layer included in the transistor,
In the above Equation 2,
Figure 112016078453200-pat00137
Denotes the intrinsic channel length in the channel region,
Figure 112016078453200-pat00138
Denotes an inverse charge layer coefficient in the channel region,
Figure 112016078453200-pat00139
Refers to the physical channel length between the source region and the drain region,
In Equation 3,
Figure 112016078453200-pat00140
Means the total amount of charge in the channel region,
Figure 112016078453200-pat00141
Denotes the intrinsic channel length in the channel region,
Figure 112016078453200-pat00142
Means a width of the drain region or the source region,
Figure 112016078453200-pat00143
Refers to the capacitance between the gate region and the source region / drain region,
Figure 112016078453200-pat00144
Quot; means the gate voltage,
In Equation (4) above,
Figure 112016078453200-pat00145
Refers to the intrinsic mobility,
Figure 112016078453200-pat00146
Means a certain length in which the laminated gate insulating layer or the gate region is formed,
Figure 112016078453200-pat00147
Means a width of the drain region or the source region,
Figure 112016078453200-pat00148
Denotes a voltage applied to the drain region,
Figure 112016078453200-pat00149
Means a drain current according to the gate voltage,
Figure 112016078453200-pat00150
Means an amount of total charge reversed in the channel region. 11. The method of claim 10,
The intrinsic mobility extractor
And extracts the intrinsic mobility using the calculated intrinsic channel length instead of using the physical channel length between the source region and the drain region in the channel region. 11. The method of claim 10,
The inverse charge layer coefficient obtaining unit
A parameter related to the physical structure of the transistor affecting the capacitance formed by the laminated gate insulating layer, wherein the parameter comprises a ratio of a dielectric constant and a thickness of a material forming the laminated gate insulating layer, And obtaining a coefficient of the layer. 11. The method of claim 10,
The intrinsic mobility extractor
And a parameter related to a physical structure of the transistor, the parameter including an area of the inverse charge layer calculated as a product of a width of the drain region or the source region and an intrinsic channel length in the channel region, An apparatus for extracting the intrinsic mobility of an MOS transistor.
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