JP5881037B2 - Method and apparatus for evaluating insulator / semiconductor interface - Google Patents

Description

  The present invention relates to an insulator / semiconductor interface evaluation technique, and more particularly to an insulating film / SiC semiconductor interface defect evaluation technique.

  The electronic properties of the insulating film / semiconductor interface (MIS interface, MOS interface) are important characteristics that influence the performance of many major semiconductor devices such as MOSFETs, TFTs, CCDs, and solar cells. In particular, in the field of silicon carbide (SiC), which is expected as a next-generation power semiconductor, improving the performance of power MOSFETs is one of the most important issues, but there are many defects (interface states) at the oxide film / SiC interface. ) And the channel mobility at the MOS interface is extremely low.

  In the evaluation of the oxide film / SiC interface, it was found that the interface state density increased exponentially as the energy band edge was approached, and this energy shallow interface state resulted in a decrease in channel mobility. I know that

  Therefore, there is an urgent need to establish a method for accurately evaluating this energy-shallow interface state (a method for accurately determining both the energy position and the interface state density).

  It is no exaggeration to say that the evaluation method of the interface state density of the insulating film / semiconductor interface has hardly progressed since it was established in the field of Si 20 to 40 years ago. These evaluation methods include the following.

1) A Turman method for obtaining an interface state density from a difference between a high frequency (0.1-1 MHz) characteristic of a MIS or MOS structure (MIS or MOS capacitor) and a theoretical characteristic.
2) High-low method obtained from CV characteristics of high frequency (0.1-1 MHz) and low frequency (quasi-electrostatic, QS).
3) Conductance method for analysis based on frequency dependence of conductance of MOS structure.

  The three types of evaluation methods 1) to 3) are general, and these are described in many textbooks related to semiconductors. For example, it is described in the following non-patent document 1, which is a typical textbook in this field.

S.M.Sze and K.K.Ng, “Physics of Semiconductor Devices (3rd ed.)”, Chapter 4, (2007, John Wiley & Sons, Inc., USA).

  The problems of the three types of typical interface state density evaluation methods that are the above-described conventional techniques will be described below.

1) Terman method: Measurement is simple.
However, if the sensitivity regarding the absolute value of the interface state density is low and the interface state density is 3 × 10 ¹¹ cm ⁻² eV ⁻¹ or less, the interface state density cannot be accurately evaluated due to the influence of noise and calculation errors.

  In addition, the method for obtaining the energy position corresponding to each interface state density is very ambiguous, and it is impossible to obtain an accurate interface state density distribution.

  2) High-low method: This is a method of performing CV measurement with QS and a high frequency of 0.1-1 MHz, and the measurement is relatively simple. Further, since the quantitative evaluation of the interface state density is relatively good, it is a standard evaluation method in the field of Si.

  However, when the energy position is ambiguous and the interface state density shows a sudden change near the band edge (in the case of SiC, etc.), it is dangerous to apply.

  Further, when applied to the case of SiC, it has been known that the interface state density in the vicinity of the most important band edge is significantly underestimated, which has been a problem. The physical reason for this underestimation was also unclear.

3) Conductance method: The most accurate in terms of absolute evaluation of interface state density.
However, the biggest problem is that it takes a very long time for measurement and data analysis (more than three times the time required for the high-low method).

  Furthermore, the obtained interface state density is obtained only as a discontinuous point corresponding to a specific energy position, and it is impossible to directly obtain the energy distribution of the interface state density necessary for device characteristic analysis.

  In addition, as in the case of the high-low method, there are problems in the ambiguity of the energy position and the quantification of the interface state density near the band edge.

  An object of the present invention is to obtain the defect density (interface state density) at the MIS or MOS interface simply and with high accuracy.

According to one aspect of the present invention, a first step of calculating a semiconductor capacitance (C _D + C _{IT to} C _D ) excluding the influence of the oxide film capacitance based on the CV characteristic at a high frequency of about 100 MHz; / a ^{_{(C D + C IT) 2}} , a second step of plotting against the surface potential Pusaiesu calculated from the low frequency (quasi-electrostatic) C-V _{characteristic, ψs-1 / (C D} + C IT) 2 An insulator / semiconductor interface evaluation method comprising: a third step of determining an absolute value of the surface potential ψs by defining a constant term so that an extrapolated value of the plot passes through the origin. . Here, the order of 100 MHz, which shows the frequency to the extent that the capacitance C _IT due to surface defects in the insulator / semiconductor interface is negligible.

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In the present invention, the relationship between the capacitance (C _D + C _IT ) obtained by subtracting the oxide film capacitance and ψ s using the determined surface potential ψ s is expressed by the capacitance C _IT caused by the interface defect at the insulator / semiconductor interface. On the basis of the fourth step obtained at negligible high and low frequencies and the theoretical characteristics of the semiconductor capacitance C _D using the doping density N _D obtained from the 1 / (C _D + C _IT ) ² −ψs plot, Using the fact that the difference between the low frequency (C _D + C _IT ) characteristic and the theoretical characteristic C _D (theory) becomes the capacitance C _IT due to the interface state, the interface state density D _IT is calculated from the C _IT value. And an insulator / semiconductor interface evaluation method characterized by having a fifth step.

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Instead of the theoretical characteristic C _D (theory), it is also possible to use a C _D + C _IT characteristic having a sufficiently high frequency.

  The semiconductor is SiC, and the high frequency is preferably an ultrahigh frequency of about 100 MHz, but can be applied to any semiconductor material such as Si, Ge, GaAs, and GaN. In a semiconductor with a relatively small forbidden band, since an inversion layer is easily formed at room temperature, it is difficult to obtain the depletion layer capacitance over a wide voltage range. In such a case, a pulse voltage is used. When the pulse CV measurement is performed, a deep depletion state can be obtained, and the depletion layer capacitance can be accurately obtained over a wide range.

  In the present invention, the surface potential ψs obtained by the method for evaluating an insulator / semiconductor interface including the first to third steps is used as the evaluation of the insulator / semiconductor interface including the fourth and fifth steps. In this method, the insulator / semiconductor interface evaluation method is used as the surface potential ψs of the fourth step.

  The present invention is a program for causing a computer to execute the insulator / semiconductor interface evaluation method described above.

  The present invention may be a computer-readable recording medium for recording the program.

According to another aspect of the present invention, insulator / semiconductor C-V characteristic in the degree of high frequency capacitance C _IT due to interface defects can be ignored based on the interface, the semiconductor capacity in which the influence of oxide capacitance ( and the semiconductor capacitance (C _D + C _IT) calculation unit for calculating the C _D + C _IT), the _{1 / (C D + C IT} ) 2 a low-frequency (quasi-electrostatic) surface potential ψs calculated from C-V characteristics The surface potential is determined by determining a constant term so that the extrapolated value of the 1 / (C _D + C _IT ) ² −ψs plot section and the φs−1 / (C _D + C _IT ) ² plot plotted through the origin. An insulator / semiconductor interface evaluation apparatus comprising: an integral constant A calculation unit for determining an absolute value of ψs.

Using finalized the surface potential Pusaiesu, high frequency to the extent that capacity obtained by subtracting the oxide film capacitance and (C _D + C _IT) the relationship between Pusaiesu negligible capacitance C _IT due to surface defects in the insulator / semiconductor interface and and _V G _{-ψ s} plot of MOS capacitors to obtain a low frequency, on the basis of the theoretical characteristics of the semiconductor capacitor Cs with a doping density _{N D} obtained from the _{1 / (C D + C iT} ) 2 -ψs plot, Using the fact that the difference between the low frequency (C _D + C _IT ) characteristic and the theoretical characteristic C _D (theory) becomes the capacitance C _IT due to the interface state, the interface state density D _IT is calculated from the C _IT value. It is preferable to have a required _DIT calculation unit.

  According to the present invention, the defect density (interface state density) at the MIS or MOS interface can be obtained easily (high speed) and with high accuracy.

  In addition, since a continuous energy distribution can be obtained without discontinuous data, a precise analysis result can be obtained.

It is a figure which shows the CV measurement result of MOS capacitor by one embodiment of this invention, and is a figure which shows the measurement result in quasi-electrostatic (QS: quasi-static), 10 kHz, 1 MHz, and 100 MHz. FIG. 2A is an equivalent circuit diagram of a general interface structure including an interface state, and FIG. 2B is a state in which majority carriers are strongly accumulated at the interface. FIG. At high frequencies, it is a plot of relationship between _{1 / (C D + C IT} ) 2 and ψs in depletion state. Here, values of 1 MHz and 100 MHz are shown. The relationship between the C _D + C _IT and Pusaiesu, illustrates the characteristics obtained, the theoretical characteristics at various frequencies. It is a figure which shows the energy distribution of the interface state density calculated | required by the various methods (The method of this application, the conventional high-low method, the conductance method) including this application in the same capacitor. It is a figure which shows an example of the structure of the insulating film / SiC capacitor used by this Embodiment. The various parameters are not limited. It is a diagram showing a relationship between ψs and V _G. It is a flowchart figure which shows an example of the evaluation method of the insulator / semiconductor interface defect by this Embodiment. It is a functional block diagram which shows one structural example of the evaluation apparatus of the insulator / semiconductor interface defect by this Embodiment. For n-type SiC MOS capacitor, it is a graph showing the frequency dependency of the C _D + C _IT measured in accumulation state (ψs = 0.03V).

Hereinafter, an insulator / semiconductor interface defect evaluation technique according to an embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a diagram showing an example of the structure of the insulating film / SiC capacitor used in the present embodiment. The structure and parameters of the insulating film / SiC capacitor are merely examples, and are not limited to the following, and can be used effectively for many structures. In the example illustrated in FIG. 6, an n-type SiC buffer layer, an n-type SiC layer, an insulating film such as SiO ₂ is formed on an n-type 4H—SiC substrate, and the first electrode is formed on the insulating film. A second electrode is formed on the substrate. By applying the voltage Vg between the first electrode and the second electrode, CV measurement can be performed and the capacitance of the capacitor can be obtained.

  FIG. 1 is a diagram showing a CV measurement result of a MOS capacitor (see FIG. 6) according to an embodiment of the present invention, and is in a quasi-static (QS) state (close to DC). It is a figure which shows the measurement result in 10 kHz, 1 MHz, and 100 MHz. FIG. 2 is an equivalent circuit diagram of the MOS capacitor according to the present embodiment, FIG. 2A is an equivalent circuit diagram of a general interface structure including interface states, and FIG. It is an equivalent circuit diagram in a state where majority carriers are strongly accumulated in the capacitor.

In the equivalent circuit diagram shown in FIG. 2A, the MOS capacitor includes an oxide film capacitance Cox, a semiconductor capacitance C _D (V _G ), a capacitance C _IT caused by the interface state, and a conductance G _{IT at} the interface. And series impedance Z.

The decrease in the storage capacity due to the increase in frequency is due to the series parasitic impedance Z, and C _OX and Z are V _G, which is assumed to be a strong storage state, as shown in FIG. = It can be obtained from the impedance at 15V.

  Next, an insulator / semiconductor interface defect evaluation method according to the present embodiment will be described with reference to FIGS.

First, calculation formulas used in the following description are shown.

(1) is an equation for calculating the surface potential depends on V _G. Here, ψs (V _G ) is a surface potential that depends on V _G. C _QS is a quasi-electrostatic capacitance, C _OX is the capacitance of the oxide film, and A is an integral constant.

Equation (2) is a diagram showing the relationship between the measured capacitance C, the semiconductor capacitance C _D, and the oxide film capacitance C _OX . The approximation on the left side holds when the frequency is sufficiently high.

Equation (3) is an equation for obtaining the interface state density D _IT , where C _D + C _IT is the semiconductor capacitance including the interface state, and corresponds to the capacitance measured in QS. D _IT is the interface state density. S is the area of the gate electrode (first electrode in FIG. 6), and e is the elementary charge.

  The expression (4) is an expression in a state in which the interface state does not respond in a sufficiently high frequency and strong depletion state.

_{Here, C depletion} is the depletion layer capacitance, epsilon _SiC is the dielectric constant of SiC, _{N D} is the doping concentration of the SiC.

（５）式は、Ｃ_Dの理論値を求める式である。

Equation (5) is an equation for _obtaining the theoretical value of CD.

  FIG. 8 is a flowchart showing an example of a semiconductor interface evaluation method according to this embodiment. FIG. 9 is a functional block diagram showing a configuration example of the insulator / semiconductor interface defect evaluation apparatus.

In step S1 of FIG. 8, the process is started. Next, in step S2, the CV measurement unit (including the case where the measurement is automatically performed when the user performs measurement, the same applies hereinafter) 100 is 1) QS (quasi-electrostatic) CV measurement, 2) CV measurement at 100 MHz out of high frequency, and 3) CV measurement at 1 MHz. Note that the measurement at 1 MHz is arbitrary, and in FIG. 1, the measurement at 10 kHz is also performed. However, in this step S2, the measurement at QS and 100 MHz is essential. Here, the reason why 100 MHz is used as the high frequency is selected in the equivalent circuit of FIG. 2 as a high frequency that can ignore the _CIT component. As shown in FIG. 1, it has been used conventionally, in a 1MHz frequency, that no rid fully the influence of the capacitance component C _IT due to interface defects which depends on the frequency, the inventors have found.

Next, in step S3, the semiconductor capacitance (C _D + C _IT ) calculation unit 110 calculates the oxide capacitance C _OX component from the capacitance C obtained by the above equation (2) from the 100 MHz capacitance of 2) obtained in step S2. Subtract to get C _D + C _IT . Here, at 100 MHz, the influence of the capacitive component C _IT caused by the frequency-dependent interface defect can be sufficiently removed, that is, C _IT = 0, so that C _D + C _IT = C _D ( (See FIG. 2).

  Next, in step S4, the ψs calculation unit 120 uses the (QS) value of 1) in step S2 from the above equation (1) (see FIG. 3), and the surface potential ψs (Vg) remains unchanged from A. calculate.

Thereby, the relationship between ψs and Vg can be determined while the position of the horizontal axis is indefinite (A indefinite). Figure 7 is a diagram showing an example of the relationship between ψs and V _G. In step S4, but the shape of the curve of the relationship between ψs and V _G shown in FIG. 7 is determined, in practice due Vg is uncertain, the relationship between the ψs and V _G, including the horizontal axis are determined Absent.

Then, in step _{S5, 1 / (C D +} C IT) 2 -ψs plot portion 130, using the ψs obtained in step S4, the obtained high-frequency measuring _{1 / (C D + C IT} ) 2 in ψs Plot against (Figure 3).

FIG. 3 is a graph plotting the relationship between 1 / (C _D + C _IT ) ² and ψs in a depletion state at high frequencies. When determining ψs, the capacity measured by QS is used, and when the vertical axis of FIG. 3 is plotted, the capacity measured at high frequency (100 MH) is used. In FIG. 3, the measured value at 100 MHz and the measured value at 1 MHz are shown as a reference, and it can be seen that the extrapolated value to the origin is almost the same in both cases. Note that since the interface state does not follow 1 MHz in a sufficiently depleted state, an extrapolated value using a value in this region has low frequency dependence and high accuracy.

Next, in step S6, the integral constant A calculation unit 140 extrapolates the plot using the above equation (4) in the 1 / (C _D + C _IT ) ² −ψs characteristic (FIG. 3) plotted in step S5. The absolute value of the surface potential ψs is determined by defining a constant term so that passes through the origin. With the processing so far, the surface potential ψs can be obtained.

Referring to equation (4), which is based on semiconductor physics considerations, ψs is proportional to 1 / (C _D + C _IT ) ² and the origin, so 1 / (C _D + C _IT ) ² −ψs characteristics By allowing the outer insertion value to pass through the origin, the integration constant const (A) of equation (1) can be obtained. In this way, the absolute value of the surface potential ψs can be determined with an accuracy of ± 0.02 eV. The accuracy of the conventional method is about ± 0.1 eV, and it can be seen that the method according to the present embodiment has higher accuracy.

FIG. 4 is a diagram showing characteristics obtained by determining the relationship between C _D + C _IT and ψs at various frequencies, and theoretical characteristics. Here, the theoretical semiconductor capacitance C _D (theory) that does not consider inversion is also plotted. It can be seen that as the frequency increases, the measured value of C _D + C _IT approaches the semiconductor capacitance C _D (theory). That is, the measured value at 1 MHz, which has been conventionally used, is greatly different from the theoretical value, but it was found that the measured value at 100 MHz is quite close to the theoretical value.

Next, in step S7, the V _G -ψ _s plotting unit 150 of the MOS capacitor determines the relationship between Vg and ψs of the MOS capacitor. The relationship between Vg and ψs has already been obtained in step S4 except for the constant term (A). In step S6, since the integration constant A is obtained, the relationship between Vg and ψs is determined at the same time. In other words, the relationship between Vg and ψs of the MOS capacitor in FIG. 7 can be determined entirely including the position on the horizontal axis.

Next, in step S8, the ψs− (C _D + C _IT ) plotting unit 160 plots the relationship between ψ s and C _D + C _IT in terms of QS and the theoretical value (theoretical characteristics of equation (5)). Here, you may plot using the measured value in 100 MHz instead of a theoretical value.

Further, in step S9, the _DIT calculation unit 170 obtains a difference in the plot in step S8, and obtains _DIT using equation (3).

Next, in step S10, the energy conversion unit 180 converts ψs into energy (E _C -E), and the (E _C -E) -D _IT plot unit 190 converts the energy (E _C -E) (see FIG. 5). ) to plot the relationship between the D _IT.

At this time, the semiconductor calculate the Fermi level _{E F} of the (impurity concentration known) (see FIG. 5, if the _{^{1 × 10 16 cm -3, E}} C -E F = 0.19eV), where, [psi _S Becomes 0. The horizontal axis E _C -E in FIG. 5 is calculated by E _F −ψs. When ψs = 0, E _C -E is about 0.1 to 0.2 eV (depending on the doping density).

Thus, the relationship between E _C -E and D _IT shown in FIG. 5 can be obtained. That is, the relationship between the energy level from the conduction band and the interface defect density can be obtained. That is, the insulating film / semiconductor interface defect can be evaluated, and the process ends in step S11.

As shown in FIG. 5, it can be seen that the interface defect density D _IT- (E _C -E) curve measured at 100 MHz shows very good agreement with the plot value obtained with high accuracy by the conductance method. Value obtained in the conventional high-low method, calculated on the basis of the flat band capacitance at 1MHz, even if measured at 1MHz high frequency of about and overlooked the effects of interfacial defects in response, a low estimate too the D _IT I understand that.

  Compared to this, according to the interface defect evaluation technique according to the present embodiment, it was conventionally considered to be highly accurate, but the measurement with the same accuracy as the conductance method, which takes time for measurement, is performed at a higher speed. It can be seen that it is possible. Furthermore, since a continuous curve can be obtained with respect to Ec-E, it can be seen that the interface defects can be easily evaluated in a shorter time than the conductance method.

FIG. 10 is a diagram showing the frequency dependence of C _D + C _IT measured in an accumulation state (ψ _S = 0.03 V) for an n-type SiC MOS capacitor. It can be seen that at 1 MHz, which is a frequency often used in the conventional high-low method, the C _D + C _IT value is clearly larger than the theoretical calculation value, and the interface state having a quick response follows.

On the other hand, in the measurement at 100 MHz, it can be seen that the C _D + C _IT value almost coincides with the theoretical value, and the interface state does not follow.

  As the high frequency value, 50 MHz or more is preferable in the sense that it is close to the theoretical value, and in particular, if it is 100 MHz, it is more preferable in the sense that it is substantially the same as the theoretical value.

  As described above, according to the present embodiment, the defect density (interface state density) at the MIS or MOS interface can be obtained with higher accuracy than any conventional evaluation method. Not only the absolute value but also the accuracy of the energy position is remarkably excellent. Moreover, the measurement / analysis time is almost the same (simple) as the high-low method which is a conventional standard method. Further, a continuous energy distribution can be obtained without discontinuous data as in the conductance method. It corresponds to the precise evaluation of the interface state density near the band edge, and there is no fault of this method.

  In the above-described embodiment, the configuration and the like illustrated in the accompanying drawings are not limited to these, and can be changed as appropriate within the scope of the effects of the present invention. In addition, various modifications can be made without departing from the scope of the object of the present invention. In addition, a program for realizing the functions described in the present embodiment is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into a computer system and executed to execute processing of each unit. May be performed.

  The present invention can be used in a defect evaluation apparatus for an insulator / semiconductor interface.

DESCRIPTION OF SYMBOLS 50 ... Insulating film / semiconductor interface evaluation apparatus, 100 ... CV measuring part m, 110 ... Semiconductor capacity (C _D + C _IT ) calculating part, 120 ... ψs calculating part, 130 ... 1 / (C _D + C _IT ) ² -ψs plot , 140 ... integral constant A calculation unit, 150 ... V _G -ψ _s plot unit of MOS capacitor, 160 ... ψs- (C _D + C _IT ) plot unit, 170 ... D _IT calculation unit, 180 ... energy conversion unit, 190 ... (E _C -E) -D _IT plot section.

Claims (10)

A first step of calculating a semiconductor capacitance (C _D + C _{IT to} C _D ) excluding the influence of the oxide film capacitance based on CV characteristics at a high frequency of about 100 MHz;
A second step of plotting 1 / (C _D + C _IT ) ² against the surface potential ψ s calculated from the low frequency (quasi-electrostatic) CV characteristics;
a third step of determining the absolute value of the surface potential ψs by defining a constant term so that the extrapolated value of ψs-1 / (C _D + C _IT ) ² plot passes through the origin. Method for evaluating an object / semiconductor interface.
Here, C _D is the capacitance of the semiconductor, C _IT is the capacitance due to the interface order, and C is the capacitance of the MOS capacitor. In the first step,

Use
In the second step,

Use
In the third step,

The method for evaluating an insulator / semiconductor interface according to claim 1, wherein:
_{Here, C OX} is the capacitance of the oxide film, _{V G} is the gate _{voltage, C QS} is quasi electrostatic capacitance, A is an integration _{constant, C depletion} is the depletion layer a capacitance, S is the area of the gate electrode, epsilon _SiC is the dielectric constant of SiC, e is the elementary charge, _{N D} is the doping concentration of the SiC. Using finalized the surface potential Pusaiesu, high frequency to the extent that capacity obtained by subtracting the oxide film capacitance and (C _D + C _IT) the relationship between Pusaiesu negligible capacitance C _IT due to surface defects in the insulator / semiconductor interface and A fourth step to find at low frequency;
Based on the theoretical characteristics of the semiconductor capacitor C _D using the doping density N _D obtained from the 1 / (C _D + C _IT ) ² −ψs plot, the low frequency (C _D + C _IT ) characteristic and the theoretical characteristic C _D ( by utilizing the fact that the difference between the theoretical) of a capacitance C _iT due to the interface state, according to claim 1, characterized in that it comprises a fifth step of obtaining the interface state density D _iT from the C _iT value 4. The method for evaluating an insulator / semiconductor interface according to 1. In the fourth step,

Use
In the fifth step,

The method for evaluating an insulator / semiconductor interface according to claim 3, wherein:
_{Here, C D, theory} is the theoretical value of _{C D,} k is the Boltzmann constant, T is _{temperature, (C D + C IT)} QS is the sum of the capacitance due to semiconductor capacity and interface state ( (Semi-electrostatic capacity). The method for evaluating an insulator / semiconductor interface according to claim 3 or 4, wherein the evaluation is performed using a C _D + C _IT characteristic having a sufficiently high frequency instead of the theoretical characteristic C _D (theory). The semiconductor is SiC;
6. The method for evaluating an insulator / semiconductor interface according to claim 5, wherein the high frequency is an ultra high frequency of about 100 MHz.   The surface potential ψs obtained by the method for evaluating an insulator / semiconductor interface according to claim 1 or 2 is calculated by using the fourth method in the method for evaluating an insulator / semiconductor interface according to any one of claims 3 to 5. A method for evaluating an insulator / semiconductor interface, characterized in that it is used as a surface potential ψs of a step.   The program for making a computer perform the evaluation method of the insulator / semiconductor interface of any one of Claim 1-7. Semiconductor capacitance that calculates semiconductor capacitance (C _D + C _IT ) that eliminates the influence of oxide film capacitance based on CV characteristics at high frequencies where the capacitance C _IT caused by interface defects at the insulator / semiconductor interface is negligible (C _D + C _IT ) calculation unit,
And _{1 / (C D + C IT} ) 1 / (C D + C) plotted against calculated by the surface potential Pusaiesu ² from the low frequency (quasi-electrostatic) C-V characteristic ² -Pusaiesu plot section,
1 / (C _D + C _IT ) ² −ψs By having a constant term so that the extrapolated value of the plot passes through the origin, an integral constant A calculation unit for determining the absolute value of the surface potential ψs is provided. Equipment for evaluating insulator / semiconductor interfaces. Using finalized the surface potential Pusaiesu, high frequency to the extent that capacity obtained by subtracting the oxide film capacitance and (C _D + C _IT) the relationship between Pusaiesu negligible capacitance C _IT due to surface defects in the insulator / semiconductor interface and A V _G -ψ _s plot portion of the MOS capacitor obtained at a low frequency;
The _{1 / (C D + C IT} ) 2 -ψs based on the theoretical characteristics of the semiconductor capacitor Cs with a doping density _{N D} obtained from the plot, the low-frequency (C _D + C _IT) characteristics and theoretical characteristic C _D (Theory And a D _IT calculation unit that obtains an interface state density D _IT from the C _IT value by utilizing the fact that the difference from the above is a capacitance C _IT caused by the interface state. The insulator / semiconductor interface evaluation apparatus described in 1.

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