JP2005142304A - Transistor evaluation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To propose a method for extracting an interface fault of a transistor with a simplified method. <P>SOLUTION: The method for evaluating transistor (10) comprises a semiconductor layer (12) formed on an insulator (11), a gate insulating film (15) formed on the semiconductor layer (12), a gate insulating electrode (16) formed on the gate insulating film (15), and a source region (13) and a drain region (14) existing in both sides of the semiconductor layer (12). The interface fault (18) of the semiconductor layer (12) and the gate insulating film (15) can be extracted by measuring the capacitance-voltage characteristic between the electrodes connected to the source region (13) and drain region (14). Since the interface fault can be extracted only by measuring the capacitance-voltage characteristic of the transistor (10), the measuring means can be simplified more than that of the interface fault extracting method of the relate art. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a transistor evaluation method, and more particularly to a technique for extracting an interface defect between a semiconductor layer and a gate insulating film.

It is known that polycrystalline polysilicon formed by a low temperature process of 500 ° C. or less has many interface defects between the semiconductor layer and the gate insulating film. This interface defect depends on the film formation process of the gate insulating film, and becomes a standard for evaluating the performance of the transistor. As a method for extracting the interface defect between the semiconductor layer and the gate insulating film, for example, M. Kimura, Jpn. J. Appl. Phys. 40, 112 (2001), M. Kimura, Jpn. J. Appl. Phys. 40, 5227 ( 2001), M. Kimura, J. Appl. Phys. 91, 3855 (2002) is known. As a technique for extracting interface defects from the CV characteristics (capacitance-voltage characteristics) of a transistor, for example, a technique disclosed in Japanese Patent Application Laid-Open No. 2001-196434 is known.
M. Kimura, Jpn. J. Appl. Phys. 40, 112 (2001) M. Kimura, Jpn. J. Appl. Phys. 40, 5227 (2001) M. Kimura, J. Appl. Phys. 91, 3855 (2002) JP 2001-196434 A

  However, since the techniques disclosed in Non-Patent Documents 1 to 3 described above require a combination of CV characteristics and IV characteristics (current-voltage characteristics), much effort is required to obtain interface defects. It was. Further, in the method disclosed in Patent Document 1 described above, it is necessary to solve complicated equations such as the Poisson equation and the carrier density equation, so that an algorithm for obtaining an interface defect becomes complicated. To solve Poisson's equation, carrier density equation, etc., it is necessary to understand various structural, material, and experimental parameters such as semiconductor layer thickness, dielectric constant, energy band gap, level density, temperature, etc. was there.

  Accordingly, an object of the present invention is to propose a method for extracting interface defects of a transistor by a simple method.

  In order to solve the above problems, a transistor evaluation method of the present invention includes a semiconductor layer formed over an insulator, a gate insulating film formed over the semiconductor layer, and a gate electrode formed over the gate insulating film. And a method for evaluating a transistor having a source region and a drain region present on both sides of a semiconductor layer, and measuring capacitance-voltage characteristics between a gate electrode and an electrode connecting the source region and the drain region Then, the interface defect between the semiconductor layer and the gate insulating film is extracted. Since the interface state between the semiconductor layer and the gate insulating film can be obtained only by measuring the capacitance-voltage characteristics of the transistor, the measurement method can be simplified. In addition, since the interface state density can be obtained without knowing various structural, material, and experimental parameters such as semiconductor layer thickness, dielectric constant, energy band gap, level density, and temperature, Excellent convenience.

  In the transistor evaluation method of the present invention, the capacitance-voltage characteristics are preferably measured by applying a high-frequency voltage and a low-frequency voltage between the gate electrode and the electrode connecting the source region and the drain region. The interface state density can be obtained from the high frequency equivalent capacitance and the low frequency equivalent capacitance.

  In the transistor evaluation method of the present invention, the frequency of the high frequency voltage is preferably 500 Hz or more, and the frequency of the low frequency voltage is preferably 50 Hz or less. Good measurement results can be obtained in this frequency range.

In the transistor evaluation method of the present invention, C _{HF represents} the capacitance per unit area measured when a high frequency voltage is applied to the transistor, and C C represents the capacitance per unit area measured when a low frequency voltage is applied to the transistor. _{When LF is} the gate insulating film capacitance per unit area C _ox , the charge amount of electrons is q, and the interface state density is D _it , D _it = [(C _LF ⁻¹ −C _ox ⁻¹ ) ⁻¹ It is desirable to calculate the interface state density as − (C _HF ⁻¹ −C _ox ⁻¹ ) ⁻¹ ] / q. If C _H and C _L are measured, the interface state density D _it can be easily obtained.

The method for evaluating a transistor of the present invention is extremely effective when applied to a thin film transistor formed on an insulator. When measuring capacitance with a transistor formed on an insulator, unlike the case of a simple MOS structure formed on a semiconductor substrate, capacitance due to defects on the backside of the semiconductor film and other parasitics due to other junctions are measured. Although the capacitance is also included in C _HF and C _LF that are measured, according to the present invention, even if this parasitic capacitance is ignored, the interface state density can be measured with the same degree of accuracy as in the prior art.

In the evaluation method of a transistor of the present invention, C _HF and C _LF measured between the semiconductor layer and the gate electrode is a gate insulating film capacitance, substrate capacitance, when applied to a transistor that includes a parasitic capacitance other than the equivalent capacitance of the interface defects The effect is great. According to the present invention, even if this parasitic capacitance is ignored, the interface state density can be measured with the same degree of accuracy as in the prior art.

  According to the present invention, since the interface state between the semiconductor layer and the gate insulating film can be obtained only by measuring the capacitance-voltage characteristics of the transistor, the measurement method can be simplified. In addition, since the interface state density can be determined without knowing various structural, material, and experimental parameters such as semiconductor layer thickness, dielectric constant, energy band gap, level density, and temperature, Excellent convenience.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
FIG. 2A shows a cross-sectional view of a general MOS (Metal Oxide Semiconductor) structure. As shown in the figure, the MOS structure 20 has a structure in which a silicon oxide film 22 and a metal electrode 23 are stacked on a silicon substrate 21. Interface defects exist at the interface 24 between the silicon oxide film 22 and the silicon substrate 21. When a predetermined AC voltage is applied to the MOS structure 20 and the CV characteristic is measured, the capacitance described by the low-frequency equivalent circuit shown in FIG. 5B and the high-frequency equivalent circuit shown in FIG. It is known that Here, if the low frequency equivalent capacitance per unit area is C _LF and the high frequency equivalent capacitance is C _HF , the following equation is obtained from these equivalent circuit diagrams.
C _LF ⁻¹ = C _ox ⁻¹ + (C _s + C _it ) ⁻¹ (1)
C _HF ⁻¹ = C _ox ⁻¹ + C _s ⁻¹ (2)
Here, C _ox represents the silicon oxide film capacity per unit area, C _s represents the substrate capacity, and C _it represents the equivalent capacity of the interface defect.
If C _s is eliminated from the above equation, the interface state density D _it = C _it / q at the interface 24 can be expressed as the following equation.
D _it = [(C _LF ^-1 -C _ox ^-1 ) ^-1- (C _HF ^-1 -C _ox ^-1 ) ^-1 ] / q (3)
Here, q represents the charge amount of electrons.
Thus, by measuring _CLF and _CHF in the MOS structure, various structural, material, and experimental characteristics such as the thickness, dielectric constant, energy band gap, level density, and temperature of the semiconductor layer are measured. The interface state density _Dit can be obtained without requiring a parameter.

  On the other hand, FIG. 1A shows a general cross-sectional structure of a TFT (Thin Film Transistor) 10. As shown in the figure, the TFT 10 includes a semiconductor layer 12 formed on the insulator 11, a gate electrode 16, a gate insulating film 15 existing between the semiconductor layer 12 and the gate electrode 16, and the semiconductor layer 12. A structure having a source region 13 and a drain region 14 existing on both sides is formed. The insulator 11 corresponds to an insulating thin film or an insulating substrate, such as a silicon oxide film, a glass substrate, a plastic substrate, or a quartz substrate. There is an interface defect at the interface 18 between the gate insulating film 15 and the semiconductor layer 12. A defect also exists in the back interface 17 of the semiconductor layer 12 in contact with the insulator 11, and an equivalent capacitance resulting from the defect is formed. The semiconductor layer 12 forms various parasitic capacitances such as a junction capacitor and a fringe capacitor between the source region 13 and the drain region 14. Since these parasitic capacitances cannot be generated in a simple MOS structure (see FIG. 2) formed on the silicon substrate 21 in which the back interface, the source region, and the drain region do not exist, the equations (1) to (3) are Therefore, the interface state density of the TFT 10 cannot be obtained.

Therefore, in this embodiment, the capacitance per unit area of all parasitic capacitances other than the gate insulating film capacitance, the substrate capacitance, and the equivalent capacitance of the interface defect between the gate insulating film and the semiconductor layer is C _etc. Consider an AC equivalent circuit when a predetermined AC voltage is applied between the electrode connecting the drain region 14 and the gate electrode 16. FIG. 1B shows a low-frequency equivalent circuit, and FIG. 1C shows a high-frequency equivalent circuit. Here, if the low frequency capacity per unit area to be measured is C _LF and the high frequency capacity is C _HF , the following equation is obtained from these equivalent circuit diagrams.
C _LF ⁻¹ = C _ox ⁻¹ + (C _s + C _it ) ⁻¹ + C _etc ⁻¹ (4)
C _HF ⁻¹ = C _ox ⁻¹ + C _s ⁻¹ + C _etc ⁻¹ (5)
If C _s is eliminated from the above equation, the interface state density D _it = C _in / q at the interface 18 can be described as the following equation.
D _it = [(C _LF ^-1 -C _ox ^-1 -C _etc ^-1 ) ^-1- (C _HF ^-1 -C _ox ^-1 -C _etc ^-1 ) ^-1 ] / q (6)
Here, in the transistor formed on the insulator, C _etc is considered to be sufficiently larger than C _ox , C _s , and C _{it in a} range where the gate voltage is sufficiently small. _Therefore , the first and second terms on the right side C _etc ⁻¹ may be considered to be approximately zero. Therefore, equation (6) is approximately equal to equation (3). This is because there is no problem even if an interface defect extraction method (a method for extracting interface defects from high-frequency and low-frequency CV characteristics), which has been used for extracting interface defects of MOS structures, is applied to TFTs. Suggests. Therefore, in the present embodiment, an interface defect extraction method that has been applied to the MOS structure is applied to the TFT to try to extract the interface defect. The specific measurement procedure is as shown in the equations (1) to (3).

  FIG. 3 shows a configuration diagram of the CV measuring apparatus. In order to measure CV of the TFT 10, first, the gate electrode 16 of the TFT 10 surrounded by the shield box 35 is connected to the voltage source 32, and the source region 13 and the drain region 14 are conducted and then connected to the current amplifier 33. To do. The AC signal output from the lock-in amplifier 31 is DC boosted by the voltage source 32 and applied to the gate electrode 16. The output current (drain current) is amplified by the current amplifier 33, and a frequency equal to the AC voltage applied by the lock-in amplifier 31 is sampled. The computer device 34 obtains the CV characteristic of the TFT 10 from the signal sent from the lock-in amplifier 31. The AC voltage applied to the TFT 10 needs at least two types of high frequency and low frequency. The high frequency is preferably 500 Hz or more, and the low frequency is preferably 50 Hz or less.

FIG. 4 shows the result of measuring the CV characteristics of the TFT 10 by dividing the frequency of the lock-in amplifier into two types, low frequency (5 Hz) and high frequency (5 kHz). When the interface state density _Dit was calculated from the measurement result of the CV characteristic using the equation (3), the result of FIG. 5 was obtained. Here, the result of measuring the lower half (mid gap to valence band) of the energy gap of the p-type transistor is shown. Here, E = 0 [eV] indicates the mid gap, and E = −0.5 [eV] indicates the vicinity of the valence band in the energy gap. For comparison with the prior art, the measurement results obtained by the conventional method disclosed in Patent Document 1 are also shown. It was confirmed that the measurement method of the present embodiment can measure the interface state density with the same degree of accuracy in the vicinity of the mid gap as compared with the method of the prior art.

  As described above, according to the interface defect extraction method of the present embodiment, the interface defect can be extracted only by measuring the CV characteristics of the transistor. Therefore, the measurement method is much simpler than the conventional interface defect extraction method. . In addition, it eliminates the need for various structural, material, and experimental parameters such as semiconductor layer thickness, dielectric constant, energy band gap, level density, and temperature. Interface defects can be extracted with the same accuracy.

It is sectional drawing and an equivalent circuit schematic of TFT. It is sectional drawing of MOS structure, and an equivalent circuit schematic. It is a block diagram of a CV measuring apparatus. It is a measurement result of the CV characteristic of a transistor. It is a measurement result of the interface state density of a transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... TFT 11 ... Insulator 12 ... Semiconductor layer 13 ... Source region 14 ... Drain region 15 ... Gate insulating film 16 ... Gate electrode 17 ... Back interface 18 ... Interface

Claims (6)

A semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film, and a source region and a drain region existing on both sides of the semiconductor layer When,
A method for evaluating a transistor comprising
A transistor evaluation method for extracting an interface defect between the semiconductor layer and the gate insulating film by measuring a capacitance-voltage characteristic between the gate electrode and an electrode connecting the source region and the drain region. A method for evaluating a transistor according to claim 1, comprising:
The capacitance-voltage characteristic is measured by applying a high frequency voltage and a low frequency voltage between the gate electrode and an electrode connecting the source region and the drain region. A method for evaluating a transistor according to claim 2, comprising:
The method for evaluating a transistor, wherein the frequency of the high-frequency voltage is 500 Hz or more and the frequency of the low-frequency voltage is 50 Hz or less. A method for evaluating a transistor according to claim 2 or claim 3, wherein
The capacitance per unit area measured when a high frequency voltage is applied to the transistor is C _HF , the capacitance per unit area measured when a low frequency voltage is applied to the transistor is C _LF , and the gate per unit area. When the insulating film capacitance is C _ox , the charge amount of electrons is q, and the interface state density is D _it ,
D _it = [(C _LF ^-1 -C _ox ^-1 ) ^-1- (C _HF ^-1 -C _ox ^-1 ) ^-1 ] / q
As an evaluation method for a transistor, the interface state density is calculated as: A method for evaluating a transistor according to any one of claims 1 to 4, wherein
The transistor evaluation method, wherein the transistor is a thin film transistor formed over an insulator. A method for evaluating a transistor according to claim 5, comprising:
C _HF and C _LF gate insulating film capacitance is measured between the gate electrode and the semiconductor layer, substrate capacitance, including parasitic capacitance other than the equivalent capacitance of the interface defects, evaluation method of a transistor.

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