JP2008109023A5 - - Google Patents
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- JP2008109023A5 JP2008109023A5 JP2006292465A JP2006292465A JP2008109023A5 JP 2008109023 A5 JP2008109023 A5 JP 2008109023A5 JP 2006292465 A JP2006292465 A JP 2006292465A JP 2006292465 A JP2006292465 A JP 2006292465A JP 2008109023 A5 JP2008109023 A5 JP 2008109023A5
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- measurement
- voltage
- change amount
- flat band
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 claims 23
- 238000005259 measurement Methods 0.000 claims 17
- 230000005669 field effect Effects 0.000 claims 8
- 239000010409 thin film Substances 0.000 claims 8
- 238000011156 evaluation Methods 0.000 claims 5
- 239000000758 substrate Substances 0.000 claims 5
- 230000000875 corresponding Effects 0.000 claims 2
Claims (8)
前記電界効果型トランジスタのゲート電圧に対するドレイン電流を測定する第１の測定をし、
前記電界効果型トランジスタに負荷をかけて電荷を注入し、
前記電荷が注入された前記電界効果型トランジスタのゲート電圧に対するドレイン電流を測定する第２の測定をし、
前記第１の測定の結果と前記第２の測定の結果から、閾値電圧の変化量とフラットバンド電圧の変化量を算出し、
前記閾値電圧の変化量と前記フラットバンド電圧の変化量との関係から前記電荷がトラップされた位置を判別することを特徴とする半導体素子の評価方法。 A gate electrode layer on a semiconductor substrate, a method for evaluating a semiconductor device having an insulating layer, a field-effect transistor provided is interposed between the semiconductor substrate and the gate electrode layer,
A first measurement to measure a drain current to the gate voltage of the field effect transistor,
The field effect transistor is loaded to inject charge,
A second measurement for measuring a drain current to the gate voltage of the field-effect transistor in which the charge is injected,
From the result of the first measurement and the result of the second measurement, the change amount of the threshold voltage and the change amount of the flat band voltage are calculated,
Evaluation method of a semiconductor device characterized by determining the position where the electric charge is trapped on the relationship between the amount of change in the change amount of the flat band voltage of the threshold voltage.
前記電界効果型トランジスタのゲート電圧に対するドレイン電流を測定する第１の測定をし、
前記電界効果型トランジスタに負荷をかけて電荷を注入し、
前記電荷が注入された前記電界効果型トランジスタのゲート電圧に対するドレイン電流を測定する第２の測定をし、
前記第１の測定の結果と前記第２の測定の結果から、閾値電圧の変化量とフラットバンド電圧の変化量を算出し、
前記閾値電圧の変化量に対する前記フラットバンド電圧の変化量が、一定の範囲内のときに前記電荷がトラップされた位置を前記絶縁層中であると判定することを特徴とする半導体素子の評価方法。 A gate electrode layer on a semiconductor substrate, a method for evaluating a semiconductor device having an insulating layer, a field-effect transistor provided is interposed between the semiconductor substrate and the gate electrode layer,
A first measurement to measure a drain current to the gate voltage of the field effect transistor,
The field effect transistor is loaded to inject charge,
A second measurement for measuring a drain current to the gate voltage of the field-effect transistor in which the charge is injected,
From the result of the first measurement and the result of the second measurement, the change amount of the threshold voltage and the change amount of the flat band voltage are calculated,
Evaluation method of a semiconductor device variation of the flat band voltage corresponding to the change in the threshold voltage, and judging with the position at which the charges are trapped when within a certain range which is the insulating layer .
前記閾値電圧の変化量に対する前記フラットバンド電圧の変化量が、一定の範囲外のときに前記電荷がトラップされた位置を前記半導体基板と前記絶縁層の界面であると判定することを特徴とする半導体素子の評価方法。 Oite to claim 1 or claim 2,
And wherein the variation of the flat band voltage relative to the change amount of the threshold voltage, determines that the charge is trapped position when out of range of a certain is the interface of the semiconductor substrate and the insulating layer Of evaluating semiconductor device.
前記薄膜トランジスタのゲート電圧に対するドレイン電流を測定する第１の測定をし、
前記薄膜トランジスタに負荷をかけて電荷を注入し、
前記電荷が注入された前記薄膜トランジスタのゲート電圧に対するドレイン電流を測定する第２の測定をし、
前記第１の測定の結果と前記第２の測定の結果から、閾値電圧の変化量とフラットバンド電圧の変化量を算出し、
前記閾値電圧の変化量と前記フラットバンド電圧の変化量との関係から前記電荷がトラップされた位置を判別することを特徴とする半導体素子の評価方法。 A gate electrode layer, a semiconductor layer, a method for evaluating a semiconductor device having an insulating layer, a thin film transistor provided is interposed between the gate electrode layer and the semiconductor layer,
A first measurement to measure a drain current to the gate voltage of the thin film transistor,
The thin film transistor is loaded to inject charge,
A second measurement for measuring a drain current to the gate voltage of the thin film transistor in which the charge is injected,
From the result of the first measurement and the result of the second measurement, the change amount of the threshold voltage and the change amount of the flat band voltage are calculated,
Evaluation method of a semiconductor device characterized by determining the position where the electric charge is trapped on the relationship between the amount of change in the change amount of the flat band voltage of the threshold voltage.
前記薄膜トランジスタのゲート電圧に対するドレイン電流を測定する第１の測定をし、
前記薄膜トランジスタに負荷をかけて電荷を注入し、
前記電荷が注入された前記薄膜トランジスタのゲート電圧に対するドレイン電流を測定する第２の測定をし、
前記第１の測定の結果と前記第２の測定の結果から、閾値電圧の変化量とフラットバンド電圧の変化量を算出し、
前記閾値電圧の変化量に対する前記フラットバンド電圧の変化量が、一定の範囲内のときに前記電荷がトラップされた位置を前記絶縁層中であると判定することを特徴とする半導体素子の評価方法。 A gate electrode layer, a semiconductor layer, a method for evaluating a semiconductor device having an insulating layer, a thin film transistor provided is interposed between the gate electrode layer and the semiconductor layer,
A first measurement to measure a drain current to the gate voltage of the thin film transistor,
The thin film transistor is loaded to inject charge,
A second measurement for measuring a drain current to the gate voltage of the thin film transistor in which the charge is injected,
From the result of the first measurement and the result of the second measurement, the change amount of the threshold voltage and the change amount of the flat band voltage are calculated,
Evaluation method of a semiconductor device variation of the flat band voltage corresponding to the change in the threshold voltage, and judging with the position at which the charges are trapped when within a certain range which is the insulating layer .
前記閾値電圧の変化量に対する前記フラットバンド電圧の変化量が、一定の範囲外のときに前記電荷がトラップされた位置を前記半導体層と前記絶縁層の界面であると判定することを特徴とする半導体素子の評価方法。 Oite to claim 4 or claim 5,
And wherein the variation of the flat band voltage relative to the change amount of the threshold voltage, determines that the charge is trapped position when out of range of a certain is the interface of the insulating layer and the semiconductor layer Of evaluating semiconductor device.
前記一定の範囲は、ずれ量Δを用いて、前記閾値電圧の変化量ΔＶｔｈをＸ軸、前記フラットバンド電圧の変化量ΔＶｓｈｉｆｔをＹ軸としたＸＹ平面上のＸ−Δ≦Ｙ≦Ｘ＋Δで表され、
前記ずれ量Δは
The fixed range is obtained by using a deviation amount Δ, and X−Δ ≦ Y ≦ X + Δ on the XY plane using the threshold voltage change amount ΔV th as the X axis and the flat band voltage change amount ΔV shift as the Y axis. Represented by
The deviation Δ is
前記フラットバンド電圧は、前記トランジスタ及び前記電荷が注入された前記トランジスタのゲート電圧に対するドレイン電流の測定結果から作成された曲線の、飽和領域における接線が、所定の一の電流値になるときの電圧であることを特徴とする半導体素子の評価方法。 In any one of claims 1 to 7,
The flat band voltage, the transistor and the curve generated from the measurement results of the drain current to the gate voltage of said transistor charges are injected, tangent at the saturation region, when a predetermined one of a current value A method for evaluating a semiconductor element, characterized by being a voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006292465A JP5063080B2 (en) | 2006-10-27 | 2006-10-27 | Semiconductor element evaluation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006292465A JP5063080B2 (en) | 2006-10-27 | 2006-10-27 | Semiconductor element evaluation method |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008109023A JP2008109023A (en) | 2008-05-08 |
| JP2008109023A5 true JP2008109023A5 (en) | 2009-09-17 |
| JP5063080B2 JP5063080B2 (en) | 2012-10-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006292465A Expired - Fee Related JP5063080B2 (en) | 2006-10-27 | 2006-10-27 | Semiconductor element evaluation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5063080B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101770964B (en) * | 2008-12-30 | 2011-09-14 | 中芯国际集成电路制造(上海)有限公司 | Test method for introducing charge in technology for forming passivation layer window |
| DE102010031362A1 (en) | 2010-07-15 | 2012-01-19 | Robert Bosch Gmbh | Composite film, process for producing a composite film, a film composite consisting of at least one composite film and apparatus for producing a composite film |
| DE112011102644B4 (en) | 2010-08-06 | 2019-12-05 | Semiconductor Energy Laboratory Co., Ltd. | Integrated semiconductor circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2665378B2 (en) * | 1989-05-31 | 1997-10-22 | 株式会社テック | Document reading device |
| JP2736501B2 (en) * | 1993-09-28 | 1998-04-02 | 三菱電機株式会社 | Simulation method of hot carrier deterioration of MOS transistor |
| JPH0855988A (en) * | 1994-08-09 | 1996-02-27 | Sony Corp | Formation of gate insulation film |
| JP2003007791A (en) * | 2001-06-26 | 2003-01-10 | Sony Corp | Method of evaluating charge trap density and device thereof |
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