KR101672959B1 - Nonvolatile memory device and method of forming the same - Google Patents

Abstract

 A non-volatile memory device is provided. A substrate is provided with a first active region and a second active region defined by a device isolation film. A MOSFET (MOSFET) comprising a first electrode pattern is provided in the first active region. A MOS capacitor comprising a second electrode pattern is provided in the second active region. The width of the first electrode pattern may be smaller than the width of the first active region in the channel width direction.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a nonvolatile memory device,

The present invention relates to a memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device and a method of manufacturing the same.

The semiconductor memory device can be classified into a volatile memory device and a nonvolatile memory device. The nonvolatile memory device can maintain stored data even if the power supply is interrupted. Examples of the nonvolatile memory device include a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable read-only memory (EPROM), and a flash memory device.

Recently, System On Chip (SCO), in which logic devices and memory devices are implemented on a single chip, has been studied as a key component technology in the digital age. For example, it is widely used in mobile DDI (Display Driver IC) chips. When the system-on-chip is equipped with the i-pill as a memory element, the logic element and the memory element are manufactured using the same process.

SUMMARY OF THE INVENTION The present invention provides a semiconductor memory device having improved electrical characteristics and a method of manufacturing the same.

Another object of the present invention is to provide a semiconductor memory device having improved integration and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a semiconductor memory device. The device includes a first active region and a second active region provided on a substrate and defined by a device isolation layer, a MOSFET provided on the first active region and including a first electrode pattern, Wherein the width of the first electrode pattern in the channel width direction may be less than the width of the first active region.

In one embodiment of the present invention, the first electrode pattern and the second electrode pattern may be electrically connected.

In one embodiment of the present invention, a conductive line electrically connecting the first electrode pattern and the second electrode pattern may be formed, and the conductive line may be spaced apart from the substrate by an interlayer insulating layer.

In one embodiment of the present invention, the first electrode pattern may be defined on the first active region.

In one embodiment of the present invention, the first electrode pattern may include a sidewall insulation film provided on a sidewall of the first electrode pattern and overlapped with the first active region and the device isolation film.

In an embodiment of the present invention, the first electrode pattern may extend on the isolation layer and may be connected to the second electrode pattern.

In one embodiment of the present invention, the MOSFET may include a tunnel insulating layer, and the width of the tunnel insulating layer may be smaller than the width of the first active region in the channel width direction.

In one embodiment of the present invention, the lower surface of the tunnel insulating film may be lower than the upper surface of the substrate.

In one embodiment of the present invention, a dent may be provided in the upper edge of the device isolation layer in the channel length direction and expose the upper sidewalls of the first active area and the second active area.

The thickness of the capacitor insulating layer on the upper sidewall of the second active region exposed by the dent may be greater than the thickness of the second active region on the upper surface of the second active region. In one embodiment of the present invention, May be less than the thickness.

In one embodiment of the present invention, a third active region defined by the device isolation layer; And a first well and a second well provided to be spaced apart from each other on the substrate, wherein the first active region and the third active region are provided in a first well, and the second active region is provided in the second well As shown in FIG.

A method of manufacturing a semiconductor memory device to solve the technical problems of the present invention is provided. The method includes forming an isolation layer defining a first active region and a second active region on a substrate, forming an insulating layer on the substrate, forming a conductive layer on the insulating layer, and patterning the conductive layer Forming a first electrode pattern on the first active region and forming a second electrode pattern on the second active region, and forming the first electrode pattern includes forming a first electrode pattern on the first active region, And patterning the conductive layer such that the sidewalls overlap the first active region.

The method may further include forming a sidewall insulation film on the sidewall of the first electrode pattern, wherein the sidewall insulation film overlaps with the first active region and the isolation film.

In one embodiment of the present invention, forming the first electrode pattern may include patterning the conductive film such that the width of the first electrode pattern in the channel width direction is less than the width of the first active region .

In one embodiment of the present invention, the step of forming the insulating layer on the substrate includes forming a first insulating layer between the substrate and the conductive layer, patterning the first insulating layer, The method of claim 1, further comprising: forming a second insulating layer on the exposed first and second active regions, and patterning the first insulating layer, wherein a portion of the first insulating layer And patterning to remain on the first active region.

In one embodiment of the present invention, patterning the first insulating layer may include exposing an upper sidewall of the first active region in a channel length direction.

In one embodiment of the present invention, the patterning of the first insulating layer may include forming a dent by removing a part of the isolation layer in the channel length direction together.

In one embodiment of the present invention, the formation of the second insulating layer may be performed by a thermal oxidation process.

In one embodiment of the present invention, the method may further include forming a conductive line electrically connecting the first electrode pattern and the second electrode pattern.

In one embodiment of the present invention, patterning the conductive layer may include patterning the first electrode pattern and the second electrode pattern to be connected.

The problem of threshold voltage dispersion due to edge thinning of the tunnel insulating film can be solved. Also, the capacitance of the control gate region can be increased.

1 is a circuit diagram of a semiconductor memory device according to embodiments of the present invention.
2 is a plan view of a semiconductor memory device according to a first embodiment of the present invention.
3 is a cross-sectional view taken along the line A-A 'in Fig.
4 is a cross-sectional view taken along the line B-B 'in Fig.
5 is an enlarged view of the area E in Fig.
6 is an enlarged view of the area F in Fig.
7 to 12 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to a first embodiment of the present invention.
13 is a plan view of a semiconductor memory device according to a second embodiment of the present invention.
14 is a cross-sectional view taken along a line G-G 'in Fig.
15 is a cross-sectional view taken along line H-H 'in Fig.
16 is a block diagram of an electronic system including a semiconductor memory device according to embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more readily apparent from the following description of preferred embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In this specification, when it is mentioned that a film (or layer) is on another film (or layer) or substrate, it may be formed directly on another film (or layer) or substrate, or a third film (Or layer) may be interposed. In the drawings, the sizes and thicknesses of the structures and the like are exaggerated for the sake of clarity. It should also be understood that although the terms first, second, third, etc. have been used in various embodiments herein to describe various regions, films (or layers), etc., It should not be. These terms are merely used to distinguish any given region or film (or layer) from another region or film (or layer). Thus, the membrane referred to as the first membrane in one embodiment may be referred to as the second membrane in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. The expression " and / or " is used herein to mean including at least one of the elements listed before and after. Like numbers refer to like elements throughout the specification.

1 is a circuit diagram showing a memory cell array of a semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 1, a non-volatile memory device according to embodiments includes bit lines BL0-BL2, word lines WL0-WL2, common bit line select lines BLS, And a plurality of memory cells MC disposed between the common bit line selection lines BL0-BL2 and the common bit line selection lines BLS. The memory cells MC may include a first transistor TR1 and a second transistor TR2 connected in series. The first transistor TR1 is one of the write, read or erase operations for the memory cells MC according to the voltages applied to the bit lines BL0-BL2 and the word lines WL0-WL2 The first transistor TR1 may be regarded as a selection transistor. The second transistor TR2 is connected to the control gate line CGL and the common bit line selection lines BLS. The second transistor TR2 performs an operation of writing or reading data to or from the memory cells MC and may be referred to as an access transistor. The second transistor TR2 may include a floating gate that performs capacitive coupling with the control gate. The floating gate may be an information storage of the memory cells MC.

2 to 6, a memory device according to a first embodiment of the present invention is described. FIG. 2 is a plan view of a memory device according to a first embodiment of the present invention, FIG. 3 is a cross-sectional view taken along the line A-A 'of FIG. 2, and FIG. 4 is a cross-sectional view taken along line B-B' of FIG. 5 is an enlarged view of portion E of Fig. 3, and Fig. 6 is an enlarged view of portion F of Fig.

Referring to Figures 2 to 4, a substrate 100 is provided. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may be of a structure doped with a first type impurity. For example, the first type impurity may be a p-type impurity. A first well 101 may be provided on the substrate 100. The first well 101 may be of a structure doped with a second type impurity. In one example, the second type impurity may be an n-type impurity. The substrate 100 may include a second well 102 and a third well 103 formed in the first well 101. The second well 102 and the third well 103 may be spaced apart from each other. The second and third wells 102 and 103 may be of a structure doped with a first type impurity. The second and third wells 102 and 103 may be pocket wells.

A device isolation film 140 may be provided which defines a first active region ACT1, a second active region ACT2, a third active region ACT3 and a fourth active region ACT4 of the substrate 100 . The isolation layer 140 may be a silicon oxide layer, particularly a silicon oxide layer formed by a high-density plasma chemical vapor deposition method having excellent gap-fill characteristics. A liner insulating layer 151 may be provided between the device isolation layer 140 and the substrate 100. The liner insulating layer 151 may be an oxide layer formed by a thermal oxidation process.

The first active region ACT1 and the fourth active region ACT4 are defined within the second well 102 and the second active region ACT2 is defined within the third well 103. [ Can be defined. The third active region ACT3 may be defined outside the second and third wells 102,

A MOSFET including the first electrode pattern 122 and the tunnel insulating layer 157 may be provided on the first active region ACT1. A MOS capacitor (hereinafter referred to as MOSCAP) including a second electrode pattern 123 and a capacitor insulating film 158 may be provided on the second active region ACT2. The first and second electrode patterns 122 and 123 may be polysilicon. The tunnel insulating film 157 and the capacitor insulating film 158 may be a thermal oxide film. The lower surfaces of the tunnel insulating film 157 and the capacitor insulating film 158 may be lower than the upper surface of the substrate 100.

The first and second electrode patterns 122 and 123 may be electrically connected through the conductive line 133 and the first and second vias 131 and 132 connected to the conductive line 133. The first via 131 may be provided on the first electrode pattern 122 and the second via 132 may be provided on the second electrode pattern 123. [ The conductive line 133 is separated from the substrate 100 by an interlayer insulating layer 161 and is electrically connected to the first and second via holes 131 and 132 through the interlayer insulating layer 161. [ And can be connected to the electrode patterns 122 and 123. The first and second vias 131 and 132 and the conductive line 133 may include at least one selected from a metal, a metal silicide, a conductive metal nitride, and a doped semiconductor material.

The first and second electrode patterns 122 and 123, the first and second vias 131 and 132, and the conductive line 133 may correspond to a floating gate of a memory device. The third well 103 may correspond to a control gate of a memory device. The memory device according to the first embodiment of the present invention may have a single gate structure. Such a conventional iipilum has cells of a laminated gate structure including a floating gate and a control gate as its unit cell. Therefore, a process of forming a floating gate and a control gate, respectively, is required to realize a laminated gate structure. However, logic devices and EEPROM are fabricated in the same process step to fabricate the EEPROM embedded in the SOC. Logic devices typically employ transistors of a single gate structure. Therefore, the SOC manufacturing process becomes complicated when the EEPROM of the laminated gate structure is embedded in the SOC. The memory device according to the first embodiment of the present invention employs a single gate structure and is easy to manufacture simultaneously with the logic elements.

A gate insulating layer 156 and a third electrode pattern 121 may be provided on the first active region ACT1 and spaced apart from the first electrode pattern 122. [ The third electrode pattern 121 may be connected to the word line of the memory device. The third electrode pattern 121 may be a gate electrode of the selection transistor. The third electrode pattern 121 may extend in the channel width direction of the channel region provided below the gate insulating layer 156 and may be connected to adjacent memory cells. Spacers 163 may be provided on the sidewalls of the electrode patterns 121-123.

A first impurity region 111, a second impurity region 112 and a third impurity region 113 may be provided in the first active region ACT1. The first impurity region 111 and the third impurity region 113 may be provided under the sidewalls of the third electrode pattern 121 and the sidewalls of the first electrode pattern 122, respectively. The second impurity region 112 may be provided between the first and third electrode patterns 122 and 121. The first impurity region 111 may be an impurity region connected to the bit lines BL. The third impurity region 113 may be an impurity region connected to the common bit line select lines BLS. The first through third impurity regions 111-113 may be doped with an impurity of a conductivity type different from that of the second well 102. For example, the first to third impurity regions 111-113 may be doped with a second impurity.

A fourth impurity region 114 may be provided in the fourth active region ACT4. The fourth impurity region 114 may be an impurity region for applying an erase voltage V _ERS to the second well 102. The fourth impurity region 114 may be doped with an impurity of the same conductivity type as that of the second well 102. For example, the second well 102 may be a structure doped with a first type impurity. The doping concentration of the fourth impurity region 114 may be higher than the doping concentration of the second well 102.

A fifth impurity region 115 and a sixth impurity region 116 may be provided in the second active region ACT2. The fifth and sixth impurity regions 115 and 116 may be provided under the sidewalls of the second electrode pattern 123. The fifth and sixth impurity regions 115 and 116 may be an impurity region for applying the control gate voltage V _CG to the second active region ACT2. The fifth and sixth impurity regions 115 and 116 may be regions doped with impurities of different conductivity types. For example, the fifth impurity region 115 may be a region doped with a first impurity and the sixth impurity region 116 may be a region doped with a second impurity. Alternatively, the fifth impurity region 115 may be a region doped with the second impurity and the sixth impurity region 116 may be a region doped with the first impurity. Only one of the fifth and sixth impurity regions 115 and 116 may be provided.

A seventh impurity region 117 may be provided in the third active region ACT3. The seventh impurity region 117 may be an impurity region for applying a voltage to the first well 101. The seventh impurity region 117 may be a region doped with an impurity of the same conductivity type as the first well 101. For example, the seventh impurity region 117 may be a region doped with the second impurity. The doping concentration of the seventh impurity region 117 may be higher than the doping concentration of the first well 101. A plurality of the seventh impurity regions 117 may be formed. For example, the seventh impurity region 117 may be additionally provided between the second well 102 and the third well 103.

A silicide layer (not shown) for ohmic contact may be provided on the upper surfaces of the first to seventh impurity regions 111-117. For example, the silicide layer may be a cobalt silicide layer.

Referring to FIG. 3, a dent (D) may be provided at the edge of the upper portion of the isolation layer 140 in the channel length direction. In this specification, the channel length direction may refer to a channel length direction of a channel region formed under the tunnel insulating film 157. That is, the channel length direction may be a direction parallel to the line A-A '. The channel width direction may refer to a channel width direction of a channel region formed under the tunnel insulating film 157. That is, the channel width direction may be a direction parallel to the B-B 'line. The dent D may be formed by removing a part of the sidewall of the isolation layer 140 during the removal process of the first insulation layer 152, which will be described later. As shown in FIG. 5, the dent D may expose upper sidewalls of the second active region ACT2. The thickness of the capacitor insulating layer 158 is greater than the thickness t2 of the upper sidewall of the second active region ACT2 exposed by the dent D on the upper surface of the second active region ACT2, .

The upper sidewall of the second active region ACT2 exposed by the dent may have a different crystallographic direction from the upper surface of the second active region ACT2. For example, when the top surface of the second active region ACT2 is a {110} plane, the top sidewall of the second active region ACT2 exposed by the dent may not be a {110} plane. Such a difference in crystallographic directionality may cause a difference in thickness of the capacitor insulating film 158 formed on the second active region ACT2. Also, differences in the thicknesses t1 and t2 may occur due to stress concentration occurring when the dent D is formed. That is, edge thinning of the device isolation film may occur.

The capacitor insulating layer 158 may serve as an insulating layer of a capacitor. The thickness of the insulating film of the capacitor in a part of the capacitor is thinned due to edge thinning of the device isolation film, so that the capacitance can be increased. Therefore, the control gate voltage V _CG applied to the memory cell can be reduced, and the area of the second electrode pattern 123 can be reduced, thereby reducing the chip size.

The width W9 of the second electrode pattern 123 in the channel length direction may be larger than the width W6 of the second active area ACT2. In this specification, the width of the active region can be referred to as the width of the upper surface of the active region defined by the device isolation film 140. When the width W9 of the second electrode pattern 123 is larger than the width W6 of the second active area ACT2, all portions of the capacitor insulating film 158 can serve as an insulating film of the capacitor, Can be increased. In addition, since the edge of the capacitor insulating film 158 serves as an insulating film of the capacitor, the capacitance can be increased by the edge thinning.

The first electrode pattern 122 may be provided on the first active region 157. The width W1 of the first electrode pattern 122 in the channel width direction may be smaller than the width W2 of the first active area ACT1 as shown in FIG. The edge thinning phenomenon can be prevented when the width W1 of the first electrode pattern 122 is smaller than the width W2 of the first active area ACT1. 4, when the dent D is formed on the upper sidewall of the device isolation layer 140, the first electrode pattern 122 may be formed on the upper surface of the dent D so as not to overlap the dent D, The width of the pattern 122 can be adjusted. The side wall of the first electrode pattern 122 may overlap with the first active region ACT1. The first electrode pattern 122 and the second electrode pattern 123 may be simultaneously formed and then separated and connected to the conductive line 133 as in the manufacturing method described below. This is for adjusting the width W1 of the first electrode pattern 122 as described above.

The memory device according to the first embodiment of the present invention can perform a write / erase operation through F-N tunneling through the tunnel insulating layer 157. The edge thinning phenomenon may be affected by crystallographic differences, etching processes, and the like as described above. Therefore, the degree of the edge thinning phenomenon may vary depending on the memory cell. That is, the degree of the edge thinning phenomenon depending on the position of the memory cell in the same wafer may be different, and the degree of the edge thinning phenomenon between the memory cells existing in other wafers may be different. Particularly, the insulating film portion where the edge thinning occurs may have a large influence on the write / erase characteristics because the thickness of the insulating film is thin. Therefore, a threshold voltage dispersion problem in which the variation of the threshold voltage between the memory cells becomes large can be caused. The edge thinning of the capacitor insulating film 158 may not cause a problem of threshold voltage dispersion. Therefore, the memory device according to the first embodiment of the present invention can solve the threshold voltage dispersion problem while increasing the capacitance by adjusting the occurrence position of the edge thinning phenomenon.

A sidewall insulating layer 169 may be provided on the sidewall of the first electrode pattern 122 to overlap with the first active region ACT1 and the device isolation layer 140. [ The sidewall insulation film 169 may be a structure for separating the second impurity region 112 and the third impurity region 113 in the impurity implantation process of the second and third impurity regions 112. As shown in FIG. 4, the sidewall insulation film 169 may be in the form of a spacer. The sidewall insulating film 169 may be an oxide film, a nitride film, or a nitride oxide film. The sidewall insulation film 169 may be formed together with the spacer 163 or may be formed by a separate process.

The width W3 of the tunnel insulating film 157 in the channel width direction may be smaller than the width W1 of the first active region ACT1. The width W3 of the tunnel insulating layer 157 may be smaller than the width W2 of the first electrode pattern 122. [ The first active region ACT1 not covered by the tunnel insulating film 157 may be covered with the first insulating film 152 and / or the liner insulating film 151. [ That is, the width of the tunnel insulating layer 157 can be adjusted so that the tunnel insulating layer 157 is spaced apart from the isolation layer 140. The width of the tunnel insulating layer 157 may be controlled to prevent generation of the dent D and the edge thinning as shown in FIG. 6, thereby providing an insulating layer having a uniform thickness t1. The first insulating layer 152 may be an oxide buffer layer for ion implantation used in a well process and / or an oxide layer used in a process for manufacturing a logic device.

According to the first embodiment of the present invention, the occurrence of the edge thinning phenomenon can be controlled to solve the threshold voltage dispersion problem of the memory element while increasing the capacitance.

7 to 12, a method of manufacturing a memory device according to the first embodiment of the present invention is described. Figs. 7, 9 and 11 are sectional views taken along the line A-A 'in Fig. 2, and Figs. 8, 10 and 12 are sectional views taken along the line B-B'

Referring to Figs. 7 and 8, a first well 101 is formed on a substrate 100. Fig. The first well 101 may be of a structure doped with a second type impurity. In one example, the second type impurity may be an n-type impurity. The substrate 100 may be of a structure doped with a first type impurity. For example, the first type impurity may be a p-type impurity. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

An isolation layer 140 may be formed on the substrate 100 on which the first wells 101 are formed to define first to fourth active regions ACT1 to ACT4. The isolation layer 140 may be a silicon oxide layer, particularly a silicon oxide layer formed by a high-density plasma chemical vapor deposition method having excellent gap-fill characteristics. A liner insulating layer 151 may be provided between the device isolation layer 140 and the substrate 100. The liner insulating layer 151 may be an oxide layer formed by a thermal oxidation process.

Second and third wells 102 and 103 may be formed on the substrate 100. The second and third wells 102 and 103 may be formed in the first well 101. The first well 102 and the third well 103 may be spaced apart from each other. The second and third wells 102 and 103 may be of a structure doped with a first type impurity. The second and third wells 102 and 103 may be pocket wells. For example, formation of the second well 102 may include doping the first type impurity multiple times at different concentrations.

A first insulating layer 152 may be formed on the substrate 100. The first insulating layer 152 may be a buffer insulating layer for a well process. Alternatively, the first insulating layer 152 may be an oxide layer or the like used in a logic device manufacturing process. For example, in the DDI process, transistors for various purposes such as LV (low voltage), MV (high voltage) and HV (high voltage) are required, and the thickness of the gate insulating film can be made different.

9 and 10, a part of the liner insulating film 151 and the first insulating film 152 may be patterned. Such a patterning process can be performed by wet etching. The upper edge of the device isolation layer 140 and the upper edge of the active areas ACT1-ACT3 may be removed together by the patterning process. A dent D may be formed on the upper sidewall of the isolation layer 140 by the patterning process. In the first active region ACT1, the distance W7 between the exposed upper sidewalls of the device isolation films 140 may be greater than the width W8 of the first active region ACT1. In the second active region ACT2, the distance W5 between the exposed upper sidewalls of the device isolation films 140 may be greater than the width W6 of the second active region ACT2. The dent D may expose upper sidewalls of the active areas ACT1-ACT3. The upper sidewall of the active regions ACT1-ACT3 may have a different crystal plane than the top surface of the active regions ACT1-ACT3. For example, the top surface of the active regions ACT1-ACT3 may be a {110} plane, and the top sidewalls of the active regions ACT1-ACT3 may not be a {110} plane. Also, stress may be concentrated on the upper sidewalls of the active regions ACT1-ACT3 during the patterning process.

The patterning process may leave a portion of the first insulating layer 152 and / or the liner insulating layer 151 in the first active region ACT1 in the channel length direction, as shown in FIG. For example, the width W3 of the patterning process may be narrower than the width W2 of the first active area ACT1 in the channel width direction.

Referring to FIGS. 11 and 12, the second insulating layer 155 may be formed on the active regions ACT1-ACT3 exposed by the patterning process. The formation of the second insulating layer 155 may be performed by a thermal oxidation process. In the channel width direction, the width of the second insulating film 155 may be the same as the width W3 of the patterning process. The lower surface of the second insulating layer 155 may be lower than the upper surface of the substrate 100. A conductive layer 120 may be formed on the substrate 100. The conductive layer 120 may be polysilicon.

Referring again to FIGS. 2 to 4, the second insulating layer 155 and the conductive layer 120 may be patterned. The first and second tunneling insulating layers 156 and 157, the capacitor insulating layer 158, and the first to third electrode patterns 121 to 123 may be formed by the patterning. The patterning process may be performed such that the width W1 of the first electrode pattern 122 is smaller than the width W2 of the first active area ACT1 in the channel width direction. Therefore, the generation of the dent D in the first active region ACT1 can be prevented. The patterning process may be performed such that the width W9 of the second electrode pattern 123 in the channel length direction is wider than the width W6 of the second active area ACT2 as shown in FIG. . Therefore, the dent D can be formed in the second active region ACT2.

Spacers 163 may be formed on the sidewalls of the electrode patterns 121-123. The spacer may be formed of an oxide film, a nitride film, or a nitride oxide film. A sidewall insulating film 169 may be formed on the sidewall of the first electrode pattern 122 in the channel width direction. The sidewall insulating layer 169 may be formed to overlap with the first active region ACT1 and the device isolation layer 140. The sidewall insulation film 169 may be formed by a spacer process. For example, the sidewall insulation layer 169 may be formed at the same time as the spacers 163.

A first impurity region 111, a second impurity region 112 and a third impurity region 113 may be formed in the first active region ACT1. The first impurity region 111 and the third impurity region 113 may be formed under the sidewalls of the third electrode pattern 121 and the sidewalls of the first electrode pattern 122, respectively. The second impurity region 112 may be formed between the first and third electrode patterns 122 and 121. The first impurity region 111 may be an impurity region connected to the bit lines BL. The third impurity region 113 may be an impurity region connected to the common bit line select lines BLS. The sidewall insulating film 169 is formed such that the second impurity region 112 and the third impurity region 113 are electrically connected to each other when the second impurity region 112 and the third impurity region 113 are formed Can be prevented. The first through third impurity regions 111-113 may be doped with an impurity of a conductivity type different from that of the second well 102. For example, the first to third impurity regions 111 to 113 may be formed by doping the substrate 100 with a second impurity.

A fourth impurity region 114 may be formed in the fourth active region ACT4. The fourth impurity region 114 may be an impurity region for applying an erase voltage V _ERS to the second well 102. The fourth impurity region 114 may be doped with an impurity of the same conductivity type as that of the second well 102. For example, the second well 102 may be formed by doping the substrate 100 with a first type impurity. The fourth impurity region 114 may be doped with a higher doping concentration than the second well 102.

A fifth impurity region 115 and a sixth impurity region 116 may be formed in the second active region ACT2. The fifth and sixth impurity regions 115 and 116 may be formed under the sidewalls of the second electrode pattern 123. The fifth and sixth impurity regions 115 and 116 may be an impurity region for applying the control gate voltage V _CG to the second active region ACT2. The fifth and sixth impurity regions 115 and 116 may be regions doped with impurities of different conductivity types. For example, the fifth impurity region 115 may be formed by doping with the first impurity and the sixth impurity region 116 may be formed by doping with the second impurity. Alternatively, the fifth impurity region 115 may be formed by doping with the second impurity and the sixth impurity region 116 may be formed by doping with the first impurity. Only one of the fifth and sixth impurity regions 115 and 116 may be formed.

A seventh impurity region 117 may be formed in the third active region ACT3. The seventh impurity region 117 may be an impurity region for applying a voltage to the first well 101. The seventh impurity region 117 may be formed by doping the substrate 100 with an impurity of the same conductivity type as that of the first well 101. For example, the seventh impurity region 117 may be formed by doping the substrate 100 with a second impurity. The seventh impurity region 117 may be doped at a doping concentration higher than the doping concentration of the first well 101. [ A silicide layer (not shown) for ohmic contact may be provided on the upper surfaces of the first to seventh impurity regions 111-117. For example, the silicide layer may be a cobalt silicide layer.

An interlayer insulating layer 161 may be formed on the substrate 100. A conductive line 133 may be formed on the interlayer insulating layer 161 to electrically connect the first electrode pattern 122 and the second electrode pattern 123 to each other. First and second vias 131 and 132 for connecting the conductive line 133 and the first and second electrode patterns 122 and 123 may be formed. The first and second vias 131 and 132 and the conductive line 133 may be formed of at least one selected from a metal, a metal silicide, a conductive metal nitride, and a doped semiconductor material.

According to the first embodiment of the present invention, the edge thinning effect can be adjusted to improve the threshold voltage dispersion problem and increase the capacitance.

13 to 15, a memory element and a method of manufacturing the same according to a second embodiment of the present invention are provided. For brevity's sake, the description of redundant technical features may be omitted.

13 is a plan view of a memory device according to a second embodiment of the present invention. 14 is a cross-sectional view taken along line G-G 'of FIG. 13, and FIG. 15 is a cross-sectional view taken along line H-H' of FIG.

13 to 15, a substrate 100 is provided. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may be of a structure doped with a first type impurity. For example, the first type impurity may be a p-type impurity. A first well 101 may be provided on the substrate 100. The first well 101 may be of a structure doped with a second type impurity. In one example, the second type impurity may be an n-type impurity. The substrate 100 may include a second well 102 and a third well 103 formed in the first well 101. The first well 102 and the third well 103 may be spaced apart. The second and third wells 102 and 103 may be of a structure doped with a first type impurity. The second and third wells 102 and 103 may be pocket wells.

A device isolation film 140 may be provided which defines a first active region ACT1, a second active region ACT2, a third active region ACT3 and a fourth active region ACT4 of the substrate 100 . The isolation layer 140 may be a silicon oxide layer, particularly a silicon oxide layer formed by a high-density plasma chemical vapor deposition method having excellent gap-fill characteristics. A liner insulating layer 151 may be provided between the device isolation layer 140 and the substrate 100. The liner insulating layer 151 may be an oxide layer formed by a thermal oxidation process.

The first active region ACT1 and the fourth active region ACT4 are defined within the second well 102 and the second active region ACT2 is defined within the third well 103. [ Can be defined. The third active region ACT3 may be defined outside the second and third wells 102,

A fourth electrode pattern 124 may be provided on the substrate 100. The fourth electrode pattern 124 may include a first portion 125 on the first active region ACT1 and a second portion 126 on the second active region ACT2.

The first portion 125 of the fourth electrode pattern 124 may form a MOSFET together with the tunnel insulating layer 157 on the first region 125. The second portion 126 of the fourth electrode pattern 124 may form a MOS cap with the capacitor insulating layer 158 on the second region.

As shown in FIG. 14, the first insulating layer 152 and / or the liner insulating layer 151 may be provided at the edge of the first active region ACT1 in the channel length direction. The first insulating layer 152 and / or the liner insulating layer 151 may prevent edge thinning in a region where the first active region ACT1 and the fourth electrode pattern 124 overlap.

A capacitor insulating layer 158 may be provided between the fourth electrode pattern 124 and the second active region ACT2. The tunnel insulating film 157 and the capacitor insulating film 158 may be a thermal oxide film. The lower surfaces of the tunnel insulating film 157 and the capacitor insulating film 158 may be lower than the upper surface of the substrate 100.

The memory device according to the second embodiment of the present invention may have a single gate structure. Such a conventional iipilum has cells of a laminated gate structure including a floating gate and a control gate as its unit cell. Therefore, a process of forming a floating gate and a control gate, respectively, is required to realize a laminated gate structure. However, logic devices and EEPROM are fabricated in the same process step to fabricate the EEPROM embedded in the SOC. Logic devices typically employ transistors of a single gate structure. Therefore, the SOC manufacturing process becomes complicated when the EEPROM of the laminated gate structure is embedded in the SOC. The memory device according to the embodiment of the present invention employs a single gate structure and is easy to manufacture simultaneously with the logic elements. According to the second embodiment, unlike the first embodiment, a single electrode pattern can be formed without a separate conductive line.

A gate insulating layer 156 and a third electrode pattern 121 may be provided on the first active region ACT1 and spaced apart from the first electrode pattern 122. [ The third electrode pattern 121 may be connected to the word line of the memory device. The third electrode pattern 121 may be a gate electrode of the selection transistor. The third electrode pattern 121 may extend in the channel width direction of the channel region provided below the gate insulating layer 156 and may be connected to adjacent memory cells.

A first impurity region 111, a second impurity region 112 and a third impurity region 113 may be provided in the first active region ACT1. The second impurity region 112 may be provided between the first and third electrode patterns 122 and 121. The first impurity region 111 may be an impurity region connected to the bit lines BL. The third impurity region 113 may be an impurity region connected to the common bit line select lines BLS. The first through third impurity regions 111-113 may be doped with an impurity of a conductivity type different from that of the second well 102. For example, the first to third impurity regions 111-113 may be doped with a second impurity.

A fourth impurity region 114 may be provided in the fourth active region ACT4. The fourth impurity region 114 may be an impurity region for applying an erase voltage V _ERS to the second well 102. The fourth impurity region 114 may be doped with an impurity of the same conductivity type as that of the second well 102. For example, the second well 102 may be a structure doped with a first type impurity. The doping concentration of the fourth impurity region 114 may be higher than the doping concentration of the second well 102.

A fifth impurity region 115 and a sixth impurity region 116 may be provided in the second active region ACT2. The fifth and sixth impurity regions 115 and 116 may be provided under the side wall of the fourth electrode pattern 124. The fifth and sixth impurity regions 115 and 116 may be an impurity region for applying the control gate voltage V _CG to the second active region ACT2. The fifth and sixth impurity regions 115 and 116 may be regions doped with impurities of different conductivity types. For example, the fifth impurity region 115 may be a region doped with a first impurity and the sixth impurity region 116 may be a region doped with a second impurity. Alternatively, the fifth impurity region 115 may be a region doped with the second impurity and the sixth impurity region 116 may be a region doped with the first impurity. Only one of the fifth and sixth impurity regions 115 and 116 may be provided in the second active region ACT2.

A seventh impurity region 117 may be provided in the third active region ACT3. The seventh impurity region 117 may be an impurity region for applying a voltage to the first well 101. The seventh impurity region 117 may be a region doped with an impurity of the same conductivity type as the first well 101. For example, the seventh impurity region 117 may be a region doped with the second impurity. The doping concentration of the seventh impurity region 117 may be higher than the doping concentration of the first well 101. A plurality of the seventh impurity regions 117 may be formed. For example, the seventh impurity region 117 may be additionally provided between the second well 102 and the third well 103.

A silicide layer (not shown) for ohmic contact may be provided on the upper surfaces of the first to seventh impurity regions 111-117. For example, the silicide layer may be a cobalt silicide layer.

Referring to FIG. 14, a dent (D) may be provided at an edge of an upper portion of the isolation layer 140 in a channel length direction. The dent D may be formed by removing a part of the sidewall of the isolation layer 140 during the removal process of the first insulation layer 152. The dent D may expose an upper sidewall of the second active region ACT2. The upper sidewall of the second active region ACT2 exposed by the dent may have a different crystallographic direction from the upper surface of the second active region ACT2. For example, when the top surface of the second active region ACT2 is a {110} plane, the top sidewall of the second active region ACT2 exposed by the dent may not be a {110} plane. Such a difference in crystallographic directionality may cause a difference in thickness of the capacitor insulating film 158 formed on the second active region ACT2. Also, the thickness difference may occur due to stress concentration occurring when the dent D is formed. That is, edge thinning of the device isolation film may occur.

The capacitor insulating layer 158 may serve as an insulating layer of a capacitor. The thickness of the insulating film of the capacitor in a part of the capacitor is thinned due to edge thinning of the device isolation film, so that the capacitance can be increased. Therefore, the control gate voltage V _CG applied to the memory cell can be reduced, and the area of the fourth electrode pattern 124 can be reduced, thereby reducing the chip size.

The width W1 of the first region 125 of the fourth electrode pattern 124 in the channel width direction may be smaller than the width W2 of the first active region ACT1. The edge thinning phenomenon can be prevented when the width W1 of the first region 125 is smaller than the width W2 of the first active region ACT1. The sidewalls of the first region 125 may overlap the first active region ACT1.

A sidewall insulation film 169 overlapping the first active region ACT1 and the device isolation film 140 may be provided on the sidewall of the first region 125. [ The sidewall insulating film 169 may be a structure for separating the second impurity region 112 and the third impurity region 113 in the impurity implantation process of the second and third impurity regions 112 and 113. As shown in FIG. 4, the sidewall insulation film 169 may be in the form of a spacer. The sidewall insulating film 169 may be an oxide film, a nitride film, or a nitride oxide film.

The width W3 of the tunnel insulating film 157 in the channel width direction may be smaller than the width W1 of the first active region ACT1. The width W3 of the tunnel insulating layer 157 may be smaller than the width W2 of the first electrode pattern 122. [ The first active region ACT1 not covered by the tunnel insulating film 157 may be covered with the first insulating film 152 and / or the liner insulating film 151. [ That is, the width of the tunnel insulating layer 157 can be adjusted so that the tunnel insulating layer 157 is spaced apart from the isolation layer 140. Adjusting the width of the tunnel insulating film 157 can prevent the generation of the dent D and the edge thinning phenomenon, thereby providing an insulating film having a uniform thickness t1. The first insulating layer 152 may be an oxide buffer layer for ion implantation used in a well process and / or an oxide layer used in a process for manufacturing a logic device.

According to an embodiment of the present invention, it is possible to control the occurrence of the edge thinning phenomenon to solve the threshold voltage dispersion problem of the memory device while increasing the capacitance.

The magnetic memory devices according to the first and second embodiments described above can be implemented in various types of semiconductor packages. For example, the semiconductor memory devices according to the embodiments of the present invention can be used in a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Level Processed Stack Package (WSP) or the like. The package in which the semiconductor memory device according to the embodiments of the present invention is mounted may further include a controller and / or a logic device for controlling the semiconductor memory device.

16 is a block diagram of an electronic system including a semiconductor memory device according to embodiments of the present invention.

16, an electronic system 1100 according to an embodiment of the present invention includes a controller 1110, an I / O device 1120, a memory device 1130, an interface 1140, and a bus 1150, bus). The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 may be coupled to each other via the bus 1150. The bus 1150 corresponds to a path through which data is moved.

The controller 1110 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The storage device 1130 may include at least one of the semiconductor storage elements disclosed in the first and second embodiments described above. Further, the storage device 1130 may further include other types of semiconductor storage elements (ex, flash storage elements, DRAM elements, and / or Slam elements). The interface 1140 may perform functions to transmit data to or receive data from the communication network. The interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 1100 is an operation memory for improving the operation of the controller 1110, and may further include a high-speed DRAM and / or an esram.

The electronic system 1100 may be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a digital music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

100: substrate 101, 102, 103:
111-117: impurity regions 121, 122 and 123: electrode pattern
133: conductive line 140: element isolation film
157: tunnel insulating film 158: capacitor insulating film
169: sidewall insulation film

Claims (11)

A first active region and a second active region provided in the substrate and defined by a device isolation layer;
Wherein the width of the first electrode pattern in the channel width direction is greater than the width of the first active region in the channel width direction, Less than width; And
And a MOS capacitor provided in the second active region and including a second electrode pattern,
Wherein the lower surface of the tunnel insulating film is lower than the upper surface of the substrate. The nonvolatile memory device according to claim 1, wherein the first electrode pattern and the second electrode pattern are electrically connected. The nonvolatile memory device according to claim 2, further comprising a conductive line electrically connecting the first electrode pattern and the second electrode pattern, wherein the conductive line is separated from the substrate by an interlayer insulating film. 4. The nonvolatile memory device according to claim 3, wherein the first electrode pattern is defined on the first active region. The nonvolatile memory element according to claim 1, comprising a sidewall insulation film provided on a sidewall of the first electrode pattern and overlapped with the first active region and the isolation film. The nonvolatile memory device according to claim 1, wherein the first electrode pattern extends on the device isolation film and is connected to the second electrode pattern. The nonvolatile memory device according to claim 1, wherein a width of the tunnel insulating film in the channel width direction is smaller than a width of the first active region. delete Board;
An element isolation layer disposed in the substrate, the element isolation layer defining a first active region and a second active region;
A MOSFET (MOSFET) provided in the first active region and including a first electrode pattern; And
And a MOS capacitor provided in the second active region and including a second electrode pattern,
And a dent provided at an edge of an upper portion of the device isolation film in a channel length direction and exposing an upper sidewall of the first active region and the second active region. 10. The semiconductor memory device of claim 9, wherein the MOS capacitor comprises a capacitor insulating layer, and the thickness of the capacitor insulating layer is less than the thickness of the upper sidewall of the second active region exposed by the dent, A nonvolatile memory device. Board;
A device isolation layer disposed in the substrate and defining a first active region, a second active region, and a third active region;
A first well and a second well disposed in the substrate and spaced apart from each other;
A MOSFET (MOSFET) disposed on the first active region and including a first electrode pattern; And
And a MOS capacitor disposed on the second active region and including a second electrode pattern,
Wherein the first electrode pattern is smaller in width than the first active region in a channel width direction,
Wherein the first active region and the third active region are disposed in the first well and the second active region is disposed in the second well.

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