KR20120015930A - Nonvolatile memory device and method of forming the same - Google Patents

Abstract

PURPOSE: A non-volatile memory device and a forming method thereof are provided to multiply capacitance of a control gate region by using an edge thinning phenomenon of a capacitor dielectric film. CONSTITUTION: A first active region and a second active region which is defined by a first element isolation film are formed on a substrate(100). A metallic oxide semiconductor field effect transistor including a first electrode pattern(125) is formed in the first active region. A first impurity region(111), a second impurity region(112), and a third impurity region(113) are formed in the first active region. A metallic oxide semiconductor capacitor including a second electrode pattern(126) is formed in the second active region. A second element isolation film is formed under the second electrode pattern.

Description

Nonvolatile memory device and method of forming the same {NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME}

The present invention relates to a memory device and a method of manufacturing the same, and more particularly to a nonvolatile memory device and a method of manufacturing the same.

Semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. The nonvolatile memory device may retain stored data even when power supply is cut off. Examples of the nonvolatile memory device include a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EPEPROM), a flash memory device, and the like.

Recently, System On Chip (SCO), in which logic and memory devices are implemented on one chip, has been studied as a core component technology in the digital era. For example, Ypyrom is widely used in a mobile display driver IC (DDI) chip. In the case where the system-on-chip includes Y pyrom as a memory element, a logic element and a memory element are manufactured using the same process.

One object of the present invention is to provide a semiconductor memory device having improved electrical characteristics and a method of manufacturing the same.

Another object of the present invention is to provide a semiconductor memory device having an improved degree of integration and a method of manufacturing the same.

A semiconductor memory device for achieving the above technical problem is provided. The device is provided in a first active region and a second active region defined in a substrate and defined by a first device isolation film, a MOSFET provided in the first active region and comprising a first electrode pattern, provided in the second active region The MOS capacitor may include a MOS capacitor including a second electrode pattern electrically connected to the first electrode pattern, and a second device isolation layer provided on the substrate under the second electrode pattern.

In example embodiments, the second active region may include a plurality of active patterns separated by the second device isolation layer.

In an exemplary embodiment, the distance between the upper sidewalls of the plurality of active patterns and the second electrode pattern may be smaller than the distance between the upper surface of the plurality of active patterns and the second electrode pattern.

In an embodiment, the MOS capacitor includes a capacitor insulating film between the second active region and the second electrode pattern, wherein the capacitor insulating film has a thickness on the upper sidewalls of the plurality of active patterns. It may be smaller than the thickness on the top surface of the active pattern.

In example embodiments, the device may include a dent provided at an edge of an upper portion of the device isolation layer and exposing upper sidewalls of the plurality of active patterns.

In one embodiment of the present invention, the dent may surround each of the plurality of active patterns.

In example embodiments, the second device isolation layer may have a strip shape crossing the second electrode pattern under the second electrode pattern.

In example embodiments, the second electrode pattern may expose end portions of the strip-shaped active patterns.

In one embodiment of the present invention, the second device isolation layer may have a shape separated in a first direction and a second direction crossing the first direction.

In one embodiment of the present invention, the second device isolation layer may be connected to the first device isolation layer.

In one embodiment of the present invention, the width of the second device isolation layer in the direction connecting the MOSFET and the MOS capacitor may be smaller than the width of the first device isolation layer.

In one embodiment of the present invention, the thickness of the second device isolation layer may be thinner than the thickness of the first device isolation layer.

In an embodiment, the semiconductor device may further include a third active region defined by the first device isolation layer, and first and second wells provided apart from each other on the substrate, wherein the first active region and The third active region may be provided in a first well, and the second active region may be provided in the second well.

A method of manufacturing a semiconductor memory device for solving the technical problem of the present invention is provided. The method includes forming an isolation layer defining a first active region and a second active region on a substrate, and forming a first electrode pattern on the first active region, and forming the first on the second active region. The method may include forming a second electrode pattern connected to the first electrode pattern, the second active region may include a plurality of active patterns, and the device isolation layer may be formed between the plurality of active patterns.

In one embodiment of the present invention, an electrode connection pattern extending from the first electrode pattern is connected to the second electrode pattern, the electrode connection pattern may be formed simultaneously with the first and second electrode pattern have.

In example embodiments, forming the device isolation layer may include forming a first device isolation layer between the first active region and the second active region, and forming a second device isolation layer between the active patterns. It may include forming.

In one embodiment of the present invention, forming the device isolation layer may include forming a first trench having a first depth in the substrate, forming a second trench deeper than the first depth in the substrate, and The method may include forming a first device isolation layer in the first trench and forming a second device isolation layer in the second trench.

In one embodiment of the present invention, the second trench may extend in a first direction and a second direction crossing the first direction.

In one embodiment of the present invention, forming a capacitor insulating film between the plurality of active patterns and the second electrode pattern, wherein forming the capacitor insulating film is to form a first insulating film on the substrate, Etching the first insulating film to expose the plurality of active patterns, and forming a thermal oxide film on the exposed plurality of active patterns, wherein etching the first insulating film includes: And exposing the upper sidewalls.

In one embodiment of the present invention, the thermal oxide film may be formed to have a thickness on the upper sidewall of the plurality of active patterns is thinner than the thickness on the top surface of the plurality of active patterns.

An edge thinning phenomenon of the capacitor insulating layer may be used to increase the capacitance of the control gate region.

1 is a circuit diagram of a semiconductor memory device according to embodiments of the present invention.
2 is a plan view of a semiconductor memory device according to a first embodiment of the present invention.
3 is a cross-sectional view taken along line II ′ of FIG. 2.
4 is a cross-sectional view taken along the line JJ 'of FIG. 2.
FIG. 5 is an enlarged view of region K of FIG. 3.
6 to 15 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with a first embodiment of the present invention.
16 to 17 are cross-sectional views illustrating a semiconductor memory device and a method of manufacturing the same according to a modification of the first embodiment of the present invention.
18 is a plan view of a semiconductor memory device according to a second embodiment of the present invention.
19 is a cross-sectional view taken along the line M-M 'of FIG. 18.
20 is a cross-sectional view taken along the line N-N 'of FIG. 18.
21 to 28 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with a second embodiment of the present invention.
29 and 30 are cross-sectional views illustrating a semiconductor memory device and a method of manufacturing the same according to a modification of the second embodiment of the present invention.
31 is a block diagram of an electronic system including a semiconductor memory device according to example embodiments.

Objects, other objects, features and advantages of the present invention will be readily understood through the following preferred embodiments associated with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the present specification, when it is mentioned that a film (or layer) is on another film (or layer) or substrate, it may be formed directly on another film (or layer) or substrate or a third film between them. In addition, in the drawings, sizes, thicknesses, etc. of components are exaggerated for clarity. In addition, in various embodiments herein, the terms first, second, third, etc. are used to describe various regions, films (or layers), etc., but these regions, films are defined by these terms. It should not be. These terms are merely used to distinguish any given region or film (or layer) from another region or film (or layer). Therefore, the film quality referred to as the first film quality in one embodiment may be referred to as the second film quality in other embodiments. Each embodiment described and illustrated herein also includes its complementary embodiment. The expression 'and / or' is used herein to include at least one of the components listed before and after. Portions denoted by like reference numerals denote like elements throughout the specification.

1 is a circuit diagram illustrating a memory cell array of a semiconductor memory device according to example embodiments.

Referring to FIG. 1, a nonvolatile memory device according to example embodiments may include bit lines BL0-BL2, word lines WL0-WL2, a common bit line select line BLS, and the bit lines BL0-. It may include a plurality of memory cells MC disposed between BL2 and the common bit line select line BLS. The memory cells MC may include a first transistor TR1 and a second transistor TR2 connected in series. According to the voltages applied to the bit lines BL0-BL2 and the word lines WL0-WL2, the first transistor TR1 may perform one of write, read, or erase operations on the memory cells MC. As selected, the first transistor TR1 may be referred to as a selection transistor. The second transistor TR2 is connected to a control gate line CGL and the common bit line select line BLS. The second transistor TR2 may be referred to as an access transistor as it performs a write or read operation on the memory cells MC. The second transistor TR2 may include a floating gate that performs capacitive coupling with the control gate. The floating gate may be an information storage of the memory cells MC.

2 to 5, a memory device according to a first embodiment of the present invention is described. 2 is a plan view of a memory device according to a first exemplary embodiment of the present invention, FIG. 3 is a cross-sectional view taken along line II ′ of FIG. 2, and FIG. 4 is a cross-sectional view taken along line J-J ′ of FIG. 2. 5 is an enlarged view of a portion K of FIG. 3.

2 to 5, a substrate 100 is provided. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may have a structure doped with a first type impurity. For example, the first type impurities may be p-type impurities. The first well 101 may be provided on the substrate 100. The first well 101 may have a structure doped with a second type impurity. For example, the second type impurities may be n-type impurities. The substrate 100 may include a second well 102 and a third well 103 formed in the first well 101. The second well 102 and the third well 103 may be spaced apart from each other. The second and third wells 102 and 103 may have a structure doped with a first type impurity. The second and third wells 102 and 103 may be pocket wells.

A first device isolation layer 140 may be provided to define a first active region ACT1, a second active region ACT2, a third active region ACT3, and a fourth active region ACT4 of the substrate 100. Can be. The first device isolation layer 140 may be a silicon oxide layer, in particular, a silicon oxide layer formed by a high density plasma chemical vapor deposition method having excellent gap-fill characteristics. A liner insulating layer 151 may be provided between the first device isolation layer 140 and the substrate 100. The liner insulating layer 151 may be an oxide film formed by a thermal oxidation process.

The first active region ACT1 and the fourth active region ACT4 are defined inside the second well 102, and the second active region ACT2 is defined inside the third well 103. Can be defined. The third active region ACT3 may be defined outside the second and third wells 102 and 103.

A MOSFET may be provided on the first active region ACT1 including a first electrode pattern 125 and a tunnel insulating layer 157. A MOS capacitor (MOSCAP) including a second electrode pattern 126 and a capacitor insulating layer 158 may be provided on the second active region ACT2. The first device isolation layer 140 may be provided between the MOSFET and the MOSFET. The first and second electrode patterns 125 and 126 may be polysilicon. The tunnel insulating layer 157 and the capacitor insulating layer 158 may be thermal oxide layers. Lower surfaces of the tunnel insulating layer 157 and the capacitor insulating layer 158 may be lower than the upper surface of the substrate 100. Spacers 163 may be provided on sidewalls of the first and second electrode patterns 125 and 126. An interlayer insulating layer 161 may be provided to cover the MOSFET and the MOSFET.

An electrode connection pattern 127 extending from the first electrode pattern 125 and connected to the second electrode pattern 126 may be provided. The first and second electrode patterns 125 and 126 and the electrode connection pattern 127 may be made of the same material. The first and second electrode patterns 125 and 126 and the electrode connection pattern 127 may be a single pattern connected to each other. The first and second electrode patterns 125 and 126 and the electrode connection pattern 127 may correspond to floating gates of a memory device. The third well 103 may correspond to a control gate of the memory device. The memory device according to the first embodiment of the present invention may have a single gate structure. The conventional ypyrom has a cell having a stacked gate structure including a floating gate and a control gate as unit cells thereof. Therefore, in order to implement a stacked gate structure, a process of forming a floating gate and a control gate, respectively, is required. However, to manufacture EEPROM embedded in SOC, logic devices and EEPROM are manufactured in the same process step. Logic elements typically employ transistors of single gate structure. Therefore, the SOC fabrication process is complicated to embed EEPROM of the stacked gate structure in the SOC. The memory device according to the first embodiment of the present invention adopts a single gate structure and can be easily manufactured at the same time as the logic devices.

The gate insulating layer 156 and the third electrode pattern 121 may be provided on the first active region ACT1 to be spaced apart from the first electrode pattern 125. The third electrode pattern 121 may be connected to a word line of a memory device. The third electrode pattern 121 may be a gate electrode of a selection transistor. The third electrode pattern 121 may extend in a channel width direction of a channel region provided under the gate insulating layer 156 to be connected to an adjacent memory cell.

A first impurity region 111, a second impurity region 112, and a third impurity region 113 may be provided in the first active region ACT1. The first impurity region 111 and the third impurity region 113 may be provided below the sidewall of the third electrode pattern 121 and the sidewall of the first electrode pattern 125, respectively. The second impurity region 112 may be provided between the first and third electrode patterns 125 and 121. The first impurity region 111 may be an impurity region connected to the bit line BL. The third impurity region 113 may be an impurity region connected to the common bit line select line BLS. The first to third impurity regions 111 to 113 may be doped with impurities of a conductivity type different from that of the second well 102. For example, the first to third impurity regions 111 to 113 may have a structure doped with a second type impurity.

A fourth impurity region 114 may be provided in the fourth active region ACT4. The fourth impurity region 114 may be an impurity region for applying an erase voltage V _EG to the second well 102. The fourth impurity region 114 may have a structure doped with impurities of the same conductivity type as that of the second well 102. For example, the second well 102 may have a structure doped with a first type impurity. The doping concentration of the fourth impurity region 114 may be higher than the doping concentration of the second well 102.

A seventh impurity region 117 may be provided in the third active region ACT3. The seventh impurity region 117 may be an impurity region for applying a voltage to the first well 101. The seventh impurity region 117 may be a region doped with impurities of the same conductivity type as the first well 101. For example, the seventh impurity region 117 may be a region doped with a second type impurity. The doping concentration of the seventh impurity region 117 may be higher than the doping concentration of the first well 101. Unlike the illustrated example, the seventh impurity region 117 may be formed in plural. For example, the seventh impurity region 117 may be further provided between the second well 102 and the third well 103.

A silicide layer (not shown) for an ohmic contact may be provided on the upper surfaces of the first to seventh impurity regions 111 to 117. For example, the silicide layer may be a cobalt silicide layer.

A second device isolation layer 141 may be provided under the second electrode pattern 126. A plurality of second device isolation layers 141 may be provided. The second active region ACT2 may include a plurality of active patterns 180 separated by the second device isolation layer 141. The plurality of active patterns 180 may be separated only under an occupied space of the second electrode pattern 126. For example, unlike the illustrated example, the plurality of active patterns 180 may be connected to each other. The plurality of active patterns 180 may have a protruding structure exposed by the second device isolation layer 141 as part of the substrate 100. The second device isolation layer 141 may be connected to the first device isolation layer 140. The thickness of the second device isolation layer 141 may be the same as the thickness of the first device isolation layer 140.

A width d2 of the second device isolation layer 141 may be smaller than a width d1 of the first device isolation layer 140 in a direction connecting the MOSFET and the MOSFET. The second electrode pattern 126 may cover at least a portion of each of the active patterns 180. The second device isolation layer 141 may have a strip shape crossing the second electrode pattern 126 under the second electrode pattern 126. The second active pattern 180 may have a strip shape spaced apart from the second device isolation layer 141. A fifth impurity region 115 and a sixth impurity region 116 may be provided at ends of the plurality of active patterns 180 exposed by the second electrode pattern 126. The fifth and sixth impurity regions 115 and 116 may be impurity regions for applying a control gate voltage V _CG to the second active region ACT2. The fifth and sixth impurity regions 115 and 116 may be regions doped with impurities of different conductivity types. For example, the fifth impurity region 115 may be a region doped with a first type impurity, and the sixth impurity region 116 may be a region doped with a second type impurity. Alternatively, the fifth impurity region 115 may be a region doped with a second type impurity and the sixth impurity region 116 may be a region doped with a first type impurity. Only one of the fifth and sixth impurity regions 115 and 116 may be provided in the fifth and sixth impurity regions 115 and 116.

As shown in FIG. 5, a dent D may be provided at an edge of the second device isolation layer 141. The dent D may be provided along sidewalls of the second device isolation layer 141. That is, the dent D may extend in a channel width direction. In this specification, the channel width direction may refer to a channel width direction of a channel region formed under the tunnel insulating layer 157. That is, the channel width direction may be a direction parallel to the J-J 'line. In addition, the channel length direction may refer to a channel length direction of a channel region formed under the tunnel insulating layer 157. That is, the channel length direction may be a direction parallel to the line II ′. The dent D may be formed by removing a portion of sidewalls of the second device isolation layer 141 during the removal process of the first insulating layer 152. The dent D may have a shape surrounding each of the plurality of active patterns 180. The dent D may also be provided at an upper edge of the first device isolation layer 140 overlapping the second electrode pattern 126.

The dent D may expose upper sidewalls of the plurality of active patterns 180. The distance t2 between the upper sidewalls of the plurality of active patterns 180 and the second electrode pattern 126 is a distance between the upper surface of the plurality of active patterns 180 and the second electrode pattern 126 ( may be less than t1). That is, the thickness of the capacitor insulating layer 158 is the thickness t2 on the upper sidewalls of the plurality of active patterns 180 exposed by the dent D, and the thickness on the top surfaces of the plurality of active patterns 180. may be less than t1).

The upper sidewalls of the plurality of active patterns 180 exposed by the dent D may have a crystal surface different from the top surfaces of the plurality of active patterns 180. For example, when the top surfaces of the plurality of active patterns 180 are {110} planes, the upper sidewalls of the plurality of active patterns 180 exposed by the dent D may not be the {110} planes. Such crystallographic differences may cause thickness differences of the capacitor insulating layers 158 formed on the plurality of active patterns 180. In addition, a difference in the thicknesses t1 and t2 may occur due to the stress concentration generated when the dent D is formed. That is, device thin film edge thinning may occur.

The capacitor insulating layer 158 may correspond to the dielectric of the MOS capacitor. Capacitance may increase because the thickness of the insulating layer of the capacitor becomes thinner in a portion of the capacitor due to the device isolation film edge thinning. The edge thinning effect may be increased by providing the second device isolation layer 141 under the second electrode pattern 126. Therefore, the control gate voltage V _CG applied to the memory cell may be reduced, and the area of the second electrode pattern 126 may be reduced, thereby reducing chip size.

6 to 15, a method of manufacturing a memory device according to the first embodiment of the present invention will be described. 6, 8, 10, 12 and 14 are views showing the manufacturing method of the moscap portion of the plan view of Figure 2, Figures 7, 9, 11, 13 and 15 are cross-sectional views along the line L-L 'of FIG. admit.

6 and 7, the first well 101 may be formed in the substrate 100. The first well 101 may have a structure doped with a second type impurity. For example, the second type impurities may be n-type impurities. The substrate 100 may have a structure doped with a first type impurity. For example, the first type impurities may be p-type impurities. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The third well 103 may be formed in the first well 101. The third well 103 may have a structure doped with first type impurities. The third well 103 may be a pocket well. For example, the formation of the third well 103 may include a step of doping the first type impurities a plurality of times at different concentrations.

A first device isolation layer 140 defining a second active region ACT2 may be formed on the substrate 100. The second active region ACT2 may be separated into a plurality of active patterns 180 by the second device isolation layer 141. The formation of the first device isolation layer 140 may include a process of forming the first trench 171. Formation of the second device isolation layer 141 may include a process of forming the second trench 172. Depths of the first trench 171 and the second trench 172 may be the same. The first and second device isolation layers 140 and 141 formed on the first and second trenches 171 and 172 may have the same thickness.

The plurality of active patterns 180 and the second device isolation layer 141 may have a strip shape extending in a channel width direction. The second device isolation layer 141 and the first device isolation layer 140 may be connected to each other. The first and second device isolation layers 140 and 141 may be simultaneously formed. That is, the process of manufacturing the first and second trenches 171 and 172 for forming the first and second device isolation layers 140 and 141 is performed simultaneously, and the insulating film forming process of filling the first and second trenches 171 and 172. May be performed simultaneously. The first and second device isolation layers 140 and 141 may be silicon oxide layers, particularly silicon oxide layers formed by a high density plasma chemical vapor deposition method having excellent gap-fill characteristics. A liner insulating layer 151 may be formed between the first and second device isolation layers 140 and 141 and the substrate 100. The liner insulating layer 151 may be an oxide film formed by a thermal oxidation process.

8 and 9, a first insulating layer 152 may be formed on the substrate 100. The first insulating layer 152 may be a buffer insulating layer for a well process. Alternatively, the first insulating film 152 may be an oxide film or the like used in a manufacturing process of a logic device. For example, in the DDI process, transistors for various uses such as low voltage (LV), high voltage (MV), and high voltage (HV) are required, and the thickness of the gate insulating layer may be different.

10 and 11, portions of the liner insulating layer 151 and the first insulating layer 152 may be removed to expose upper portions of the active patterns 180. This removal process may be performed by wet etching. During the etching process, the upper sidewalls of the first and second device isolation layers 140 and 141 may be removed together to form a dent (D). The dent D may extend in the channel width direction. The dent D may have a shape surrounding each of the plurality of active patterns 180. Unlike shown, a portion of the first insulating layer 152 may remain on the first and second device isolation layers 140 and 141.

12 and 13, a capacitor insulating layer 158 may be formed on the active patterns 180. A portion of the capacitor insulating layer 158 may be formed to overlap the liner insulating layer 151 or the second device isolation layer 141. An upper surface of the capacitor insulating layer 158 may be lower than an upper surface of the second device isolation layer 141.

Formation of the capacitor insulating layer 158 may be performed by a thermal oxidation process. As illustrated in FIG. 5, the capacitor insulating layer 158 may have a thickness on the upper sidewalls of the plurality of active patterns 180 smaller than a thickness on the top surface of the plurality of active patterns 180. The upper sidewalls of the plurality of active patterns 180 exposed by the dent D may have a crystal surface different from the top surfaces of the plurality of active patterns 180. For example, top surfaces of the plurality of active patterns 180 may be {110}, and upper sidewalls of the plurality of active patterns 180 may not be {110}. In addition, stress may be concentrated on upper sidewalls of the plurality of active patterns 180 during the etching process. Edge thinning may occur in the capacitor insulating layer 158 due to such crystallographic directional difference and stress concentration.

14 and 15, a second electrode pattern 126 may be formed on the capacitor insulating layer 158. The second electrode pattern 126 may be formed by a patterning process after forming a conductive film (not shown) on the capacitor insulating film 158. In the patterning process, an electrode connection pattern 127 connecting the second electrode pattern 126 and the first electrode pattern 125 may be formed together. The second electrode pattern 126 and the electrode connection pattern 127 may include polysilicon. The second electrode pattern 126 may cover at least a portion of each of the active patterns 180. The second electrode pattern 126 may expose a portion of the capacitor insulating layer 158 in the channel width direction. The capacitor insulating layer 158 exposed by the second electrode pattern 126 may be removed. A fifth impurity region 115 and a sixth impurity region 116 may be formed at ends of the plurality of active patterns 180 from which the capacitor insulating layer 158 is removed. The fifth and sixth impurity regions 115 and 116 may be formed under sidewalls of the second electrode pattern 126. The fifth and sixth impurity regions 115 and 116 may be impurity regions for applying a control gate voltage V _CG to the second active region ACT2. The fifth and sixth impurity regions 115 and 116 may be regions doped with impurities of another conductivity type. For example, the fifth impurity region 115 may be formed by doping with a first type impurity, and the sixth impurity region 116 may be formed by doping with a second type impurity. Alternatively, the fifth impurity region 115 may be formed by doping with a second type impurity, and the sixth impurity region 116 may be formed by doping with a first type impurity. Only one of the fifth and sixth impurity regions 115 and 116 may be formed. Silicide layers (not shown) for ohmic contacts may be provided on upper surfaces of the fifth and sixth impurity regions 115 and 116. For example, the silicide layer may be a cobalt silicide layer.

According to the first embodiment of the present invention, the capacitance of the MOS cap portion of the nonvolatile memory device may be increased by using edge thinning of the capacitor insulating film.

16 to 17, a memory device and a method of manufacturing the same according to a modification of the first embodiment of the present invention are provided. 16 is a cross-sectional view taken along the line II ′ of FIG. 2, and FIG. 17 is a cross-sectional view taken along the line J-J ′ of FIG. 2. For brevity of description, descriptions of overlapping technical features may be omitted.

The thickness t4 of the second device isolation layer 141 may be thinner than the thickness t3 of the first device isolation layer 140. The distance from the top surface of the substrate 100 to the bottom surface of the second device isolation layer 141 may be smaller than the distance from the top surface of the substrate 100 to the bottom surface of the first device isolation layer 140. The first device isolation layer 140 and the second device isolation layer 141 may be formed to have different thicknesses by a separate trench forming process. For example, after performing a plurality of trench processes having different depths, the first and second device isolation layers 140 and 141 may be formed. Alternatively, the second device isolation layer 141 may be formed by forming the first device isolation layer 140 and then performing a trench formation process at a different depth from the first device isolation layer 140. Controlling the thickness of the second device isolation layer 141 may further increase capacitance.

18 to 20, a memory device according to a second embodiment of the present invention is provided. 18 is a plan view of a memory device according to a second exemplary embodiment of the present invention, FIG. 19 is a cross-sectional view taken along the line M-M 'of FIG. 18, and FIG. 20 is a cross-sectional view taken along the line N-N' of FIG.

18 to 20, a substrate 100 is provided. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may have a structure doped with a first type impurity. For example, the first type impurities may be p-type impurities. The first well 101 may be provided on the substrate 100. The first well 101 may have a structure doped with a second type impurity. For example, the second type impurities may be n-type impurities. The substrate 100 may include a second well 102 and a third well 103 formed in the first well 101. The second well 102 and the third well 103 may be spaced apart from each other. The second and third wells 102 and 103 may have a structure doped with a first type impurity. The second and third wells 102 and 103 may be pocket wells.

A first device isolation layer 140 may be provided to define a first active region ACT1, a second active region ACT2, a third active region ACT3, and a fourth active region ACT4 of the substrate 100. Can be. The first device isolation layer 140 may be a silicon oxide layer, in particular, a silicon oxide layer formed by a high density plasma chemical vapor deposition method having excellent gap-fill characteristics. A liner insulating layer 151 may be formed between the first device isolation layer 140 and the substrate 100. The liner insulating layer 151 may be an oxide film formed by a thermal oxidation process.

The first active region ACT1 and the fourth active region ACT4 are defined inside the second well 102, and the second active region ACT2 is defined inside the third well 103. Can be defined. The third active region ACT3 may be defined outside the second and third wells 102 and 103.

A MOSFET may be provided on the first active region ACT1 including a first electrode pattern 125 and a tunnel insulating layer 157. A MOS capacitor (MOSCAP) including a second electrode pattern 126 and a capacitor insulating layer 158 may be provided on the second active region ACT2. The first and second electrode patterns 125 and 126 may be polysilicon. The tunnel insulating layer 157 and the capacitor insulating layer 158 may be thermal oxide layers. Lower surfaces of the tunnel insulating layer 157 and the capacitor insulating layer 158 may be lower than the upper surface of the substrate 100. Spacers 163 may be provided on sidewalls of the first and second electrode patterns 125 and 126. An interlayer insulating layer 161 may be provided to cover the MOSFET and the MOSFET.

An electrode connection pattern 127 extending from the first electrode pattern 125 and connected to the second electrode pattern 126 may be provided. The first and second electrode patterns 125 and 126 and the electrode connection pattern 127 may be made of the same material. The first and second electrode patterns 125 and 126 and the electrode connection pattern 127 may be a single pattern connected to each other. The first and second electrode patterns 125 and 126 and the electrode connection pattern 127 may correspond to floating gates of a memory device. The third well 103 may correspond to a control gate of the memory device. The memory device according to the first embodiment of the present invention may have a single gate structure. The conventional ypyrom has a cell having a stacked gate structure including a floating gate and a control gate as unit cells thereof. Therefore, in order to implement a stacked gate structure, a process of forming a floating gate and a control gate, respectively, is required. However, to manufacture EEPROM embedded in SOC, logic devices and EEPROM are manufactured in the same process step. Logic elements typically employ transistors of single gate structure. Therefore, the SOC fabrication process is complicated to embed EEPROM of the stacked gate structure in the SOC. The memory device according to the first embodiment of the present invention adopts a single gate structure and can be easily manufactured at the same time as the logic devices.

The gate insulating layer 156 and the third electrode pattern 121 may be provided on the first active region ACT1 to be spaced apart from the first electrode pattern 125. The third electrode pattern 121 may be connected to a word line of a memory device. The third electrode pattern 121 may be a gate electrode of a selection transistor. The third electrode pattern 121 may extend in a channel width direction of a channel region provided under the gate insulating layer 156 to be connected to an adjacent memory cell.

A first impurity region 111, a second impurity region 112, and a third impurity region 113 may be provided in the first active region ACT1. The first impurity region 111 and the third impurity region 113 may be provided below the sidewall of the third electrode pattern 121 and the sidewall of the first electrode pattern 125, respectively. The second impurity region 112 may be provided between the first and third electrode patterns 125 and 121. The first impurity region 111 may be an impurity region connected to the bit line BL. The third impurity region 113 may be an impurity region connected to the common bit line select line BLS. The first to third impurity regions 111 to 113 may be doped with impurities of a conductivity type different from that of the second well 102. For example, the first to third impurity regions 111 to 113 may have a structure doped with a second type impurity.

A fourth impurity region 114 may be provided in the fourth active region ACT4. The fourth impurity region 114 may be an impurity region for applying an erase voltage V _ERS to the second well 102. The fourth impurity region 114 may have a structure doped with impurities of the same conductivity type as that of the second well 102. For example, the second well 102 may have a structure doped with a first type impurity. The doping concentration of the fourth impurity region 114 may be higher than the doping concentration of the second well 102.

A seventh impurity region 117 may be provided in the third active region ACT3. The seventh impurity region 117 may be an impurity region for applying a voltage to the first well 101. The seventh impurity region 117 may be a region doped with impurities of the same conductivity type as the first well 101. For example, the seventh impurity region 117 may be a region doped with a second type impurity. The doping concentration of the seventh impurity region 117 may be higher than the doping concentration of the first well 101. Unlike the illustrated example, the seventh impurity region 117 may be formed in plural. For example, the seventh impurity region 117 may be further provided between the second well 102 and the third well 103.

A silicide layer (not shown) for an ohmic contact may be provided on the upper surfaces of the first to seventh impurity regions 111 to 117. For example, the silicide layer may be a cobalt silicide layer.

A second device isolation layer 142 may be provided under the second electrode pattern 126. The second active region ACT2 may include a plurality of active patterns 181 separated by the second device isolation layer 142. A plurality of second device isolation layers 142 may be provided. The plurality of active patterns 181 may be exposed by the second device isolation layer 142 as part of the substrate 100 and may protrude from the substrate 100. The second device isolation layer 142 may be connected to the first device isolation layer 140. The thickness of the second device isolation layer 142 may be the same as the thickness of the first device isolation layer 140. The width d2 of the second device isolation layer 142 may be smaller than the width d1 of the first device isolation layer 140. The second electrode pattern 126 may cover a portion of the plurality of active patterns 181. The second device isolation layer 142 may have a shape extending in a first direction and a second direction crossing the first direction. The first direction may be a channel length direction, but is not limited thereto. The second active pattern 181 may be separated by the second device isolation layer 142 in a second direction crossing the first direction and the first direction. Edge thinning may be further increased by the second device isolation layer 142. Although illustrated as a rectangle in FIG. 18 of the second active pattern 181, the present invention is not limited thereto.

A fifth impurity region 115 and a sixth impurity region 116 may be provided in a portion of the plurality of active patterns 181 exposed by the second electrode pattern 126. The fifth and sixth impurity regions 115 and 116 may be impurity regions for applying a control gate voltage V _CG to the second active region ACT2. The fifth and sixth impurity regions 115 and 116 may be regions doped with impurities of different conductivity types. For example, the fifth impurity region 115 may be a region doped with a first type impurity, and the sixth impurity region 116 may be a region doped with a second type impurity. Alternatively, the fifth impurity region 115 may be a region doped with a second type impurity and the sixth impurity region 116 may be a region doped with a first type impurity. Only one of the fifth and sixth impurity regions 115 and 116 may be provided in the fifth and sixth impurity regions 115 and 116.

According to the second embodiment of the present invention, the capacitance may be increased by increasing the boundary between the second device isolation layer and the active pattern.

21 to 28 show a method of manufacturing a memory device according to the second embodiment of the present invention. 21, 23, 25 and 27 are views illustrating a manufacturing method of the moscap portion of the plan view of FIG. 18, and FIGS. 22, 24, 26 and 28 are cross-sectional views taken along the line O 'of FIG. For brevity of description, descriptions of overlapping technical features may be omitted.

21 and 22, a first well 101 may be formed in the substrate 100. The first well 101 may have a structure doped with a second type impurity. For example, the second type impurities may be n-type impurities. The substrate 100 may have a structure doped with a first type impurity. For example, the first type impurities may be p-type impurities. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The third well 103 may be formed in the first well 101. The third well 103 may have a structure doped with first type impurities. The third well 103 may be a pocket well. For example, the formation of the third well 103 may include a step of doping the first type impurities a plurality of times at different concentrations.

A first device isolation layer 140 defining a second active region ACT2 may be formed on the substrate 100. The second active region ACT2 may include a plurality of active patterns 181 separated by the second device isolation layer 142. The formation of the first device isolation layer 140 may include a process of forming the first trench 171. The formation of the second device isolation layer 142 may include a process of forming the second trench 172. Depths of the first trench 171 and the second trench 172 may be the same. The thicknesses of the first and second device isolation layers 140 and 142 formed on the first and second trenches 171 and 172 may be the same.

The second device isolation layer 142 may have a grid shape extending in a first direction and a second direction crossing the first direction. The plurality of active patterns 181 may be separated in the first direction and the second direction by the second device isolation layer 142.

The second device isolation layer 142 and the first device isolation layer 140 may be connected to each other. The first and second device isolation layers 140 and 142 may be formed at the same time. That is, the process of manufacturing the first and second trenches 171 and 172 for forming the first and second device isolation layers 140 and 142 is performed simultaneously, and the insulating film forming process of filling the first and second trenches 171 and 172. May be performed simultaneously. The first and second device isolation layers 140 and 142 may be silicon oxide layers, particularly silicon oxide layers formed by a high density plasma chemical vapor deposition method having excellent gap-fill characteristics. A liner insulating layer 151 may be provided between the first and second device isolation layers 140 and 142 and the substrate 100. The liner insulating layer 151 may be an oxide film formed by a thermal oxidation process.

Referring to FIGS. 23 and 24, a first insulating layer 152 may be formed on the substrate 100. The first insulating layer 152 may be a buffer insulating layer for a well process. Alternatively, the first insulating film 152 may be an oxide film or the like used in a manufacturing process of a logic device. For example, in the DDI process, transistors for various uses such as low voltage (LV), high voltage (MV), and high voltage (HV) are required, and the thickness of the gate insulating layer may be different.

Referring to FIGS. 25 and 26, portions of the liner insulating layer 151 and the first insulating layer 152 may be removed to expose the upper portions of the active patterns 181. This removal process may be performed by wet etching. During the etching process, the upper sidewalls of the first and second device isolation layers 140 and 142 may be removed together to form a dent (D). The dent D may be generated along a boundary between the first and second device isolation layers 140 and 142 and the plurality of active patterns 181. For example, the dent D may have a shape surrounding each of the plurality of active patterns 181. Unlike illustrated, a portion of the first insulating layer 152 may remain on the first and second device isolation layers 140 and 142.

27 and 28, a capacitor insulating layer 158 may be formed on the active patterns 181. A portion of the capacitor insulating layer 158 may be formed to overlap the liner insulating layer 151 or the second device isolation layer 142. An upper surface of the capacitor insulating layer 158 may be lower than an upper surface of the second device isolation layer 142. Formation of the capacitor insulating layer 158 may be performed by a thermal oxidation process. The capacitor insulating layer 158 may have a thickness on upper sidewalls of the plurality of active patterns 181 to be smaller than a thickness on upper surfaces of the plurality of active patterns 181. An upper sidewall of the plurality of active patterns 181 exposed by the dent D may have a crystal surface different from the top surface of the plurality of active patterns 181. For example, upper surfaces of the plurality of active patterns 181 may be {110}, and upper sidewalls of the plurality of active patterns 181 may not be {110}. In addition, stress may be concentrated on upper sidewalls of the plurality of active patterns 181 during the etching process. Edge thinning may occur in the capacitor insulating layer 158 due to such crystallographic directional difference and stress concentration.

The second electrode pattern 126 may be formed on the capacitor insulating layer 158. The second electrode pattern 126 may be formed by a patterning process after forming a conductive film (not shown) on the capacitor insulating film 158. In the patterning process, an electrode connection pattern 127 connecting the second electrode pattern 126 and the first electrode pattern 125 may be formed together. The second electrode pattern 126 and the electrode connection pattern 127 may include polysilicon. The second electrode pattern 126 may cover a portion of the plurality of active patterns 181. The second electrode pattern 126 may expose a portion of the capacitor insulating layer 158 in the channel width direction. The capacitor insulating layer 158 exposed by the second electrode pattern 126 may be removed. A fifth impurity region 115 and a sixth impurity region 116 may be formed in the plurality of active patterns 181 exposed by the second electrode pattern 126. The fifth and sixth impurity regions 115 and 116 may be impurity regions for applying a control gate voltage V _CG to the second active region ACT2. The fifth and sixth impurity regions 115 and 116 may be regions doped with impurities of another conductivity type. For example, the fifth impurity region 115 may be formed by doping with a first type impurity, and the sixth impurity region 116 may be formed by doping with a second type impurity. Alternatively, the fifth impurity region 115 may be formed by doping with a second type impurity, and the sixth impurity region 116 may be formed by doping with a first type impurity. Only one of the fifth and sixth impurity regions 115 and 116 may be formed. Silicide layers (not shown) for ohmic contacts may be provided on upper surfaces of the fifth and sixth impurity regions 115 and 116. For example, the silicide layer may be a cobalt silicide layer.

According to the second embodiment of the present invention, the capacitance may be increased by increasing the boundary between the second device isolation layer and the active pattern.

29 through 30, a memory device and a method of manufacturing the same according to a modification of the first embodiment of the present invention are provided. FIG. 29 is a cross-sectional view taken along the line M-M 'of FIG. 16, and FIG. 30 is a cross-sectional view taken along the line N-N' of FIG. For brevity of description, descriptions of overlapping technical features may be omitted.

The thickness t4 of the second device isolation layer 142 may be thinner than the thickness t3 of the first device isolation layer 140. The distance from the top surface of the substrate 100 to the bottom surface of the second device isolation layer 142 may be smaller than the distance from the top surface of the substrate 100 to the bottom surface of the first device isolation layer 140. The first device isolation layer 140 and the second device isolation layer 142 may be formed to have different thicknesses by a separate trench forming process. For example, after performing a plurality of trenches having different depths, the first and second device isolation layers 140 and 142 may be formed. Alternatively, the second device isolation layer 142 may be formed by forming the first device isolation layer 140 and performing a trench formation process at a different depth from the first device isolation layer 140. The thickness control of the second device isolation layer 142 may further increase capacitance.

The magnetic memory devices according to the first to second embodiments described above may be implemented in various types of semiconductor package. For example, semiconductor memory devices according to an exemplary embodiment of the present invention may include package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), and plastic dual in-line package. (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline ( SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer- It can be packaged in a manner such as Level Processed Stack Package (WSP). The package in which the semiconductor memory device is mounted according to embodiments of the present invention may further include a controller and / or a logic device for controlling the semiconductor memory device.

31 is a block diagram of an electronic system including a semiconductor memory device according to example embodiments.

Referring to FIG. 31, an electronic system 1100 according to an embodiment of the present invention may include a controller 1110, an input / output device 1120, an I / O, a memory device 1130, an interface 1140, and a bus ( 1150, bus). The controller 1110, the input / output device 1120, the memory device 1130, and / or the interface 1140 may be coupled to each other through the bus 1150. The bus 1150 corresponds to a path through which data is moved.

The controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing functions similar thereto. The input / output device 1120 may include a keypad, a keyboard, and a display device. The memory device 1130 may store data and / or commands. The memory device 1130 may include at least one of the semiconductor memory devices disclosed in the first to second embodiments described above. The memory device 1130 may further include other types of semiconductor memory devices (eg, flash memory devices, DRAM devices, and / or SRAM devices). The interface 1140 may perform a function of transmitting data to or receiving data from a communication network. The interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired / wireless transceiver. Although not shown, the electronic system 1100 may further include a high speed DRAM and / or an SRAM as an operation memory for improving the operation of the controller 1110.

The electronic system 1100 may be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a digital music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

100: substrate 101,102,103: well
111-117: Impurity regions 121, 125, 126: electrode patterns
127: electrode connection pattern 140, 141, 142: device isolation layer
157: tunnel insulating film 158: capacitor insulating film

Claims (10)

A first active region and a second active region provided in the substrate and defined by the first device isolation film;
A MOSFET provided in the first active region and including a first electrode pattern;
A MOS capacitor including the second electrode pattern provided in the second active region and electrically connected to the first electrode pattern; And
And a second device isolation layer provided on the substrate under the second electrode pattern. The nonvolatile memory device of claim 1, wherein the second active region comprises a plurality of active patterns separated by the second device isolation layer. 3. The nonvolatile memory device of claim 2, wherein a distance between an upper sidewall of the plurality of active patterns and the second electrode pattern is smaller than a distance between an upper surface of the plurality of active patterns and the second electrode pattern. 3. The MOS capacitor of claim 2, wherein the MOS capacitor comprises a capacitor insulating film between the second active region and the second electrode pattern, wherein the capacitor insulating film has a thickness on upper sidewalls of the plurality of active patterns. Non-volatile memory device less than the thickness on the upper surface. The nonvolatile memory device of claim 2, further comprising a dent provided at an edge of an upper portion of the device isolation layer and exposing upper sidewalls of the plurality of active patterns. The nonvolatile memory device of claim 2, wherein the second device isolation layer has a strip shape intersecting the second electrode pattern under the second electrode pattern. The nonvolatile memory device of claim 2, wherein the second device isolation layer extends in a first direction and a second direction crossing the first direction. The nonvolatile memory device of claim 1, wherein the second device isolation layer is connected to the first device isolation layer. The nonvolatile memory device of claim 1, wherein a width of the second device isolation layer in a direction connecting the MOSFET and the MOS capacitor is smaller than a width of the first device isolation layer. The nonvolatile memory device of claim 1, wherein a thickness of the second device isolation layer is thinner than a thickness of the first device isolation layer.

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