KR101668798B1 - Display apparatus and method of driving the same - Google Patents

Abstract

In the display device, the display panel displays an image, and the frame rate converter divides the image signal input from the outside into a first image frame for the left eye and a second image frame for the right eye, And generates first and second continuous intermediate image frames. The timing controller converts each of the first and second image frames into first and second compensation frames, and outputs the first compensation frame, the first intermediate image frame, the second compensation frame, and the second intermediate image frame to the data driver in the order of the first compensation frame, to provide. The data driver converts each of the first and second compensation frames into a left eye data voltage and a right eye data voltage, converts the first and second intermediate image frames into a predetermined black data voltage, and provides the same to the display panel.

Description

DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display apparatus and a driving method thereof, and more particularly to a display apparatus and a driving method thereof that can improve display quality and reduce the number of parts.

The stereoscopic image display device is a device for displaying the left eye image and the right eye image having binocular disparity separately in the left and right eyes of an observer. The observer sees the left eye and right eye images through both eyes and fuses these images in the brain to acknowledge the stereoscopic effect.

The stereoscopic image display apparatus alternately displays the left eye image and the right eye image on the display panel to realize the stereoscopic image. When the image displayed on the display panel is switched from the left eye image to the right eye image or conversely from the right eye image to the left eye image, the quality of the stereoscopic image is deteriorated due to the mixture of the left eye image and the right eye image due to the scanning method of the display panel.

In order to increase the response speed of the liquid crystal, the stereoscopic image display device employs a driving method of correcting the current image with a correction voltage considering the target voltage of the current image and the driving voltage of the previous image. The stereoscopic image display apparatus requires a memory for storing the driving voltage of the previous image of the left eye image and the right eye image.

A problem to be solved by the present invention is to provide a display device for reducing the number of components and improving display quality.

Another object of the present invention is to provide a method for driving the display device.

In order to solve the above problems, a display device according to the present invention includes a display panel for displaying an image, a frame rate converter, a timing controller, and a data driver.

Wherein the frame rate converter divides a video signal input from the outside into a first image frame for the left eye and a second image frame for the right eye and outputs the first and second intermediate frames to the first image frame and the second image frame, Frame to generate a 4x-speed video signal. Wherein the timing controller compensates the first and second video frames with first and second compensating frames, respectively, to generate the first compensating frame, the first intermediate frame, the second compensating frame, Respectively. Wherein the data driver converts the first and second compensation frames received from the timing controller into a left eye data voltage and a right eye data voltage respectively and outputs the first and second intermediate image frames in response to a black insertion control signal, Converted into a black data voltage corresponding to the black gradation and provided to the display panel.

In order to solve the above-mentioned problems, a driving method of a display apparatus according to the present invention is as follows. The display device separates the video signal into a first image frame for the left eye and a second image frame for the right eye, and outputs the first intermediate image frame and the second intermediate image frame, which are continuous to the first image frame and the second image frame, . Next, the first image frame is compensated with a first compensation frame, and the second image frame is converted into a second compensation frame. Thereafter, the first and second compensation frames are respectively converted into a left eye data voltage and a right eye data voltage, and in response to the black insertion control signal, the first intermediate image frame and the second intermediate image frame correspond to a predetermined black gradation Into a black data voltage. The left data voltage, the black data voltage, the right data voltage, and the black data voltage.

In order to solve the above-mentioned problems, a driving method of a display apparatus according to the present invention is as follows. Wherein the display device separates the image signal into a first image frame for the left eye and a second image frame for the right eye and outputs the first intermediate image frame and the second intermediate image frame, which are respectively continuous to the first image frame and the second image frame, . Next, the first image frame is converted into a left eye data voltage, and the second image frame is converted into a right eye data voltage. Thereafter, in response to the black insertion control signal, a black data voltage corresponding to a predetermined black gradation is inserted between the left eye data voltage and the right eye data voltage. The left data voltage, the black data voltage, and the right data voltage are successively received to display an image.

As described above, according to the present embodiment, the display device generates an intermediate image frame continuous with each of the left eye image frame and the right eye image frame when implementing a three-dimensional image, and converts the intermediate image frame into a black data voltage Thereby preventing a mixture of the left eye image and the right eye image.

In addition, the number of frame memories required for DCC (Dynamic Capacitance Compensation) driving can be reduced. Therefore, the manufacturing cost of the display device can be reduced.

1 is a block diagram showing a display device according to an embodiment of the present invention.
2 is a block diagram of the frame rate converter shown in Fig.
3 is a block diagram of the timing controller shown in Fig.
4 is a block diagram of the data driver shown in FIG.
5 is a diagram illustrating a resistor string included in the D / A converter shown in FIG.
6 is a circuit diagram showing the black data selector shown in FIG.
7 is a block diagram of a data driver according to another embodiment of the present invention.
8 is a waveform diagram for explaining the driving operation of the display device with reference to Figs. 1 and 7. Fig.
9 is a block diagram of a display device according to another embodiment of the present invention.
10 is a flowchart illustrating a three-dimensional image display method in the display apparatus shown in FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. Each drawing has been partially or exaggerated for clarity. It should be noted that, in adding reference numerals to the constituent elements of the respective drawings, the same constituent elements are shown to have the same reference numerals as possible even if they are displayed on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 is a block diagram showing a display device according to an embodiment of the present invention.

1, a display device 50 includes a display panel 100 for displaying an image, a gate driver 120 for driving the display panel 100, a data driver 140, a data driver 140, A connected gamma voltage generator 150 and a timing controller 160 for controlling the gate driver 120 and the data driver 140. The display device 50 may further include a repeater 170 and a frame rate converter 180, a frame memory 310, a 3D timing converter 330, and shutter glasses 300.

The repeater 170 receives a two-dimensional image signal DATA from a video system (not shown). The repeater 170 may receive the two-dimensional image signal DATA in a low voltage differential signaling (LVDS) manner. The lifter 170 transmits the received two-dimensional video signal DATA to the frame rate converter 180.

The frame rate converter 180 receives the two-dimensional image signal DATA from the repeater 170, converts the two-dimensional image signal DATA into a three-dimensional image signal, And converts the frame rate according to the frame rate of the display panel 100. [ For example, the frame rate converter 180 converts the two-dimensional image signal DATA having a frequency of 60 Hz into a left eye image frame (hereinafter referred to as a left eye image frame L and a right eye image frame (R), and converts the 3-dimensional image signal into a 4x image signal (LLRR) having a frequency of 240 Hz. In this case, the frame rate converter 180 converts the 3- The frame rate converter 180 may have a driving frequency other than 240 Hz (e.g., 120 Hz, 360 Hz, etc.).

The two-dimensional image signal DATA having a frequency of 60 Hz includes a plurality of frames, and the output time of each frame may be 1/60 second. On the other hand, the quad-speed video signal LLRR includes a plurality of frames, and the output time of each frame may be 1/240 seconds.

In order to output the 4x-speed video signal LLRR, the frame rate converter 180 divides the video signal received from the repeater 170 into a left eye image frame L and a right eye image frame R Speed video signal. The frame rate converter 180 then generates a first intermediate image frame L and a second intermediate image frame R that are continuous with the left eye image frame L and the right eye image frame R, respectively. The first intermediate image frame L may have the same value as the left eye image frame L and the second intermediate image frame R may have the same value as the right eye image frame R. [ Accordingly, the frame rate converter 180 can convert the 2x-speed video signal into the 4x-speed video signal LLRR.

Also, although FIG. 1 shows one frame rate converter 180, the display device 50 may include two frame rate converters. As described above, when the display device 50 includes the two frame rate converters, the first frame rate converter receives the video signal (the video signal) corresponding to the entire display panel 100 from the repeater 170 DATA, and output the left video signal corresponding to the left area based on the center line of the display panel 100. [ The second frame rate converter receives the video signal DATA corresponding to the whole of the display panel 100 from the repeater 170 and outputs the right video corresponding to the right area on the basis of the center line of the display panel 100 A signal can be output.

The timing controller 160 receives the 4x image signal LLRR from the frame rate converter 180 and receives the control signal CONT1 from the repeater 170. [ The timing controller 160 compensates the quad-speed image signal LRRR through a data compensation method for compensating the charge rate of each pixel to output a quad rate compensation video signal L'LR`R. Specifically, the timing controller 160 compensates the left eye image frame L to output a left eye compensation frame L ', and compensates the right eye image frame R to output a right eye compensation frame R' . Also, the timing controller 160 outputs the first and second intermediate image frames L and R as they are without applying the data compensation method.

The control signal CONT1 received by the timing controller 160 may include a main clock signal MCLK, a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, a data enable signal DE, . The timing controller 160 generates a gate control signal CONT2 for controlling the operation of the gate driver 120 using the control signal CONT1 and a data control signal CONT2 for controlling the operation of the data driver 140. [ And provides the generated gate control signal CONT2 and the data control signal CONT3 to the gate driver 120 and the data driver 140, respectively.

Meanwhile, the timing controller 160 receives the 3D enable signal 3D_EN and generates a gamma selection control signal CONT4 in response to the 3D enable signal 3D_EN. The gamma selection control signal CONT4 is supplied to the gamma voltage generator 150. [ The gamma voltage generator 150 outputs three-dimensional gamma reference voltages VGMA1 to VGMA18 in response to the high-level gamma selection control signal CONT4. Although not shown, when the two-dimensional enable signal 2D_EN is supplied to the timing controller 160, the gamma voltage generator 150 generates the gamma voltage control signal CONT3 in response to the gamma selection control signal CONT4 at the low level, Dimensional gamma reference voltages having different magnitudes from the gamma reference voltages VGMA1 to VGMA18 of the display panel 100. The display panel 100 includes a plurality of gate lines GL1 to GLn receiving a gate voltage, And a plurality of data lines DL1 to DLm for receiving data voltages. A plurality of pixel regions are defined in the display panel 100 in the form of a matrix by the gate lines GL1 to GLn and the data lines DL1 to DLm and pixels 103 are provided in each pixel region. The pixel 103 includes a thin film transistor 105, a liquid crystal capacitor 107, and a storage capacitor 109.

The thin film transistor 105 includes a gate electrode connected to the first gate line GL1, a source electrode connected to the first data line DL1, and a drain electrode connected to the liquid crystal capacitor 107 and the storage capacitor 109 do. The liquid crystal capacitor 107 and the storage capacitor 109 are connected in parallel to the drain electrode.

Although not shown in the drawing, the display panel 100 includes a first display substrate (not shown), a second display substrate (not shown) facing the first display substrate, and a second display substrate And a liquid crystal layer (not shown) interposed therebetween.

A pixel electrode (not shown) which is a first electrode of the gate lines GL1 to GLn, the data lines DL1 to DLm, the thin film transistor 105 and the liquid crystal capacitor 107 is formed on the first display substrate. . The thin film transistor 105 applies the data voltage to the pixel electrode in response to the gate voltage.

On the other hand, a common electrode (not shown) which is a second electrode of the liquid crystal capacitor 107 is formed on the second display substrate, and a reference voltage is applied to the common electrode. The liquid crystal layer interposed between the pixel electrode and the common electrode functions as a dielectric. The liquid crystal capacitor 107 is charged with a voltage corresponding to a potential difference between the data voltage and the reference voltage.

The gate driver 120 is electrically connected to the gate lines GL1 to GLn provided in the display panel 100 to provide the gate voltages to the gate lines GL1 to GLn. Specifically, the gate driver 120 applies a gate-on voltage VON and a gate-on voltage VON to drive the gate lines GL1 to GLn based on the gate control signal CONT2 received from the timing controller 160. [ Off voltage VOFF, and sequentially outputs the generated gate signals to the gate lines GL1 to GLn. The gate control signal CONT2 determines a vertical start signal STV for starting the operation of the gate driver 120, a gate clock signal GCLK for determining an output timing of the gate voltage, An output enable signal OE, and the like.

The data driver 140 receives the quad rate compensation data L`LR`R from the timing controller 260 and outputs the left eye compensation frame L` and the left eye compensation frame L` in response to the data control signal CONT3. And converts the right eye compensation frame R 'into a left eye data voltage and a right eye data voltage, respectively, and supplies them to the display panel 100. In particular, the data driver 140 drives the left eye compensation frame L 'and the right eye compensation frame R' based on the three-dimensional gamma reference voltages VGMA1 to VGMA18 provided from the gamma voltage generator 190. [ ) To the left eye data voltage and the right eye data voltage, respectively. The data control signal CONT3 includes a horizontal start signal STH for starting the operation of the data driver 140, an inverted signal POL for controlling the polarity of the left and right eye data voltages, A load signal TP for determining the output timing of the left eye and right eye data voltages, and the like.

In response to the black insertion control signal BIC, the data driver 140 sets the first and second intermediate image frames L and R among the 4x speed compensation data L ' Converted into a black data voltage and provided to the display panel 100. [

The data driver 140 is electrically connected to the data lines DL1 to DLm included in the display panel 100 to generate the left data voltage, the black data voltage, the right data voltage, To the data lines DL1 to DLm in this order.

The display device 50 includes a frame memory 310 connected to the timing controller 160 to store a previous image frame and a three-dimensional (3D) image display unit 150 for providing the black insertion control signal BIC to the data driver 140. [ ) Timing converter 330 as shown in FIG.

The frame memory 310 sequentially stores frames of the 4x-speed video signal (LLRR) provided to the timing controller 160. For example, when the right eye image frame R is provided to the timing controller 160, the frame memory 310 stores the first intermediate image frame L, which is a previous frame, and the timing controller 160 And provides the stored first intermediate image frame L to the timing controller 160 in response to a request from the timing controller 160. The timing controller 160 may convert the right eye image frame R into the right eye image frame R 'based on the data of the first intermediate image frame L. [

The 3D timing converter 330 receives the 3D synchronization signal 3D_Sync from the video system and outputs the black insertion control signal BIC to the data driver 140 in response to the 3D synchronization signal 3D_Sync to provide. In addition, the 3D timing converter 330 provides an inversion control signal PCS to the timing controller 160. The timing controller 160 changes the period of the inversion signal POL that controls the polarity of the left eye data voltage and the right eye data voltage in response to the inversion control signal PCS, To the data driver 140. For example, when a two-dimensional synchronizing signal is generated, the timing controller 160 changes the inversion period of the inverting signal POL to one frame, and when the three-dimensional synchronizing signal 3D_Sync is generated, The period can be changed to two frames.

The display device (50) further includes shutter glasses (300) for observing an image displayed on the display panel (100).

The shutter glasses 300 include a left eye shutter (not shown) and a right eye shutter (not shown). The shutter glasses 300 receive the 3D synchronization signal 3D_Sync and sequentially drive the left eye shutter and the right eye shutter in response to the 3D synchronization signal 3D_Sync. When a user wears the shutter glasses 300, a three-dimensional image displayed on the display panel 100 can be observed through the left and right eye shutters sequentially driven. FIG. Lt; / RTI > is a block diagram of a conventional frame rate converter.

Referring to FIG. 2, the frame rate converter 180 may include a data separator 181, a scaler 182, and an intermediate image inserter 183.

The data separator 181 receives the 2-dimensional image signal DATA from the repeater 210 and outputs the 2-dimensional image signal DATA to the left eye image signal And outputs the 2x-speed image signal LR by separating the frame L and the right eye image frame R. [ The data separator 220 provides the separated left and right eye image frames (L, R) to the scaler 182.

The scaler 182 scales the left and right eye images to match the resolutions of the left eye image frame L and the right eye image frame R received from the data separator 181 to the resolution of the display panel 100. [ The format of the video frames L and R is converted.

 The intermediate image inserting unit 183 inserts the same value as the Nth left eye image frame L between the Nth left eye image frame L and the Nth right eye image frame R received from the scaler 183 The first intermediate image frame L is generated. The intermediate image inserting unit 183 inserts the Nth right eye image frame R between the Nth right eye image frame R and the (N + 1) th left eye image frame L received from the scaler 183, The second intermediate image frame R having the same value as the first intermediate image frame R is generated.

Accordingly, the intermediate image inserting unit 183 sequentially outputs the Nth left eye image frame L, the first intermediate image frame L, the Nth right eye image frame R, and the second intermediate image frame R Speed video signal LR to the 4x-speed video signal LLRR.

Although not shown, when the frame rate converter 180 receives a two-dimensional image signal of 60 Hz, the frame rate converter 180 converts the two-dimensional image signal of 60 Hz into a left eye image frame and a right eye image frame It is possible to change only the frame rate without separating. That is, the frame rate converter 180 can convert a 2-dimensional image signal of 60 Hz into a 4-times 2-dimensional image signal of 240 Hz and output it.

3 is a block diagram of the timing controller shown in Fig.

Referring to FIG. 3, the timing controller 160 includes a data compensation block 162, a first lookup table (3D_LUT), and a second lookup table (2D_LUT). A correction value for 3D is stored in the first lookup table (3D_LUT), and a correction value for 2D is stored in the second lookup table (2D_LUT). Accordingly, the data compensation block 162 refers to the first lookup table (3D_LUT) in the 3D mode and refers to the second lookup table (2D_LUT) in the 2D mode.

3, when the data compensation block 162 receives the 4x-speed video signal LLRR, the data compensation block 162 refers to the first lookup table (3D_LUT) And compensates the quad-speed video signal LLRR with the quad-speed compensation signal L'LR`R.

The frame memory 310 sequentially stores frames of the 4x-speed video signal (LLRR). For example, if the left eye image frame L is provided to the data compensation block 162, the second intermediate image frame R of the previous frame is stored in the frame memory 310, The second intermediate image frame R of the previous frame is provided to the data compensation block 162 in response to a request from the data compression block 162. The data compensation block 162 may convert the left eye image frame L into the left eye image frame L 'based on the data of the second intermediate image frame R of the previous frame.

When the right-eye image frame R is provided to the data compensation block 162, the first intermediate image frame L, which is a previous frame, is stored in the frame memory 310, And provides the first intermediate image frame (L) to the data compensation block (162) in response to a request of the first intermediate image frame (162). The data compensation block 162 may convert the right eye image frame R into the right eye compensation frame R 'based on the data of the first intermediate image frame L. [

When the first and second intermediate image frames L and R are provided to the data compensation block 162, the data compensation block 162 generates the first and second intermediate image frames L and R, Without directly compensating the data. Since the first and second intermediate image frames L and R are not substantially supplied to the liquid crystal display panel, there is no need to perform data compensation. Accordingly, the timing controller 160 generates 4 (4) frames in the order of the left eye compensation frame L ', the first intermediate image frame L, the right eye compensation frame R' It is possible to output the double speed compensation signal L'LR`R.

As described above, the first intermediate image frame L has the same value as the left eye image frame L, and the second intermediate image frame R has the same value as the right eye image frame R . Accordingly, in compensating the right eye image frame R, the data compensation block 162 may refer to the value of the immediately preceding frame, i.e., the first intermediate image frame L. [ Also, in compensating the left eye image frame L, the data compensation block 162 may refer to a value of a previous frame, that is, the second intermediate image frame R. [

In the case where the first intermediate image frame L has the same value as the left eye image frame L and the second intermediate image frame R has the same value as the right eye image frame R, For compensation, the frame memory 310 may store only data corresponding to one frame. However, if the first and second intermediate image frames L and R have different values from the left and right eye image frames L and R, respectively, the left and right eye image frames L and R may be compensated The frame memory 310 must store two frames of data, so that the total number of frame memories can be increased. Accordingly, when the first and second intermediate image frames L and R have the same value as the left and right eye image frames L and R, respectively, the 4x image signal LLRR is converted into the data It is possible to prevent the number of the frame memories 310 from increasing.

4 is a block diagram of the data driver shown in FIG. 1, and FIG. 5 is a diagram illustrating a resistor string included in the D / A converter shown in FIG. 4. Referring to FIG. 4, A register 142, a latch 143, a D / A converter 144, a black data selector 145, and an output buffer 146.

The shift register 142 includes a plurality of stages (not shown) connected in a connected manner, and each stage is provided with a horizontal clock signal CKH, and a horizontal start signal STH is applied to a first stage among the plurality of stages . When the operation of the first stage is started by the horizontal start signal STH, the plurality of stages sequentially output control signals in response to the horizontal clock signal CKH.

The latch 143 receives the quad-speed compensation signal L'LR`R from the timing controller 160 and outputs the quad-speed compensation signal L'LR`R in response to the control signal sequentially received from the plurality of stages L ' LR ' R). The latch 143 provides the latched data of one line to the D / A converter 144.

The D / A converter 144 receives the data supplied from the latch 143 and converts the received data into a data voltage based on the gamma reference voltages VGMA1 to VGMA18.

Referring to FIG. 5, the D / A converter 144 may include a resistor string 144a for converting the eighteen gamma reference voltages VGMA1 to VGMA18 into 2 * ^2k gradation voltages. In one example of the present invention, k may be defined as the number of bits of the data. That is, when the data is composed of 8 bits, the resistance string 144a can be converted into 512 gradation voltages.

The resistor string 144a includes a positive resistor string 144b and a negative resistor string 144c to polarize the gradation voltages. The positive polarity resistance string 144b generates 256 positive polarity gradation voltages V1 to V256 based on the first to ninth gamma reference voltages VGMA1 to VGMA9 of the gamma reference voltages VGMA1 to VGMA18. can do. Conversely, the negative polarity resistance string 144c outputs 256 negative polarity gradation voltages (-V1 to VGMA18) based on the 10th to 18th gamma reference voltages (VGMA10 to VGMA18) of the gamma reference voltages VGMA1 to VGMA18. V256). In an embodiment of the present invention, the magnitudes of the gamma reference voltages VGMA1 to VGMA18 may be reduced in the order of the first gamma reference voltage VGMA1 to the eighteenth gamma reference voltage VGMA18.

The positive polarity gradation voltages V1 to V256 have a positive polarity based on a predetermined reference voltage Vcom and the negative polarity gradation voltages -V1 to -V256 correspond to the common voltage Vcom (Vcom). The positive gradation voltages V1 to V256 have a higher gradation (i.e., white gradation) as they are away from the common voltage Vcom, and the lower the gradation voltages V1 to V256 as the common voltage Vcom is, (I.e., black gradation). Similarly, the negative polarity gradation voltages (-V1 to -V256) have a higher gradation (i.e., white gradation) as they are away from the common voltage Vcom, and a lower gradation , Black gradation).

The D / A converter 144 selects either the positive polarity resistor string 144b or the negative polarity resistor string 144c based on the inverted signal POL and outputs 256 Selects a gradation voltage corresponding to the data among the gradation voltages, and outputs the selected gradation voltage as the data voltage. The output data voltage is supplied to the black data selector 145.

The black data selector 145 supplies the data voltage supplied from the D / A converter 144 to the output buffer 146 in response to the black insertion control signal BIC, And provides the voltage V _B to the output buffer 146. In an embodiment of the present invention, the black data voltage V _B may be a voltage corresponding to the common voltage Vcom.

The output buffer 145 includes a plurality of operational amplifiers (not shown), and temporarily stores any one of the data voltage and the black data voltage V _B output from the black data selector 145 And outputs it at the same time point in response to the load signal TP.

6 is a circuit diagram showing the black data selector shown in FIG.

6, the black data selector 145 includes a plurality of first switching transistors TR1 and a black insertion control signal BIC for switching the data voltage in response to the black insertion control signal BIC, And a plurality of second switching transistors TR2 for providing the black data voltage (V _B ) to the output buffer 146 instead of the data voltage in response to the data voltage.

In detail, each of the first switching transistors TR1 includes a first electrode connected to a corresponding output terminal of the D / A converter 144, a second electrode receiving the black insertion control signal BIC, Lt; RTI ID = 0.0 > 146 < / RTI > In one embodiment of the present invention, each of the first switching transistors TR1 may be a P-type transistor.

Each of the second switching transistors TR2 includes a first electrode for receiving the black data voltage V _B , a second electrode for receiving the black insertion control signal BIC, And a third electrode coupled to a corresponding input. In one embodiment of the present invention, each of the second switching transistors TR2 may be an N-type transistor.

When the black insertion control signal BIC has a low state, the first switching transistors TR1 are turned on and the second switching transistors TR2 are turned off. Accordingly, the data voltages output from the D / A converter 144 may be transmitted to the output buffer 146 through the black data selector 145. Conversely, if the black insertion control signal BIC has a high state, the first switching transistors TR1 are turned off and the second switching transistors TR2 are turned on. Therefore, the data voltages output from the D / A converter 144 can not pass through the first switching transistors TR1. The black data voltage V _B passing through the second switching transistors TR2 may be provided at an input terminal of the output buffer 146. [

Accordingly, the black data selector 145 may select the first and second intermediate image frames L and R in response to the black insertion control signal BIC in the high state, The data voltage converted from the intermediate image frames L and R is not selected but instead the black data voltage V _B is output. In addition, the black data selection unit 145 may output the converted data (L ') from the left eye compensation frame L' in a period in which the left eye compensation frame L 'is provided in response to the black insertion control signal BIC in a low state And selects and outputs the converted data voltage from the right eye compensation frame R 'in a section where the right eye compensation frame R' is provided.

7 is a block diagram of a data driver according to another embodiment of the present invention. 7, the same constituent elements as those shown in FIG. 4 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

7, the data driver 149 according to another embodiment of the present invention includes a shift register 142, a latch 143, a D / A converter 144, a logic controller 147, a black data selector 148 and an output buffer 146.

The logic controller 147 generates a first control signal CT1 and a second control signal CT2 based on the inverted signal POL and the black insertion control signal BIC, And provides the control signals CT1 and CT2 to the black data selector 148. [

The black data selector 148 receives the first and second control signals CT1 and CT2 and outputs the gamma reference voltages VGMA1 to VGMA18 output from the gamma voltage generator 150, And a tenth gamma reference voltage (VGMA9, VGMA10). Accordingly, the black data selector 148 outputs either the ninth and tenth gamma reference voltages VGMA9 and VGMA10 as the black data voltages in response to the first and second control signals CT1 and CT2 do.

Specifically, when the first control signal CT1 is in the high state and the second control signal CT2 is in the low state, the common voltage Vcom has a positive polarity with respect to the common voltage Vcom, And outputs the ninth gamma reference voltage VGMA9 representing the black gradation closest thereto as the black data voltage of positive polarity. On the other hand, when the first control signal CT1 is in a low state and the second control signal CT2 is in a high state, the first control signal CT1 has a negative polarity with respect to the common voltage Vcom, And outputs the tenth gamma reference voltage (VGMA10) showing the black gradation closest to the black data voltage having the negative polarity.

8 is a waveform diagram for explaining the driving operation of the display device with reference to Figs. 1 and 7. Fig.

8, the frame rate converter 180 receives a two-dimensional image signal from the repeater 170 and outputs the two-dimensional image signal DATA in three-dimensional (3D) mode in response to the three- Into a video signal LLRR. Specifically, the frame rate converter 180 separates the two-dimensional image signal DATA into a left eye image frame L and a right eye image frame L, and outputs the left eye image frame L and the right eye image frame L, And outputs the 4x image signal LLRR as the 3-dimensional image signal.

8, when the three-dimensional enable signal in the (N-3) -th frame period is switched to the high state, the frame rate converter 180 converts the two-dimensional video signal DATA into the three- 2-th frame and the (N-1) -th frame interval as the buffer interval to output the 3-dimensional image signal LLRR from the N-th frame period. The left eye image frame L is output during the Nth frame period and the first intermediate image frame L having the same value as the left eye image frame L during the (N + 1) ), The right eye image frame R is output during the (N + 2) -th frame period, and the second intermediate image frame R having the same value as the right eye image frame R during the (N + Is output.

The 3D timing converter 330 provides the inversion control signal PCS to the timing controller 160 in response to the 3D synchronization signal 3D_Sync provided from the video system. In one embodiment of the present invention, the 3D image sync signal 3D_Sync maintains a high level during two frame periods corresponding to the left eye image frame and the first intermediate image frame L, And can maintain a low level for two frames corresponding to the video frame RR.

The timing controller 160 controls the period of the inversion signal POL in response to the inversion control signal PCS. Specifically, the inversion signal POL has an inversion period of one frame during the (N-3) th frame, the (N-2) th frame and the (N-1) th frame period. Thereafter, when the inversion control signal PCS based on the 3D synchronization signal 3D_Sync is supplied to the timing controller 160, the period of the inversion signal POL increases to two frames. That is, the inversion signal POL from the Nth frame period in which the 3D synchronization signal 3D_Sync is generated has an inversion period of two frames.

In addition, the 3D timing converter 330 may convert the first and second intermediate image frames L and R into the black data voltage V L in response to the three-dimensional image synchronization signal 3D_Sync maintained at a high level for two frame periods, And provides the data driver 140 with the black insertion control signal BIC of high level during the (N + 1) < th >

The data driver 140 may supply a positive data voltage VDATA corresponding to the left eye image frame to the data lines VD in response to the left eye image frame L and the inversion signal POL during the Nth frame period, DL1 to DLm. During the (N + 1) -th frame period, the data driver 140 generates first and second control signals CT1 and CT2 based on the black insertion control signal BIC and the inverted signal POL, , The first intermediate image frame is converted into a black data voltage (+ B-DATA) having a positive polarity and provided to the data lines DL1 to DLm in response to the first intermediate image frame.

The data driver 140 generates a negative data voltage VDATA corresponding to the right eye image frame R in response to the right eye image frame R and the inversion signal POL during the (N + 2) To the data lines DL1 to DLm. During the (N + 3) -th frame period, the data driver 140 responds to the first and second control signals CT1 and CT2 based on the black insertion control signal BIC and the inverted signal POL, Converts the second intermediate image frame to a negative black data voltage (-B-DATA), and provides it to the data lines DL1 to DLm.

As described above, according to the present embodiment, when implementing a three-dimensional image, the display device inserts an intermediate image frame between the left eye image frame and the right eye image frame, converts the intermediate image frame into the black data voltage, It is possible to prevent the phenomenon that the image and the right eye image are mixed.

9 is a block diagram of a display device according to another embodiment of the present invention. Note that, among the components shown in FIG. 9, the components shown in FIG. 1 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

9, a display device 55 according to another embodiment of the present invention includes a display panel 100 for displaying an image, a gate driver 120 for driving the display panel 100, a data driver 140, A gamma voltage generator 150 connected to the data driver 140 and a timing controller 190 for controlling the gate driver 120 and the data driver 140. The display device 55 may further include a repeater 170 and a frame rate converter 180.

The display device 55 of Fig. 9 is similar to the display device 50 of Fig. 1 except that the timing controller 190 incorporates the 3D timing converter 330 and the frame memory 310 shown in Fig.

The timing controller 190 receives the 4x image signal LLRR from the frame rate converter 180 and receives the control signal CONT1 from the repeater 170. [ The timing controller 160 compensates the quad-speed image signal LRRR through a data compensation method for compensating the charge rate of each pixel to output a quad rate compensation video signal L'LR`R. Specifically, the timing controller 160 compensates the left eye image frame L to output a left eye compensation frame L ', and compensates the right eye image frame R to output a right eye compensation frame R' . Also, the timing controller 160 outputs the first and second intermediate image frames L and R as they are without applying the data compensation method.

The timing controller 190 may include a frame memory for sequentially storing the frames of the 4x-speed video signal (LLRR) in order to compensate the data. The timing controller 190 receives the 3D synchronization signal 3D_Sync from the video system and outputs the black insertion control signal BIC to the data driver 140 in response to the 3D synchronization signal 3D_Sync. Can be provided.

By thus processing the functions of the 3D timing converter 330 and the frame memory 310 shown in FIG. 1 in the timing controller 190, it is possible to reduce the total number of components provided in the display device 55.

10 is a flowchart illustrating a three-dimensional image display method in the display apparatus shown in FIG.

Referring to FIGS. 1 and 10, the frame rate converter 180 receives a two-dimensional image signal DATA from an external video system (S11).

The frame rate converter 180 separates the two-dimensional image signal DATA into a left eye image frame L and a right eye image frame R through the data separator 181 (shown in FIG. 2) (S21 ).

The frame rate converter 180 receives the left eye image frame L and the right eye image frame R from the intermediate image inserting unit 183 (shown in FIG. 2) The first intermediate image frame L and the second intermediate image frame R that are continuous to each of the right eye image frames R are generated (S31). The first intermediate image frame L may have the same value as the left eye image frame L and the second intermediate image frame R may have the same value as the right eye image frame R. [

The frame rate converter 180 converts the 4x image signal including the left eye image frame L, the first intermediate image frame L, the right eye image frame R and the second intermediate image frame R, (LLRR) to the timing controller 160.

The timing controller 160 compensates the quad-speed image signal LRRR through a data compensation method for compensating the charge rate of each pixel to output a quad rate compensation video signal L'LR`R. Specifically, the timing controller 160 compensates the left eye image frame L to output a left eye compensation frame L ', and compensates the right eye image frame R to output a right eye compensation frame R' (S41). Also, the timing controller 160 outputs the first and second intermediate image frames L and R as they are without applying the data compensation method. Accordingly, the timing controller 160 provides the quad-speed-compensated video signal L 'LR' R to the data driver 140.

The data driver 140 converts the left eye compensation frame L into a left eye data voltage and converts the right eye compensation frame R into a right eye data voltage. In addition, the data driver 140 may supply the first intermediate image frame L and the second intermediate image frame R in response to the black image control signal BIC provided from the 3D timing converter 330 Into a predetermined black data voltage (S51).

The data driver 140 sequentially provides the left eye data voltage, the black data voltage, the right eye data voltage, and the black data voltage to the display panel 100 (S61). Accordingly, the display panel 100 sequentially receives the left eye data voltage, the black data voltage, the right eye data voltage, and the black data voltage to display a three-dimensional image.

As described above, according to the present embodiment, the three-dimensional image display method includes inserting first and second intermediate image frames continuous to each of a left eye image frame and a right eye image frame, It is possible to prevent the phenomenon that the left eye image and the right eye image are mixed together by converting them into data voltages and displaying them.

The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: display panel 120: gate driver
140: Data driver 160: Timing controller
170: Repeater 180: Frame rate converter
190: gamma voltage generator 300: shutter glasses
310: frame memory 330: frame conversion control unit

Claims (23)

A display panel for displaying an image;
Separating a video signal input from the outside into a first image frame for the left eye and a second image frame for the right eye and generating first and second intermediate image frames respectively continuous to the first image frame and the second image frame, A frame rate conversion unit for converting a video signal into a quadruple speed video signal;
Generating first and second compensation frames by compensating the first and second image frames, and sequentially generating the first compensation frame, the first intermediate image frame, the second compensation frame, and the second intermediate image frame sequentially A timing controller for outputting; And
Converts the first and second compensation frames received from the timing controller into a left eye data voltage and a right eye data voltage respectively and outputs the first and second intermediate image frames in response to a predetermined black gradation And a data driver for converting the data voltage into a black data voltage and providing the data voltage to the display panel. The display apparatus of claim 1, wherein the first intermediate image frame has the same value as the first image frame, and the second intermediate image frame and the first image frame have the same value. The display device according to claim 1, further comprising a three-dimensional timing converter for generating the black insertion control signal in response to a three-dimensional synchronization signal, and supplying the black insertion control signal to the data driver. 4. The display device according to claim 3, further comprising a frame memory for sequentially storing frames included in the 4x-speed video signal. 5. The display device according to claim 4, wherein the timing controller compensates a current image frame based on a previous image frame previously stored in the frame memory. The data driver as claimed in claim 3, wherein the data driver controls a polarity of the left eye data voltage and the right eye data voltage in response to an inversion signal,
Wherein the left eye data voltage and the right eye data voltage have different polarities with respect to a predetermined reference voltage. The display device according to claim 6, wherein the black data voltage has the same voltage level as the reference voltage. The method of claim 6, wherein the black data voltage includes a first black data voltage and a second black data voltage having different polarities with respect to the reference voltage,
Wherein the data driver selects either the first or the second black data voltage according to the polarity of the left and right data voltages in response to the inverted signal and the black insertion control signal. The method according to claim 6,
Wherein the three-dimensional timing converter generates an inversion control signal in response to the three-dimensional synchronization signal, provides the inversion control signal to the timing controller,
Wherein the timing controller changes the period of the inversion signal for controlling the polarity inversion of the left eye data voltage and the right eye data voltage to the data driver in response to the inversion control signal. The display device according to claim 9, wherein the state of the inverted signal is inverted in units of two frames. The apparatus according to claim 1,
A three-dimensional timing converter for generating the black insertion control signal in response to a three-dimensional synchronization signal, and supplying the black insertion control signal to the data driver; And
And a frame memory for sequentially storing the frames included in the 4x-speed video signal. 12. The liquid crystal display of claim 11, wherein the data driver controls a polarity of the left eye data voltage and the right eye data voltage in response to an inversion signal,
Wherein the left eye data voltage and the right eye data voltage have different polarities with respect to a predetermined reference voltage. 13. The display device according to claim 12, wherein the black data voltage has the same voltage level as the reference voltage. The apparatus of claim 1, further comprising a gamma voltage generator for providing a gamma reference voltage to the data driver,
Wherein the data driver converts each of the first compensation frame and the second compensation frame into the left eye data voltage and the right eye data voltage based on the gamma reference voltage. The display device according to claim 1, wherein the frame rate converter has a driving frequency of 240 Hz. Separating a video signal into a first image frame for the left eye and a second image frame for the right eye;
Generating a first intermediate image frame and a second intermediate image frame that are continuous with the first image frame and the second image frame, respectively;
Compensating the first image frame with a first compensation frame and converting the second image frame into a second compensation frame;
Converting the first and second compensation frames into a left eye data voltage and a right eye data voltage, respectively, and outputting the first intermediate image frame and the second intermediate image frame in black Converting into a data voltage; And
And displaying the image in the order of the left eye data voltage, the black data voltage, the right eye data voltage, and the black data voltage. 17. The method according to claim 16, wherein the left eye data voltage and the right eye data voltage have different polarities with respect to a predetermined reference voltage. 18. The method of claim 17, wherein the black data voltage has the same voltage level as the reference voltage. The method of claim 17, wherein the black data voltage includes a first black data voltage and a second black data voltage having different polarities with respect to the reference voltage,
Wherein either one of the first and second black data voltages is selected in accordance with polarities of the left eye and right eye data voltages. Separating a video signal into a first image frame for the left eye and a second image frame for the right eye;
Generating a first intermediate image frame and a second intermediate image frame that are continuous to the first image frame and the second image frame, respectively;
Converting the first image frame into a left eye data voltage and the second image frame into a right eye data voltage;
Inserting a black data voltage corresponding to a predetermined black gradation between the left eye data voltage and the right eye data voltage in response to a black insertion control signal; And
And displaying the image by continuously receiving the left eye data voltage, the black data voltage, and the right eye data voltage. 21. The method of claim 20, wherein the left eye data voltage and the right eye data voltage have different polarities with respect to a predetermined reference voltage. 22. The method of claim 21, wherein the black data voltage has the same voltage level as the reference voltage. 22. The display device according to claim 21, wherein the black data voltage includes a first black data voltage and a second black data voltage having different polarities with respect to the reference voltage, And the second black data voltage is selected as the second black data voltage.

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