KR101664182B1 - Organic electro-luminescent device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic electroluminescent device, and more particularly, to an organic electroluminescent device capable of reducing a mask process and preventing damage to a metal wiring.
A feature of the present invention is that the protective layer is removed and the metal wiring corresponding to the frit pattern is formed into a jumping structure.
Therefore, by eliminating the protective layer, the process cost can be reduced and the efficiency of the process can be improved, and at the same time, the metal wiring can be prevented from being damaged by the frit pattern, and the occurrence of contact failure can be prevented.
Thus, the electrical characteristics and reliability of the OLED can be improved.
Further, since the frit pattern comes into contact with the interlayer insulating film having a better adhesive force than when it is directly bonded to the metal wiring, the adhesion of the frit pattern can be improved and the permeation of oxygen and moisture can be prevented more effectively.

Description

[0001] The present invention relates to an organic electroluminescent device,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic electroluminescent device, and more particularly, to an organic electroluminescent device capable of reducing a mask process and preventing damage to a metal wiring.

Until recently, CRT (cathode ray tube) was mainly used as a display device. However, in recent years, flat panel displays such as a plasma display panel (PDP), a liquid crystal display device (LCD), and an organic electro-luminescence device (OLED) Display devices have been widely studied and used.

Of the above flat panel display devices, an organic electroluminescent element (hereinafter referred to as OLED) is a self-luminous element and can be lightweight and thin because it does not require a backlight used in a liquid crystal display device which is a non-light emitting element.

In addition, it has a better viewing angle and contrast ratio than liquid crystal display devices, is advantageous in terms of power consumption, can be driven by DC low voltage, has a fast response speed, is resistant to external impacts due to its solid internal components, It has advantages.

Particularly, since the manufacturing process is simple, it is advantageous in that the production cost can be saved more than the conventional liquid crystal display device.

FIG. 1 schematically shows a cross section of a general OLED, wherein the OLED is a top emission type.

As shown, the OLED 10 comprises a first substrate 1 and a second substrate 2 facing the first substrate 1, and the first and second substrates 1, So that the edges thereof are sealed and joined together through a frit pattern (20).

In more detail, a driving thin film transistor DTr is formed for each pixel region P on the first substrate 1, a first electrode 11 connected to each driving thin film transistor DTr, An organic light emitting layer 13 for emitting light of a specific color is formed on the first electrode 11 and a second electrode 15 is formed on the organic light emitting layer 13.

The first and second electrodes 11 and 15 and the organic light emitting layer 13 formed therebetween form an organic light emitting diode E. At this time, the OLED 10 having such a structure constitutes the first electrode 11 as the anode and the second electrode 15 as the cathode.

The non-display area NA outside the display area AA is exposed to the outside and is electrically connected to a pad for applying a signal voltage to the driving thin film transistor DTr and the organic electroluminescent diode E from an external power source And a pad portion PA having an electrode PAD formed thereon.

The driving thin film transistor DTr and the organic electroluminescent diode E are electrically connected to the pad portion PA through a plurality of wirings, that is, a link wiring (not shown).

A protective layer 27 is formed on the upper portion of the driving thin film transistor DTr so that the driving thin film transistor DTr is separated from external moisture and contaminants by the protective layer 27. The protective layer 27 is formed separately There is a problem in that a mask process of adding a mask is added.

In order to reduce the number of mask processes through the removal of the protective layer 27 but to remove the protective layer 27, the pad portion PA, the driving thin film transistor DTr, and the organic light emitting diode E There arises a problem that the link wiring (not shown) to be connected is damaged by the frit pattern 20 covering the edge of the OLED 10.

SUMMARY OF THE INVENTION It is a first object of the present invention to provide an OLED capable of shortening a masking process and shortening a process time and improving the efficiency of a cost reduction process.

Another object of the present invention is to prevent the metal wiring from being damaged when the protective layer is removed.

In order to achieve the above-mentioned object, the present invention is characterized in that first and second non-display regions are defined with a display region including a plurality of pixel regions and a frit pattern outside the display region, A first substrate including a pad electrode formed in a non-display region; A semiconductor layer located in the pixel region and having a first region of pure polycrystalline silicon and a second region doped with impurities on both sides of the first region; A gate insulating film formed on a front surface of the first substrate including the semiconductor layer; A gate electrode formed on the gate insulating film and corresponding to the first region; A jumping wiring formed in the same layer as the gate electrode and overlapped with the frit pattern; An interlayer insulating layer formed on the gate electrode and the jumping wiring and including first and second semiconductor contact holes for exposing the second region together with a gate insulating layer disposed under the gate electrode and the jumping wiring; First and second jumping wiring contact holes formed in the interlayer insulating film to expose a part of the jumping wiring; Source and drain electrodes formed in contact with the second region above the interlayer insulating film and spaced apart from each other; A driving element formed in the first non-display region and formed of the same material as the source and drain electrodes and formed in the same layer, the driving element being connected to the jumping wiring through the first jumping wiring contact hole; And a gate electrode formed on the second non-display region and formed on the same layer as the source and drain electrodes, one end connected to the jumping wiring through the second jumping wiring contact hole, A link wiring line connected to the connection line; An organic light emitting diode comprising a first electrode connected to the drain electrode, an organic light emitting layer and a second electrode; A second substrate facing the first substrate; And a frit pattern formed on the edges of the first and second substrates and overlapping the jumping wiring and the interlayer insulating film.

Here, the driving element is located inside the frit pattern, the link wiring and the pad electrode are located outside the frit pattern, and the driving element includes a gate and a data driver connected to the gate and the data line, And a power supply line connected to the power supply line.

The link wiring is a selected one of a power supply link wiring, a gate and a data link wiring, and a gate and a data wiring crossing each other on the first substrate to define the pixel region; And a power supply line formed so as to be spaced apart from the line of the gate and the data line, the pad electrode being located at an end of the gate and the data line.

According to another aspect of the present invention, an amorphous silicon layer is formed on the pixel region on the insulating substrate on which the first and second non-display regions are defined with the display region including a plurality of pixel regions and the frit pattern as the boundary outside the display region Forming an impurity amorphous silicon layer on the amorphous silicon by doping impurities on the amorphous silicon; Patterning the amorphous silicon layer and the impurity amorphous silicon layer by a second mask process to form a semiconductor layer; Forming a gate insulating film on the semiconductor layer; Depositing a first metal layer on the gate insulating layer, forming a gate wiring and a gate electrode in a second mask process, and forming a jumping wiring corresponding to the frit pattern; Forming an interlayer insulating film on the gate wiring, the gate electrode, and the jumping wiring; The first and second semiconductor contact holes exposing the impurity amorphous silicon layer of the semiconductor layer by patterning the interlayer insulating film and the gate insulating film in the pixel region in a third mask process, Patterning the interlayer insulating film in the region to form the first and second jumming wiring contact holes exposing the jumping wiring; Depositing a second metal layer on the interlayer insulating film, forming source and drain electrodes spaced apart from the gate electrode by a fourth mask process, and a data line connected to the source electrode; A driving element connected to the jumping wiring via the first jumping wiring in the same layer with the same material as the source and drain electrodes in the first non-display area; and a driving element connected to the second non- Forming a link wiring to be connected to the jumping wiring via the wiring layer; Forming a first electrode in the display region that is in contact with the drain electrode in a fifth mask process; Forming an organic light emitting layer on the first electrode; Forming a second electrode over the organic light emitting layer; Forming a frit pattern on a selected one of the first and second substrates after having a second substrate facing the first substrate; Attaching the first and second substrates such that the frit pattern overlaps the jumping wiring and the interlayer insulating film; And curing the frit pattern by irradiating the frit pattern with a laser beam.

Here, the driving element is formed on the inner side of the frit pattern, the link wiring is formed on the outside of the frit pattern, a pad electrode is formed on one end of the gate and the data wiring, Lt; / RTI >

As described above, the protective layer is removed according to the present invention, and the metal interconnection corresponding to the frit pattern is formed in a jumping structure, thereby reducing the process cost and improving the process efficiency, It is possible to prevent the metal wiring from being damaged, and to prevent the occurrence of contact failure.

Accordingly, the electrical characteristics and reliability of the OLED can be improved.

Further, since the frit pattern comes into contact with the interlayer insulating film having a better adhesive force than when it is directly bonded to the metal wiring, it has an effect of improving adhesion of the frit pattern and more effectively preventing penetration of oxygen and moisture.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 schematically shows a cross section of a typical OLED. FIG.
2 is a plan view schematically showing an OLED according to an embodiment of the present invention.
3 is a cross-sectional view schematically showing a cross section taken along a line III-III in FIG. 2 according to an embodiment of the present invention.
4 is an enlarged cross-sectional view of a non-display region according to an embodiment of the present invention;

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.

2 is a plan view schematically showing an OLED according to an embodiment of the present invention.

The OLED 100 includes a first substrate 101 on which a driving and switching thin film transistor DTr (not shown) and an organic light emitting diode E are formed, And the first and second substrates 101 and 102 are spaced apart from each other. The edge portions of the first and second substrates 101 and 102 are sealed and adhered to each other through a frit pattern 120.

Here, the first substrate 101 is divided into a display area AA for displaying an image and first and second non-display areas NA1 and NA2 for covering the edges of the display area AA, The second non-display areas NA1 and NA2 are defined by dividing the frit pattern 120 as a boundary.

A plurality of gate lines GL are formed in the display region AA in the first direction and extend in a second direction intersecting the first direction to form pixel regions P in addition to the gate lines GL A data line DL for defining a data line DL and a power line PL for applying a power source voltage are formed.

In each pixel region P, a switching thin film transistor STr connected to the two lines is formed at a portion where the gate line GL and the data line DL intersect each other. The switching thin film transistor STr includes a thin film transistor A transistor DTr and a storage capacitor StgC and the driving thin film transistor DTr is connected between the power supply line PL and the organic electroluminescent diode E. [

That is, the first electrode, which is one terminal of the organic electroluminescent diode E, is connected to the drain electrode of the driving thin film transistor DTr, and the second electrode, which is the other terminal, is grounded. At this time, the power supply line PL transfers the power supply voltage to the organic light emitting diode E.

A data driver 130 is formed in a second non-display area NA2 outside the display area AA and a gate driver 140 is formed on the left and right edges of the data driver 130 perpendicular to the edge, A plurality of pixel regions P are divided and scanned.

At this time, the gate driver 140 is located in the first non-display area NA1 inside the frit pattern 120. [

Power is supplied to the respective electrodes of the organic electroluminescent diode E between the gate driver 140 and the display area AA of the first non-display area NA1 and between the data driver 130 and the display area AA And the first and second power supply lines 150 and 160 are formed in the second non-display area NA2 (Not shown).

The first power supply line 150 is formed along the four edges of the display area AA and supplies a reference voltage to the second electrode of the organic light emitting diode E formed on the entire surface of the pixel area P, The second power supply line 160 is formed on the upper, lower, right, left, and right sides of the display area AA and is connected to the power supply line PL of the pixel area P to form the respective organic light emitting diodes E And supplies the power supply voltage to the first electrode, which is the other terminal.

A pad electrode PAD for electrically connecting to a FPC (not shown) in the form of a film is formed on the pad portion PA. A signal is inputted from the outside through an FPC (not shown) And the first and second power supply lines 150 and 160 are connected to each other through the power supply link wiring 190 and the gate and data drivers 130 and 140 are also connected to the pad And is connected to the electrode PAD.

The gate and data drivers 130 and 140 are connected to gates and data lines GL and DL of the pixel region P through gate signal link lines (not shown) and data signal link lines 180, respectively .

When signals are inputted from the outside to the first and second power supply lines 150 and 160 and the gate and data drivers 130 and 140 through the pad electrode PAD, the gate driver 140 and the data driver 130 perform scan Signal and data signals to the gate wiring GL and the data wiring DL, respectively.

Therefore, in each pixel region P, when a signal is applied through the gate line GL, the switching thin film transistor STr is turned on for each pixel region P, and the signal of the data line DL is driven The light is transmitted through the gate electrode of the thin film transistor DTr and the driving thin film transistor DTr is turned on to output light through the organic light emitting diode E.

At this time, when the driving thin film transistor DTr is turned on, the level of a current flowing from the power supply line PL to the organic electroluminescent diode E is determined, A gray scale can be realized.

The storage capacitor StgC maintains the gate voltage of the driving thin film transistor DTr constant when the switching thin film transistor STr is turned off so that the switching thin film transistor STr is turned off The level of the current flowing through the organic electroluminescent diode E can be kept constant until the next frame.

As a most characteristic part of the present invention, the OLED 100 of the present invention includes a first non-display area NA1 and a second non-display area NA2, that is, wirings 170 formed outside the frit pattern 120 The wirings 140, DL, 150 and 160 formed inside the frit pattern 120 and the driving elements 140 are connected to each other through the jumping wirings 200.

That is, the first and second power supply lines 150 and 160 and the gate driver 140 are located inside the frit pattern 120 so as to surround the edge of the display area AA, The lines 150 and 160 and the gate driver 140 are connected to the pad electrode PAD formed outside the frit pattern 120 through the power supply link wiring 190 and the gate link wiring 170, .

The data driver 130 is formed outside the frit pattern 120 and is electrically connected to a plurality of data lines DL of the display area AA through a data signal link wiring 180.

At this time, the power supply link wiring 190, the gate link wiring 170 and the data signal link wiring 180 of the present invention are formed only to the outside of the frit pattern 120, and the lower part of the frit pattern 120 and the frit pattern 120 A jumping wiring 200 is formed so as to be connected to the gate driver 140 and the data line DL and the first and second power supply lines 150 and 160 and the data line DL .

Accordingly, the OLED 100 according to the present invention can reduce the number of mask processes, shorten the process time, reduce the process cost, and increase the efficiency of the process. At the same time, the frit The pattern 120 prevents the power supply link wiring 190, the gate link wiring 170, and the data signal link wiring 180 from being damaged.

This will be described in more detail with reference to FIG.

3 is a cross-sectional view schematically showing a cross-section taken along line III-III of FIG. 2 according to an embodiment of the present invention.

The OLED 100 according to the present invention includes a first substrate 101 on which a driving and switching thin film transistor DTr and an organic light emitting diode E are formed, The first and second substrates 101 and 102 are spaced apart from each other. The edges of the first and second substrates 101 and 102 are sealed through a frit pattern 300, do.

A semiconductor layer 201 is formed in each pixel region P in the display region AA of the first substrate 101. The semiconductor layer 201 is made of silicon and the central portion thereof includes an active region 201a, And source and drain regions 201b and 201c doped with impurities at a high concentration on both sides of the active region 201a.

A gate insulating layer 203 is formed on the semiconductor layer 201.

A gate wiring GL extending in one direction from the gate electrode 205 corresponding to the active region 201a of the semiconductor layer 201 is formed in each pixel region P in the display region AA Respectively.

An interlayer insulating film 207 is formed on the entire upper surface of the gate electrode 205 and the gate wiring GL and the interlayer insulating film 207 and the gate insulating film 203 under the gate insulating film 207 are formed on both sides of the active region 201a And first and second semiconductor layer contact holes 209a and 209b exposing the source and drain regions 201b and 201c, respectively.

Next, in each pixel region P, first and second semiconductor layer contact holes 209a and 209b are formed on the upper part of the interlayer insulating film 207 including the first and second semiconductor layer contact holes 209a and 209b, And source and drain electrodes 211 and 213 which are in contact with the source and drain regions 201b and 201c, respectively,

At this time, the semiconductor layer 201 including the source and drain electrodes 211 and 213 and the source and drain regions 201b and 201c in contact with the electrodes 211 and 213 and the gate insulating film 201 formed on the semiconductor layer 201 The gate electrode 203 and the gate electrode 205 constitute a driving thin film transistor DTr.

Although not shown in the drawing, a data line (DL in FIG. 2) is formed which intersects the gate wiring (not shown) to define the pixel region P. The switching thin film transistor STr in FIG. 2 has the same structure as the driving thin film transistor DTr and is connected to the driving thin film transistor DTr.

The switching thin film transistor (STr in FIG. 2) and the driving thin film transistor DTr are shown as an example of a top gate type in which the semiconductor layer 201 is formed of a polysilicon semiconductor layer. Or may be formed as a bottom gate type of pure and impurity amorphous silicon.

The first electrode 111, the organic light emitting layer 113, and the second electrode 115 constituting the organic electroluminescent diode E are sequentially formed in a region for displaying an image on the interlayer insulating film 207 .

The first electrode 111 is connected to the drain electrode 213 of the driving thin film transistor DTr.

That is, the OLED 100 of the present invention is characterized in that the organic electroluminescent diode E is directly located on the interlayer insulating film 207. Thus, the existing protective layer (27 in FIG. 1) can be removed, and the protective layer (27 in FIG. 1) can be removed.

1) of the organic light emitting diode E includes the drain electrode 213 and the first electrode (not shown) of the organic light emitting diode E, 111 may be in contact with each other, a contact hole (not shown) may be formed to expose the drain electrode 213 through a separate mask process. However, the present invention is not required to form such a contact hole (not shown) One mask process can be reduced.

Meanwhile, the OLED 100 is divided into a top emission type and a bottom emission type according to the transmission direction of the emitted light. Hereinafter, the bottom emission type will be described as an example of the present invention.

Accordingly, the first electrode 111 is preferably formed of indium-tin-oxide (ITO), which is a relatively high work function value, to serve as an anode electrode.

The second electrode 115 is made of aluminum (Al) or an aluminum alloy (AlNd), which is a metal material having a relatively low work function value, in order to serve as a cathode.

Accordingly, the light emitted from the organic light emitting layer 113 is driven by the lower light emitting method, which is emitted toward the first electrode 111.

A hole injection layer, a hole transporting layer, and an emitting material layer may be formed on the organic light emitting layer 113 to enhance the light emitting efficiency. , An electron transporting layer, and an electron injection layer.

Therefore, when a predetermined voltage is applied to the first electrode 111 and the second electrode 115 according to a selected color signal, the OLED 100 can emit electrons injected from the first electrode 111 and electrons injected from the second electrode 115, The excitons are transported to the organic light emitting layer 113 to form excitons. When the excitons transit from the excited state to the ground state, light is emitted and emitted in the form of visible light.

At this time, the emitted light passes through the transparent first electrode 111 and exits to the outside, so that the OLED 100 realizes an arbitrary image.

The first electrode 111 is formed for each pixel region P and a bank 221 is located between the first electrodes 111 formed for each pixel region P. [

That is, the banks 221 are formed in a matrix type of a grid structure as a whole on the substrate 101, and the first electrodes 111 are divided into the pixel regions P with the banks 221 as boundary portions for the respective pixel regions Respectively.

Particularly, in the process of attaching the first and second substrates 101 and 102, the edges of the first and second substrates 101 and 102 are sealed together through the frit pattern 120 as described above.

Thereby, the OLED 100 is encapsulated.

The frit pattern 120 is formed in a non-display area NA covering the edge of the display area AA for sealing the display area AA and preventing penetration of oxygen and moisture.

The frit pattern 120 is much smaller than a water molecule in terms of its material properties and is far superior to a seal pattern of a sealant in terms of preventing water from penetrating from the outside. Therefore, the organic light emitting diode ) Can be prolonged.

As described above, the OLED 100 of the present invention encapsulates and adheres the first and second substrates 101 and 102 through the frit pattern 120 made of an inorganic material, 101, 102 are sealed more tightly.

This allows a contamination source such as moisture or gas from the outside to penetrate into the space between the first and second substrates 101 and 102 apart from the outside by the space between the first and second substrates 101 and 102 Can be prevented.

Therefore, deterioration of the organic electroluminescent diode (E) can be prevented and the lifetime of the OLED (100) can be extended. Also, since the first and second substrates 101 and 102 are firmly attached to each other to reduce the defect rate generated after the cementation, the overall cost and material cost loss are reduced and the production yield is improved.

Particularly, the OLED 100 of the present invention has the first and second power supply lines (150 and 160 in FIG. 2) positioned inside the frit pattern 120 as the protective layer (27 in FIG. 1) The first and second power supply lines 150 and 160 of FIG. 2 and the gate driver 140 of FIG. 2 may be formed between the gate insulating layer 203 and the interlayer insulating layer 140, The jumping wiring 200 located under the insulating film 207 and the jumping wiring contact hole 210 exposing the jumping wiring 200 are connected.

The jumping wiring 200 is formed on the outside of the frit pattern 120 and is connected to the power supply link wiring 190 (FIG. 2) connected to the pad electrode PAD of the pad portion PA and the gate link wiring ).

The first and second power supply lines 150 and 160 and the gate driver 140 of FIG. 2 located inside the frit pattern 120 are electrically connected to the frit pattern 120 through the jumping wiring 200, The pad electrode PA of the pad portion PA is connected to the power supply link wiring 190 of FIG. 2 and the gate link wiring 170 of FIG. It is connected.

2) for connecting the first and second power supply lines (150 and 160 in FIG. 2) and the gate driver (140 in FIG. 2) to the pad electrode (PAD) ) And the gate link wiring (170 in FIG. 2) from being damaged by the frit pattern 120. [0064] As shown in FIG.

2) and the gate driver (140 in FIG. 2) are connected to the pad electrode (PAD) of the pad unit (PA) in the conventional OLED, and the first and second power supply lines 2) and the gate driver (140 in FIG. 2) of the power supply link wiring (190 in FIG. 2) and the gate link wiring (170 in FIG. 2) and the first and second power supply lines The same material as the source and drain electrodes 211 and 213 of the transistor DTr is formed in the same layer.

2), the gate driver (140 in FIG. 2), and the power source (not shown in FIG. 2) in the case of deleting the protection layer (27 in FIG. 1) like the OLED 100 of the present invention. Both the link wiring (190 in FIG. 2) and the gate link wiring (170 in FIG. 2) are configured to be exposed.

Thus, a part of the frit pattern 120 formed around the edge of the substrate 101 and the power supply link wiring 190 (FIG. 2) and the gate link wiring (170 of FIG. 2) overlap each other.

Here, the frit pattern 120 generally refers to a state in which a paste-like frit made of a glass raw material in the form of powder is cured through a firing process. That is, after the frit pattern 120 is formed on the substrate 101, it is required to undergo a process of curing by irradiating laser and infrared rays using a laser device (not shown) or the like.

2) 190 and the gate link wiring (170 in FIG. 2) overlapping with the frit pattern 120 are formed on the frit pattern 120 in the process of firing the frit pattern 120 There arises a problem that it is damaged by an applied laser or infrared rays.

This results in a poor contact between the pad electrode PAD and the power supply link wiring 190 (FIG. 2) and the gate link wiring (FIG. 2) 170. Accordingly, signals transmitted from an external power supply (not shown) Or an open defect that can not be transmitted to the data line (GL, DL in FIG. 2), and eventually causes the driving failure of the OLED 100.

Further, as the metal wiring (170, 190 in FIG. 2) is positioned between the frit pattern 120 and the substrate 101, the combined force between the frit pattern 120 and the substrate 101 is lowered , And the combined power of the OLED 100 is lowered.

Therefore, the OLED 100 of the present invention has the jumping wiring 200 separately provided under the gate insulating film 203 or the interlayer insulating film 207, and the first and second power supply lines 150 and 160 The gate drive unit 140 of FIG. 2 is connected to the pad electrode PAD of the pad unit PA located outside the frit pattern 120 through the jumping wiring 200, Thereby preventing the power supply link wiring (190 in FIG. 2) and the gate link wiring (170 in FIG. 2) from being damaged.

Further, since the frit pattern 120 comes into contact with the interlayer insulating film having a better adhesive force than the case where the frit pattern 120 is directly bonded to the metal wiring, the adhesion of the frit pattern can be improved and penetration of oxygen and moisture can be prevented more effectively.

2) of the data driver (130 in FIG. 2) formed outside the frit pattern 120 and the data line (DL in FIG. 2) in the inside display area AA of the frit pattern 120 are connected (180 in FIG. 2) to be connected to each other through the jumping wiring 200.

4 is an enlarged cross-sectional view of a non-display region according to an embodiment of the present invention.

A semiconductor layer 201 including an active region 201a and source and drain regions 201b and 201c and a semiconductor layer 201 including a gate insulating film 203 and a gate 201c are formed in each pixel region P of the display region AA, A driving thin film transistor DTr including an electrode 205, source and drain electrodes 211 and 213, and an interlayer insulating film 207 is formed.

An organic light emitting diode E (E) including a first electrode 111, an organic light emitting layer 113, and a second electrode 115, which is in contact with the drain electrode 213 of the driving thin film transistor DTr, Is formed.

A second power supply line 160 formed in the same layer as the source and drain electrodes 211 and 213 of the driving thin film transistor DTr is formed in the frit pattern 120 of the non-display area NA. Is formed on the upper surface of the interlayer insulating film 207.

The second power supply line 160 overlaps the frit pattern 120 and exposes a part of the jumping wiring 200 and the jumping wiring 200 located under the interlayer insulating layer 207 to the inside of the frit pattern 120 And are connected to each other through the first jumper wiring contact hole 210a.

The source and drain electrodes 211 and 213 of the driving thin film transistor DTr and the second power supply line 160 of the non-display area NA are formed in the same layer on the outside of the frit pattern 120, The power supply link wiring 190 is formed on the interlayer insulating layer 207 and the power supply link wiring 190 is connected to the pad electrode PAD of the pad portion PA.

The power supply link wiring 190 is connected to the jumping wiring 200 through a second jumping wiring contact hole 210b exposing a part of the jumping wiring 200 to the outside of the frit pattern 120. [

The second power supply line 160 located inside the frit pattern 120 is connected to the power supply link wiring 190 located outside the frit pattern 120 through the jumping wiring 200, And is connected to the pad electrode PAD of the pad portion PAD.

This prevents the power supply wiring line 190 connecting the pad electrode PAD of the pad portion PA and the second power supply line 160 from being damaged by the firing process of the frit pattern 120.

In addition, since the frit pattern 120 comes into contact with the interlayer insulating film 207, the bonding strength with the substrate 101 is also improved, so that the bonding force of the OLED 100 can be improved.

Here, it is preferable that the jumping wiring 200 is formed on the same layer with the same material in the process of forming the gate electrode 205 of the driving thin film transistor DTr. Accordingly, the jumping wiring 200 is formed simultaneously with the mask process for forming the gate electrode 205, so that the additional mask process is not required.

The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the present invention.

101: first substrate, 102: second substrate, 111: first electrode
113: organic light emitting layer, 115: second electrode, 120: frit pattern
160: second power supply line, 190: power link wiring, 200: jumping wiring
201: semiconductor layer (201a: active region, 201b, 201c: source and drain regions)
203: gate insulating film, 205: gate electrode, 207: interlayer insulating film
209a, 209b: first and second semiconductor layer contact holes 211; Source electrode, 213: drain electrode
210a, 210b: first and second jumping wiring contact holes, 221:
AA: display area, NA: non-display area, P: pixel area
PA: pad portion, PAD: pad electrode

Claims (8)

A first and a second non-display areas are defined with a frit pattern therebetween and a display area including a plurality of pixel areas, and a first electrode including a pad electrode located in the second non- Claims [1]
A semiconductor layer located in the pixel region and having a first region of pure polycrystalline silicon and a second region doped with impurities on both sides of the first region;
A gate insulating film located on a front surface of the first substrate including the semiconductor layer;
A gate electrode positioned on the gate insulating film and corresponding to the first region;
A jumping wiring located in the same layer as the gate electrode and overlapped with the frit pattern;
An interlayer insulating layer disposed on the gate electrode and the jumping wiring and including first and second semiconductor contact holes exposing the second region together with a gate insulating layer disposed under the gate electrode and the jumping wiring;
First and second jumping wiring contact holes provided in the interlayer insulating film to expose a part of the jumping wiring;
Source and drain electrodes which are in contact with the second region above the interlayer insulating film and are spaced apart from each other;
A bank covering the source and drain electrodes and located at a boundary of the plurality of pixel regions;
A driving element located in the first non-display region and formed of the same material as the source and drain electrodes and located in the same layer and connected to the jumping wiring through the first jumping wiring contact hole;
And the source electrode and the drain electrode are formed of the same material as the source and drain electrodes and are located on the same layer, one end is connected to the jumping wiring through the second jumping wiring contact hole, A link wiring line connected to the connection line;
An organic light emitting diode comprising a first electrode connected to the drain electrode, an organic light emitting layer and a second electrode;
A second substrate facing the first substrate;
A frit pattern disposed over the edges of the first and second substrates and overlapping the jumping wiring and the interlayer insulating film;
Wherein the second electrode is disposed on a front surface of the substrate including the bank, and the frit pattern is in intimate contact with the interlayer insulating layer.
The method according to claim 1,
Wherein the driving element is located inside the frit pattern, and the link wiring and the pad electrode are located outside the frit pattern.
The method according to claim 1,
Wherein the driving element is a selected one of a gate and a data driver connected to the gate and the data line, and a power supply line connected to the power line.
The method according to claim 1,
Wherein the link wiring is a power supply link wiring or a gate and a data link wiring.
The method according to claim 1,
A gate and a data line crossing each other on the first substrate to define the pixel region;
A power supply wiring line formed in parallel with the one of the gate and data lines,
And the pad electrode is located at an end of the gate and the data line.
There is provided an amorphous silicon device comprising a display region including a plurality of pixel regions and an amorphous silicon layer in the pixel region on a first substrate on which first and second non-display regions are defined with a frit pattern as a boundary outside the display region, Doping an impurity on the silicon to provide an impurity amorphous silicon layer;
Patterning the amorphous silicon layer and the impurity amorphous silicon layer by a second mask process to form a semiconductor layer;
Providing a gate insulating layer on the semiconductor layer;
Depositing a first metal layer on the gate insulating layer, forming a gate wiring and a gate electrode in a second mask process, and providing a jumping wiring corresponding to the frit pattern;
Providing an interlayer insulating film on the gate wiring, the gate electrode, and the jumping wiring;
The first and second semiconductor contact holes exposing the impurity amorphous silicon layer of the semiconductor layer by patterning the interlayer insulating film and the gate insulating film in the pixel region in a third mask process, The first and second jumping wiring contact holes exposing the jumping wiring by patterning the interlayer insulating film in the region;
A source electrode and a drain electrode spaced apart from each other in a state of being overlapped with the gate electrode in a fourth mask process after depositing a second metal layer on the interlayer insulating film; and a data line connected to the source electrode;
A driving element connected to the jumping wiring via the first jumping wiring in the same layer with the same material as the source and drain electrodes in the first non-display area; and a driving element connected to the second non- And a link wiring connected to the jumping wiring via the wiring line.
Providing a first electrode in the display region in contact with the drain electrode in a fifth mask process;
A bank covering the source and drain electrodes in correspondence with a boundary of the plurality of pixel regions of the display region;
Providing an organic light emitting layer on the first electrode;
Providing a second electrode over the entire surface of the first substrate including the bank above the organic light emitting layer;
Providing a second substrate to face the first substrate and then providing a frit pattern on a selected one of the first and second substrates;
Attaching the first and second substrates such that the frit pattern overlaps the jumping wiring and the interlayer insulating film;
Curing the frit pattern by irradiating the frit pattern with a laser beam
Wherein the frit pattern is in intimate contact with the interlayer insulating layer.
The method according to claim 6,
Wherein the driving element is formed inside the frit pattern, and the link wiring is provided outside the frit pattern.
The method according to claim 6,
Wherein a pad electrode is formed at one end of the gate and the data line, and the link wiring is connected to the pad electrode.

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