KR101657159B1

KR101657159B1 - Transient voltage suppressor package

Info

Publication number: KR101657159B1
Application number: KR1020140186046A
Authority: KR
Inventors: 김현식; 장희원; 백종윤
Original assignee: 주식회사 케이이씨
Priority date: 2014-12-22
Filing date: 2014-12-22
Publication date: 2016-09-20
Also published as: KR20160076176A

Abstract

The present invention relates to a transient voltage suppressor package, and it is an object of the present invention to provide an overvoltage suppressor package, in which when an overcurrent due to a transient voltage is continuously applied to a transient voltage suppressor due to a load failure, So that a continuous overcurrent is prevented from being applied to the transient voltage suppressing element.
To this end, the present invention discloses a transient voltage suppression device package comprising a transient voltage suppression element and a positive temperature coefficient thermistor connected in series with the transient voltage suppression element.

Description

[0001] Transient voltage suppressor package [0002]

The present invention relates to a transient voltage suppression device package.

Referring to Fig. 1, the operation principle and circuit diagram of the transient voltage suppressing element are shown.

A transient voltage suppressing device TVS (for example, varistor, thyristor, diode (rectifier / zener)) is connected in parallel between a power source VG and a load RLOAD as shown in FIG. One side of the transient voltage suppressing device TVS is connected to the ground GND.

In such a configuration, when a transient voltage exceeding a voltage required by the load (RLOAD) is input by surge or ESD (Electrostatic Discharge), the transient current ITV due to the transient voltage is input to the transient voltage suppressor To the ground GND. That is, the transient voltage suppressing device TVS can safely protect the load RLOAD from the transient voltage by allowing only the clamped and stabilized voltage to be applied to the load RLOAD.

However, when the load RLOAD is poor, the transient voltage suppressing device TVS receives the current applied through the power source VG continuously. Therefore, the transient voltage suppressing device TVS may be damaged due to heat, Can be generated.

SUMMARY OF THE INVENTION It is an object of the present invention to overcome the above-mentioned problems of the prior art, and it is an object of the present invention to provide a transient voltage suppressing device in which, when an overcurrent due to a transient voltage is continuously applied to a transient voltage suppressing device, And to prevent a continuous overcurrent from being applied to the transient voltage suppressing element.

A transient voltage suppressing device package according to the present invention includes: a first conductive type substrate; a first conductive type epilayer formed on a first surface of the first conductive type substrate; An insulating layer formed in the second conductive type well region to expose a part of a first surface of the second conductive type well region to the outside; A transient voltage suppressing element including a first electrode layer formed to cover the first surface of the exposed second conductivity type well region and a positive temperature coefficient thermistor electrically connected to the first electrode layer of the transient voltage suppressing element have.

The positive temperature coefficient thermistor may include a ceramic layer, a first electrode formed on a first surface of the ceramic layer, and a second electrode formed on a second surface opposite to the first surface of the ceramic layer.

And a conductive wire electrically connecting the first electrode of the positive temperature coefficient thermistor and the first electrode layer of the transient voltage suppressing element to each other.

And a second electrode layer formed on a second surface of the transient voltage suppressing element opposite to the first surface of the first conductive type substrate.

A lead pad on which the transient voltage suppressing element is mounted and which is electrically connected to the second electrode layer and a lead portion on which the positive temperature coefficient thermistor is mounted and which is electrically connected to the second electrode of the positive temperature coefficient thermistor, .

The transient voltage suppressing element, the conductive wire, and the positive temperature coefficient thermistor. The encapsulant may be formed to cover the lead frame, the transient voltage suppressing element, the conductive wire, and the positive temperature coefficient thermistor.

The encapsulant may expose a part of the die pad of the lead frame and a part of the lead part to the outside.

The transient voltage suppressor package according to the present invention may include a transient voltage suppressor and a positive temperature coefficient thermistor connected in series with the transient voltage suppressor.

The overvoltage suppression device package according to the present invention can increase the resistance of the positive temperature coefficient thermistor to reduce the overcurrent when the overcurrent due to the transient voltage is continuously applied to the transient voltage suppressor due to the failure of the load, So that it can be prevented from being applied to the transient voltage suppressing element.

1 is a circuit diagram for explaining the operation principle of a general transient voltage suppressing element.
2A and 2B are a plan view and a cross-sectional view illustrating a transient voltage suppressor package according to an embodiment of the present invention.
Figure 3 shows the equivalent circuit of the transient voltage suppressor package of Figure 2a.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified in various other forms, The present invention is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more faithful and complete, and will fully convey the scope of the invention to those skilled in the art.

In the following drawings, thickness and size of each layer are exaggerated for convenience and clarity of description, and the same reference numerals denote the same elements in the drawings. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" include singular forms unless the context clearly dictates otherwise. Also, " comprise "and / or" comprising "when used herein should be interpreted as specifying the presence of stated shapes, numbers, steps, operations, elements, elements, and / And does not preclude the presence or addition of one or more other features, integers, operations, elements, elements, and / or groups.

Although the terms first, second, etc. are used herein to describe various elements, components, regions, layers and / or portions, these members, components, regions, layers and / It is obvious that no. These terms are only used to distinguish one member, component, region, layer or section from another region, layer or section. Thus, a first member, component, region, layer or section described below may refer to a second member, component, region, layer or section without departing from the teachings of the present invention.

Referring to FIG. 2A, there is shown a plan view of a transient voltage suppressor package according to an embodiment of the present invention, and FIG. 2B is a sectional view taken along line 2b-2b of FIG. 2A.

2A and 2B, the transient voltage suppressor package 100 may include a lead frame 110, a first conductive substrate 120, a first conductive epi layer 130, The second conductive type well region 140, the insulating layer 150, the first electrode layer 160, the second electrode layer 170, the positive temperature coefficient thermistor 180, the conductive wire 190, and the encapsulant 195 . The transient voltage suppressor TVS includes a first conductive substrate 120, a first conductive epi layer 130, a second conductive well region 140, an insulating layer 150, a first electrode layer 160, And a second electrode layer 170.

The first conductivity type may be an N-type semiconductor layer containing an impurity such as arsenic (As), phosphorus (P), or antimony (Sb), which is a Group 5 element, ), Indium (In), boron (B), or the like. On the contrary, when the first conductivity type is a P-type semiconductor layer containing an impurity such as gallium (Ga), indium (In) or boron (B) as a Group III element, the second conductivity type is arsenic (As) , Phosphorus (P), antimony (Sb), or the like.

Hereinafter, the case where the first conductivity type is the N-type semiconductor layer and the second conductivity type is the P-type semiconductor layer will be described.

The lead frame 110 has a substantially plate shape and includes a die pad 111 connected to the second electrode layer 160 of the transient voltage suppressing element TVS and a lead portion 112 spaced from the die pad 111 . The positive temperature coefficient thermistor 180 mounted on the die pad 111 and the positive temperature coefficient thermistor 180 mounted on the lead portion 112 are disposed on the lead portion 112 And is electrically connected through the conductive wire 190.

The lead frame 110 may be located inside the encapsulant 195 and may be partially exposed to the outside of the encapsulant 195 to be an external terminal of the transient voltage suppression device package 100. A part of the die pad 111 of the lead frame 110 is exposed to the outside of the encapsulant 195 to become the first terminal 111a and a part of the lead part 112 is encapsulated 195 to form the second terminal 112a. That is, the transient voltage suppressing device package 100 includes the second terminal 112a of the lead portion 112 electrically connected to the positive temperature coefficient thermistor 180, the second electrode layer 160 of the transient voltage suppressing element TVS, And a first terminal 111a of the die pad 111 electrically connected thereto.

The first conductive substrate 120 has a substantially plate shape and has a first surface 121 and a second surface 122 which is opposite to the first surface 121. The first conductive type substrate 120 has a first surface 121 contacting the second surface 132 of the first conductive epi layer 130 and a second surface 122 contacting the second electrode layer 170 . The first conductive type substrate 120 may be a high concentration (N +) semiconductor wafer including an N type impurity which is a Group 5 element such as arsenic (As), phosphorous (P), or antimony (Sb)

The first conductive epi layer 130 is deposited from the first surface 121 of the first conductive type substrate 120 and is formed of a Group 5 element such as arsenic (As), phosphorus (P), or antimony (Sb) And may be an N-type semiconductor layer containing impurities at a low concentration. Here, the low concentration means that the concentration is relatively low compared to the impurity concentration of the first conductive type substrate 120. The first conductive type epi layer 130 includes a first surface 131 that is in contact with the insulating layer 150 and a second surface 131 that is opposite to the first surface 131, And a second surface 132 in contact with the first surface 121.

The second conductive well region 140 is formed inward from the first surface 131 of the first conductive epi layer 130. The second conductive type well region 140 may be formed of gallium (Ga), indium (In), boron (B), or the like as a Group III element in the inward direction from the first surface 131 of the first conductive type epilayer 130 By ion implantation at a high concentration. The depth of the second conductive type well region 140 may be lower than the height of the first conductive type first epi layer 130. That is, the second conductive type well region 140 may be located inside the first conductive type first epi-layer 130. The first surface 141 of the second conductive type well region 140 is located on the same plane as the first surface 131 of the first conductive epi layer 130. The PN junction of the second conductive type well region 140 and the first conductive epi layer 130 realizes a transient voltage suppressing device TVS.

The insulating layer 150 is formed to cover the first surface 131 of the first conductive epitaxial layer 130 and the first surface 141 of the second conductive type well region 140. The insulating layer 150 covers all of the first surface 131 of the first conductive epi layer 130 exposed to the outside and a part of the first surface 141 of the second conductive type well region 140 Respectively . The insulating layer 150 may be interposed between the second conductive type well region 140 and the first surface 141 and the electrode layer 160 and may include a second conductive type well region 140 and a first surface 141 Can be exposed to the outside. At this time, the second conductive type well region 140 exposed through the insulating layer 150 and the first surface 141 may be electrically connected to the electrode layer 160. The insulating layer 150 may be formed to cover the first surface 131 of the first conductive epi-layer 130 to protect the first conductive epi-layer 130 from the external environment.

The first electrode layer 160 is formed to cover the first surface 141 of the second conductive well region 140 and the first surface 151 of the insulating layer 150. The first electrode layer 160 is formed to cover the entire first surface 120a of the second conductive well region 140 exposed to the outside through the insulating layer 150, And may extend to the first surface 151. The first electrode layer 160 is electrically connected to the positive temperature coefficient thermistor 180 through the conductive wire 190. The first electrode layer 160 may be formed by sequentially sputtering or sequentially plating molybdenum (Mo), aluminum (Al), nickel (Ni), and gold (Au) The invention is not limited thereto.

The second electrode layer 170 covers the entire second surface 122 of the first conductive type substrate 120 and is electrically connected to the first conductive type substrate 120. That is, the second electrode layer 170 is interposed between the first conductive type substrate 120 and the lead frame 110 to electrically connect the first conductive type substrate 120 and the lead frame 110. The second electrode layer 170 may be formed by sequentially sputtering or sequentially plating molybdenum (Mo), aluminum (Al), nickel (Ni), and gold (Au) The invention is not limited thereto.

The positive temperature coefficient thermistor 180 may be a flat ceramic layer 181 and may include a first electrode 182 formed to cover the first surface 181a of the ceramic layer 181, And a second electrode 183 formed to cover the second surface 181b of the ceramic layer 181. [ The ceramic layer 181 may be made of a semiconductor ceramic or a ceramics, and the material of the ceramic layer 181 is not limited in the present invention. In addition, the positive temperature coefficient thermistor 180 may have a structure in which ceramic layers are laminated in a multilayer structure. The first electrode 182 is electrically connected to the first electrode layer 160 of the transient voltage suppressing element TVS through the conductive wire 190 and the second electrode 183 is electrically connected to the first electrode layer 160 of the transient voltage suppressing element TVS, And is electrically connected to the lead portion 112 of the lead frame 110.

The conductive wire 190 electrically connects the positive temperature coefficient thermistor 180 between the first electrode 182 and the first electrode layer 160 of the transient voltage suppressing device TVS. The conductive wire 190 may be formed of any one of gold (Au), aluminum (Al), and copper (Cu) or an alloy thereof. However, the present invention is not limited thereto. The conductive wire 190 may also be located inside the encapsulant 195 and protected from the external environment by the encapsulant 195.

The encapsulant 195 may be made of an insulating material and may be formed of a conductive material such as a lead frame 110, a transient voltage suppressor (TVS), a positive temperature coefficient thermistor 180 and a conductive wire 190, Encapsulate. At this time, a part of the die pad 111 of the lead frame 110 is exposed to the outside of the encapsulant 195 to become the first terminal 111a, and a part of the lead part 112 is connected to the encapsulant 195 And is exposed to the outside to become the second terminal 112a.

In such a transient voltage suppression device package 100, the first terminal 111a and the second terminal 112a of the lead frame 110 are exposed to the outside of the encapsulant 195, and the transient voltage suppressor package 100 As shown in Fig. The first electrode 182 of the transient voltage suppressing element TVS and the first electrode layer 160 of the positive temperature coefficient thermistor 180 are connected to each other through the conductive wire 190. [ The transient voltage suppression device package 100 further includes a first terminal 111a of the lead frame 110 connected to the second electrode layer 170 of the transient voltage suppressing device TVS and a second terminal 111b of the second characteristic The second terminal 112a of the lead frame 110 connected to the electrode 183 is exposed to the outside. That is, the transient voltage suppression device package 100 includes a transient voltage suppressor (TVS) connected in series as shown in FIG. 3 and a positive temperature coefficient thermistor 180.

When a transient voltage is input between the first terminal 111a and the second terminal 112a by surge or ESD (Electrostatic Discharge), the transient voltage suppressor package 100 generates a current due to the transient voltage To flow through the transient voltage suppressing element TVS. When the transient voltage suppressing device package 100 is continuously supplied with the current due to the transient voltage due to the failure of the load between the first terminal 111a and the second terminal 112a, the positive temperature coefficient thermistor 180 ) Increases in proportion to the temperature rise, so that the current can be reduced to prevent the continuous overcurrent from being applied to the transient voltage suppressor (TVS).

It is to be understood that the present invention is not limited to the above-described embodiment, and that various modifications and variations of the present invention are possible in light of the above teachings. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

100; Transient suppression device package
110; Lead frame 120; The first conductive type substrate
130; A first conductive epitaxial layer 140; The second conductivity type well region
150; An insulating layer 160; The first electrode layer
170; A second electrode layer 180; Positive characteristic thermistor
190; Conductive wire 195; Encapsulation

Claims

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A first conductive type substrate;
A first conductive type epi layer formed on a first surface of the first conductive type substrate;
A second conductive well region formed inwardly from a first side of the first conductive epilayer;
An insulating layer formed in the second conductive type well region to expose a part of the first surface of the second conductive type well region to the outside; And
And a first electrode layer formed to cover the first surface of the second conductive type well region exposed to the outside through the insulating layer; And
And a positive temperature coefficient thermistor electrically connected to the first electrode layer of the transient voltage suppressing element,
Wherein the positive temperature coefficient thermistor comprises: a ceramic layer;
A first electrode formed on a first surface of the ceramic layer; And
And a second electrode formed on a second surface opposite to the first surface of the ceramic layer,
Further comprising a conductive wire electrically connecting the first electrode of the positive temperature coefficient thermistor and the first electrode layer of the transient voltage suppressing element to each other,
And a second electrode layer formed on a second surface of the transient voltage suppressing element opposite to the first surface of the first conductive substrate,
And a lead frame formed of a die pad on which the transient voltage suppressing element is mounted and electrically connected to the second electrode layer and a lead portion on which the positive temperature coefficient thermistor is mounted and which is electrically connected to the second electrode of the positive temperature coefficient thermistor Wherein the first and second electrodes are connected to each other.

The method of claim 5,
Further comprising an encapsulant formed to cover the lead frame, the transient voltage suppressing element, the conductive wire, and the positive temperature coefficient thermistor.

The method of claim 6,
The encapsulant
A part of the die pad of the lead frame and a part of the lead part are exposed to the outside.

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