KR101644296B1 - Frequency control circuit for led driver - Google Patents

Abstract

The present invention relates to a frequency control circuit for driving an LED, comprising: a reference time generator for generating a reference time for determining one period of a frequency to be limited; And a frequency limiter which passes only the waveform and passes the input signal as it is when a frequency lower than the set frequency is inputted. According to the present invention, since the frequency of the critical conduction mode is abnormally generated due to the short circuit of the secondary side, the primary side energy is excessively transferred to the secondary side by operating at a high frequency, And the like can be prevented.

Description

TECHNICAL FIELD [0001] The present invention relates to a frequency control circuit for driving an LED,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency control circuit for driving LEDs, and more particularly, to a frequency control circuit for LED driving that prevents destruction and fire of a primary circuit through frequency control at the time of a secondary short- .

Recently, the use of LEDs is increasing, and the role of power supply, which plays an important role in the reliability of LED driving, is also becoming important.

Switching Mode Power Supply (SMPS), as an example of a power supply unit, converts AC power supplied from the outside into DC power and supplies the AC power to electronic devices including LEDs. The switching power supply is small in size, light weight, low loss, and high efficiency because the switching element operates in the switching mode because of its low power loss and the transformer uses a high frequency transformer. It can be used in areas where the input voltage is different without changing the constants.

On the other hand, there are Forward, Flyback, cuk, inverter rectifier type converters which are used in switching power supply. Flyback converter method, which is an insulation method for relatively small and medium output power, is mainly used for LED driving.

Here, a conventional flyback converter method for LED driving will be described.

1 is an LED drive circuit using a conventional flyback structure.

Referring to FIG. 1, the LED driving circuit includes a Critical Mode Power factor correcting driving unit 1 for controlling a constant voltage / constant current for driving an LED, A flyback converter unit 2 for isolating the first and second loads with a transformer in order to solve a safety problem in which an electric shock may occur due to a large voltage applied between the voltage and the ground, And an LED output unit 3 grounded.

Here, the operation of the critical mode (Critical Conduction Mode) is described in Korean Patent Publication No. 2012-35080 (published on March 13, 2012) and http://blog.naver.com/PostView.nhn?blogId=chungis1&logNo=70102253393 .

In the use of the LED driving circuit constructed as described above, the fly-back converter unit 2 is used to insulate the first and second phases, the ground of the LED output unit 3 is grounded, It is possible to prevent electric shock due to the touch of the LED output unit 3. [ In recent years, using a Buck type converter using a PFC (Power Factor Correct), the LED function is performed, and the flicker and the electric shock problem are solved.

On the other hand, the operating frequency for LED driving is usually 20KHz to 200KHz.

However, when a short occurs in the secondary side, the energy of the primary side Np can not be transmitted to the secondary side Ns, and LC resonance occurs in the auxiliary winding Naux. The frequency increases from several hundreds KHz to MHz according to the LC resonance and the circuit detects the frequency of the ZCD (Zero Current Detect) terminal of the critical mode power factor compensation driving unit 1 corresponding to the zero voltage, . That is, as the driving frequency is detected in the critical conduction mode, the operating frequency of the driving unit 1 operates in accordance with the resonance frequency. As a result, excessive heat is generated at the primary side of the flyback converter unit 2 as the normal frequency zero is detected and the operation frequency is higher than that when the switching frequency is determined. As a result, the critical mode power factor correction driving unit 1 is destroyed There is a problem that a fire may occur.

Korean Registered Patent Publication No. 1997-0022719 (published on May 30, 1997) KoreaMickUp Open Patent Publication No. 2012-35080 (Published on April 13, 2012)

SUMMARY OF THE INVENTION It is an object of the present invention to provide a critical-mode power factor correction driving unit that includes a circuit for limiting a maximum operating frequency outside a normal operating range, And to prevent the destruction and fire of the primary side circuit at the time of short circuit (Short).

According to an aspect of the present invention, there is provided a frequency control circuit for driving an LED, comprising: a reference time generator for generating a reference time for determining a period of a frequency to be limited; And a frequency limiting unit that passes only a limited waveform corresponding to the reference time when a signal higher than the set frequency is input and passes the input signal as it is when a frequency lower than the set frequency is inputted.

The reference time generator generates a pulse for a reference time in synchronization with a rising edge of the input signal, performs a self reset, and repeats the operation in synchronization with the input signal.

The input signal is a signal input to a ZCD (Zero Current Detect) terminal for using a critical mode (Critical Conduction Mode), and the output of the frequency limiter is outputted to the LED driver.

Wherein the reference time generator comprises: a first flip-flop for outputting a high level signal at the rising edge of the input signal input to the clock terminal; A first transistor connected to a gate terminal to be turned on in response to a low level signal which is a complement signal of the first flip-flop; A second transistor connected to a gate terminal to be turned off in response to a low level signal which is a complement signal of the first flip-flop; A capacitor charged by a constant current source in response to the turn-on of the first transistor; And a gate terminal connected to a drain terminal of the first transistor, a drain terminal of the first transistor, and a drain terminal of the second transistor. The high-level signal is output from the constant current source, A third transistor connected to one end of the capacitor; A first logical product operator in which the output of the first flip-flop is input at one end and the other end is connected to a drain terminal of the third transistor; A first delay element for delaying an output of the first logical product operator; And an output terminal connected to the enable terminal of the first flip-flop, wherein the output of the first AND gate is input at one end, the output of the first delay element is inverted and input at the other end, Includes one logical OR operator.

The frequency limiting unit may include: a second delay element for delaying the input signal; A second flip-flop that receives a signal output from the second delay element at a clock terminal and is synchronized with a rising edge; A third flip-flop for receiving a signal output from the second flip-flop, an output of the second delay element being input to a clock terminal through a first inverting element and being synchronized with a falling edge; A second logical product operator in which a signal output from the third flip-flop is input to one end via a second inversion element and a signal output from the second flip-flop is input to the other end; The output of the second AND gate is input at one end, the output (Tref) of the first AND gate is input at the other end, the output is inverted and input to the enable terminals of the second flip-flop and the third flip- A second OR operator; And a third AND gate that receives the output of the second AND gate at one end and receives the input signal at the other end to output an operation result.

As described above, according to the LED driving frequency control circuit of the present invention, the secondary side is short-circuited and the frequency of the critical conduction mode is unstable, so that it operates at a high frequency and the energy of the primary side is excessively It is possible to prevent breakage of the circuit and fire.

1 is an LED drive circuit using a conventional flyback structure.
2 is a conceptual diagram of a frequency control circuit for driving LEDs according to an embodiment of the present invention.
3 is a block diagram of a control circuit of the LED driving frequency control circuit according to the embodiment of the present invention.
FIG. 4 is an operation waveform diagram when a normal signal is input in FIG.
FIG. 5 is an operation waveform diagram when an abnormal signal is input in FIG.

The present invention can be applied to an LED driving method of a flyback structure including a critical conduction mode and includes means for limiting a maximum operating frequency.

The means for limiting the maximum operating frequency of the present invention includes a reference time generator for generating a reference time for determining one period of a frequency to be limited, And passes the input signal as it is when a frequency lower than the set frequency is input.

The reference time generator of the present invention starts time at the rising edge of the input signal, and the signal operates at a low level after the set time. Then, the reference time generator maintains the low level until the rising edge of the input signal while maintaining the low level until the input signal is applied again after resetting the set time.

The frequency limiting unit of the present invention includes a flip-flop that operates by receiving a delayed input signal and operates by receiving a delayed input signal and a flip-flop that operates by receiving an inverted signal of the delayed input signal.

The present invention can constitute a circuit for limiting the frequency between the ZCD (Zero Current Detect) terminal of the critical mode power factor compensation driving unit and the final DRV.

As described above, the present invention is characterized in that after setting a reference time for restricting a fast signal out of the normal operation range, only the minimum necessary signal corresponding to the reference time is applied to the DRV.

Hereinafter, the LED driving frequency control circuit of the present invention will be described in detail with reference to the accompanying drawings.

2 is a conceptual diagram of a frequency control circuit for driving LEDs according to an embodiment of the present invention.

Referring to FIG. 2, the LED driving frequency control circuit of the present invention includes a reference time generation unit 4 for generating a reference time for determining one period of a frequency to be limited, And a frequency limiter 5 for passing only the limited waveform (first waveform) corresponding to the reference time and passing the input signal IN as it is when a frequency lower than the set frequency is inputted.

Here, the reference time generator 4 generates a pulse for a reference time in synchronization with a rising edge of the input signal, performs a self reset, and repeats the operation in synchronization with the input signal again do.

3 is a block diagram of a control circuit of the LED driving frequency control circuit according to the embodiment of the present invention.

Referring to FIG. 3, the reference time generator 4 includes a first flip-flop 41 for outputting a high level signal at a rising edge of an input signal input to a clock terminal, A first transistor M1 connected to the gate terminal so as to turn on in response to a low level signal which is a complement signal of the flip flop 41 and a second transistor M1 connected to the gate terminal in response to a low level signal which is a complement signal of the first flip flop 41 A capacitor C which is charged by a constant current source in response to the turn-on of the first transistor M1, and a high level signal is outputted by a constant current source And a gate terminal connected to a drain terminal of the first transistor M1, a drain terminal of the second transistor M2, and a capacitor C connected to the drain terminal of the first transistor M1, A third transistor M3 connected at one end, A first AND gate 42 in which the output of one flip flop 41 is input at one end and the other end is connected to the drain terminal of the third transistor M3, A first delay element 43 for delaying the output of the first delay element 43 and a second delay element 43 for delaying the output of the first delay element 43 and the output of the first logical multiplication operator 42, (OR gate) 44 whose Re_start signal is inverted and input to the enable terminal of the first flip-flop 41.

On the other hand, the frequency limiting section 5 includes a second delay element 51 for delaying the input signal, a second flip-flop 51 for inputting a signal output from the second delay element 51 to the clock terminal, Flop 52 and the output of the second delay element 51 are input to the clock terminal via the first inverting element 53 and the output of the second flip- 3 flip-flop 54 and the signal output from the third flip-flop 54 are input to one end via the second inverting element 55 and the signal output from the second flip-flop 52 is input to the other end The outputs of the second AND gate 56 and the second AND gate 56 are input at one end and the output Tref of the first AND gate 42 is input at the other end, A second OR operator 57 input to the enable terminals of the second flip-flop 52 and the third flip-flop 54, and an output of the second AND operator 56 And a third logical product operator 58 for inputting the input signal at the other end and outputting the operation result.

Here, the input signal IN may be a signal input to the ZCD (zero current detect) terminal of the critical mode power factor correction driving unit 1, and the output signal OUT may be a signal output to the DRV terminal.

The first, second and third flip-flops 41, 52 and 54 are D flip-flops, the first transistor M1 is a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) The second transistor M2 and the third transistor M3 are N-type MOSFETs.

Hereinafter, the operation of the LED driving frequency control circuit constructed as described above will be described.

First, when the input signal is applied, the reference time generator 4 generates an output N1 of the first flip-flop 41 at the rising edge and a low-level signal at the output N2 at the rising edge. By this signal, the first transistor M1 is turned on and the second transistor M2 is turned off. At this time, the capacitor C starts to be charged by the constant current source Isrc, and the voltage of N3 rises. Accordingly, when the voltage of N4 is in the high level state and the voltage of N3 rises due to the charging and reaches the threshold voltage of the third transistor M3, the voltage becomes low level. That is, since N1 and N4 are in the high level state until the time of starting the charging and operating the third transistor M3, the output of the third transistor M3 is maintained at the high level by the first logical product operator 42 The output (Tref) of the first logical product operator (42) becomes low level to determine the time of Tref. Thus, Tref changes to a high level when the input signal IN is input and to a low level when N4 is changed by N3. When Tref is changed to a low level, the signal is delayed and inverted through the first delay element 43 and passes through the first OR gate 44, thereby generating a Re_start signal falling to a low level for a delayed time. This signal configures the circuit to produce a Re_start pulse at the falling edge of Tref. This operation repeats the operation of generating and resetting the signal period of the constant Tref in synchronization with the rising edge of the input signal (IN) frequency.

Subsequently, the frequency limiting section 5 uses a signal passed through the second delay element 51 to operate on the basis of the Tref, and outputs the synchronized signal to the rising edge of the input signal IN via the second delay element 51 The second flip-flop 52 and the third flip-flop 53 synchronized with the falling edge. The output of each of the flip-flops 52 and 53 is maintained at a high level at the output of the second AND gate 56 only during a period in which N5 is at a high level and N7 is at a low level, The output signal OUT is generated from the third logical product operator 58 so that the output is made only in the high level section of Tref. By making N8 low level at all times except the first high level interval of the input signal, a reset is made, so that the input signal is not output to the output signal.

FIG. 4 is an operation waveform diagram when a normal signal is input in FIG. 3, and FIG. 5 is an operation waveform diagram when an abnormal signal is input in FIG.

FIG. 4 is a graph showing waveforms simulated in FIG. 3, in which waveforms longer than the Tref period are input, that is, when the normal frequency is input, the same waveform as that of the input signal is output. FIG. It can be seen that when a short waveform is input, that is, when a high frequency is input, only the first one is output.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention.

1: critical mode power factor compensation drive
2: flyback converter
3: LED output section
4: Reference time generating section
5:
Np: Number of primary winding of transformer
Ns: Number of secondary windings of the transformer
Naux: number of windings of auxiliary winding
Rstr: Initial starting resistance

Claims (5)

A frequency control circuit for driving an LED included in a critical mode correcting power factor correcting driver for controlling a constant voltage / constant current for driving LEDs,

A reference time generator for generating a reference time for determining a period of a frequency to be restricted for the input signal IN; And
When a signal higher than the set frequency is input, only a limited waveform corresponding to the reference time is passed through the output signal OUT. When a frequency lower than the set frequency is inputted, the input signal is directly passed through the output signal OUT A frequency limiter,

The input signal IN is input to the ZCD (Zero Current Detect) terminal of the critical mode power factor correction driving unit 1,
The output signal OUT is output from the driving (DRV) terminal of the critical mode power factor compensation driving unit 1,

The reference time generating unit generates the reference time through switching control in which a voltage charged in accordance with the input signal IN reaches a threshold voltage and a level is changed,
A Re_start pulse is generated at a falling edge of the reference time to perform a reset,
Wherein the reset operation is repeated after the reference time is generated in synchronization with a rising edge of the input signal.
delete delete The method according to claim 1,
The reference time generation unit may include:
A first flip-flop for outputting a high level signal at the rising edge of the input signal input to the clock terminal;
A first transistor connected to a gate terminal to be turned on in response to a low level signal which is a complement signal of the first flip-flop;
A second transistor connected to a gate terminal to be turned off in response to a low level signal which is a complement signal of the first flip-flop;
A capacitor charged by a constant current source in response to the turn-on of the first transistor;
And a gate terminal connected to a drain terminal of the first transistor, a drain terminal of the first transistor, and a drain terminal of the second transistor. The high-level signal is output from the constant current source, A third transistor connected to one end of the capacitor;
A first logical product operator in which the output of the first flip-flop is input at one end and the other end is connected to a drain terminal of the third transistor;
A first delay element for delaying an output of the first logical product operator; And
An output of the first AND gate is input at one end, an output of the first delay element is inverted and input at the other end, and an Re_start signal as an output is inverted to input to an enable terminal of the first flip- A frequency control circuit for driving an LED including an OR operation.
The method according to claim 1,
The frequency-
A second delay element for delaying the input signal;
A second flip-flop that receives a signal output from the second delay element at a clock terminal and is synchronized with a rising edge;
A third flip-flop for receiving a signal output from the second flip-flop, an output of the second delay element being input to a clock terminal through a first inverting element and being synchronized with a falling edge;
A second logical product operator in which a signal output from the third flip-flop is input to one end via a second inversion element and a signal output from the second flip-flop is input to the other end;
The output of the second AND gate is input at one end, the output (Tref) of the first AND gate is input at the other end, the output is inverted and input to the enable terminals of the second flip-flop and the third flip- A second OR operator; And
And a third AND gate which receives the output of said second AND gate and receives said input signal at the other end to output a result of the operation.

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