KR101636906B1 - Gate driving device and method of driving gate - Google Patents

Abstract

A gate driving device and a gate driving method capable of reducing power consumption of a display device are disclosed. The disclosed gate driving apparatus and gate driving method provide a current to be discharged to the next pixel row from the previous pixel row while selecting the next pixel row after selecting the previous pixel row. Therefore, the current discarded in the previous pixel row can be recycled in the next pixel row, and the current required to select each pixel row can be reduced. As a result, the power consumption of the display device employing the disclosed gate driving device and gate driving method can be reduced overall.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate driving device,

The present disclosure relates to a gate driving apparatus and a gate driving method, and more particularly, to a gate driving apparatus and a gate driving method capable of reducing power consumption of a display apparatus.

A representation of an image in a flat panel display device such as a liquid crystal display device (LCD) or the like is performed by sequentially selecting a pixel row to display an image and providing color information to each pixel of a selected pixel row in a column direction . In this way, an image of one frame is displayed, for example, by scanning an image by one pixel row from the upper pixel row to the lower pixel row. In this case, digital selection data such as ON / OFF is provided as the pixel row, and analog data such as color information is provided to the pixel column. The function of selecting such a pixel row and pixel column direction and providing data is performed in a display driver IC (DDI) arranged on the side and upper and lower sides of the display panel.

The display driver IC may have, for example, a row driver for controlling driving in the pixel row direction and a column driver for controlling driving in the pixel column direction. Attempts have been made to form a row driver on a display panel because the row driver can be implemented with a relatively simple digital switching circuit as compared to a column driver that processes analog signals.

On the other hand, each pixel is provided with a thin film transistor for switching ON / OFF of the pixel. The row driver is connected to the gate of the thin film transistor to apply a gate voltage to the thin film transistors in the selected pixel column. The row driver is also referred to as a gate driver circuit or a gate driver in this respect.

In recent years, the gate select time for one pixel line is decreasing due to the large area / high resolution of the display device. For example, in the case of a display device having a resolution of 1600 x 1200 and a frame rate of 60 Hz, 1200 pixel lines should be sequentially selected in only 1/60 second. Therefore, the gate selection time for one pixel row is only about 13 占 퐏. Accordingly, oxide thin film transistors having higher mobility than conventional amorphous silicon (a-Si) thin film transistors are increasingly used. In addition, the power consumption of the display device is increased to drive more pixels.

A gate driving device capable of reducing power consumption of a display device is provided.

Further, there is provided a gate driving method capable of reducing power consumption of a display device.

A gate driver according to one type comprises: a plurality of cascaded stages each having a set signal input terminal, a first clock input terminal, a second clock input terminal and an output terminal, respectively; A plurality of switches connected to deliver a residual current discharged at each of the stages to an output of the other stage subsequent thereto; And a switch control unit for controlling the closing operation of the plurality of switches.

For example, the plurality of switches may be connected between the output lines of two adjacent stages.

Here, the output terminal of each stage may be connected to the set signal input terminal of the other stage succeeding thereto.

If a signal is input through the set signal input terminal, each of the stages can be set to be capable of outputting a signal input from the first clock input terminal to the output terminal.

Further, when a signal is inputted through the second clock input terminal, each of the stages can be reset to a state before receiving the signal from the set signal input terminal.

For example, the residual current may be discharged through the output terminal of each stage along the path to the first clock input terminal of the stage.

The gate driving apparatus may further include a clock generator for generating a plurality of clocks to be input to the first clock input terminal and the second clock input terminal.

In one example, the clock generator may repeatedly generate three sequentially phase-shifted clock signals and input them to the first clock input terminal and the second clock input terminal of each stage.

In this case, each of the stages receives a pair of clock signals different from the pair of clock signals input to the other stage adjacent thereto.

In one example, the plurality of switches may be located within the clock generator.

For example, the plurality of switches include three switches, a first switch is disposed between a line of a first clock signal and a line of a second clock signal in a clock generator, a second switch is disposed between a line of a first clock signal and a line of a second clock signal, And the third switch may be disposed between the line of the first clock signal and the line of the third clock signal.

Also, the plurality of stages may have a configuration in which the first to third stages are repeated in order. In this case, the first stage receives the first clock signal from the first clock input terminal and the second clock input terminal The second stage receives the second clock signal from the first clock input terminal and receives the third clock signal from the second clock input terminal. The third stage receives the second clock signal from the first clock input terminal, 3 clock signal, and receives the first clock signal from the second clock input terminal.

Meanwhile, a gate driving method according to one type is a method in which a set signal is input to any one of a plurality of cascade-connected stages of a gate driving apparatus sequentially outputting pulses, step; Inputting a clock to one of the stages and outputting a pulse, and inputting a part of the output pulse as a set signal to the succeeding stage; Stopping the input of the clock to interrupt the output of the pulse and discharging the residual current; Transferring the residual current to be discharged to the output of the subsequent stage; Resetting and initializing any one of the stages; And outputting a pulse by inputting a clock to the succeeding other stage.

According to the disclosed gate driver and gate driving method, the current discharged from the previous pixel row can be provided to the next pixel row while the next pixel row is selected after the previous pixel row is selected. That is, the current discarded from the previous pixel row can be recycled in the next pixel row. Thus, the current required to select each pixel row can be reduced, and as a result, the power consumption of the display device can be reduced overall.

Hereinafter, a gate driving apparatus and a gate driving method will be described in detail with reference to the accompanying drawings. In the following drawings, like reference numerals refer to like elements, and the size of each element in the drawings may be exaggerated for clarity and convenience of explanation.

FIG. 1 shows a connection relationship between the disclosed gate driving apparatus 100 and a plurality of pixels 15 in a display panel. Referring to FIG. 1, a plurality of pixels 15 are arranged in a two-dimensional array in a display panel. Each pixel 15 is provided with a thin film transistor 16 for switching ON / OFF of the pixel 15. The gate of the thin film transistor 16 is connected to the corresponding gate line GL1 to GL4. For example, the gate lines GL1 to GL4 are arranged for each pixel row, and the gate of the thin film transistor 16 of the pixels 15 in one pixel row is connected to the same gate line GL1 to GL4 It is connected. The gate driving device 100 has outputs as many as the number of pixel rows, and the respective outputs thereof are transferred to the corresponding gate lines GL1 to GL4. The drain of the thin film transistor 16 is connected to the output of a column driver (not shown). The column driver has outputs as many as the number of pixels in one pixel row, and the respective outputs thereof are transferred to the corresponding signal lines SL1 to SL6.

In this structure, the gate driving apparatus 100 sequentially selects gate lines GL1 to GL4 from top to bottom in order to provide output pulses to the selected gate lines GL1 to GL4. Then, the pixels 15 in the pixel rows connected to the selected gate lines GL1 to GL4 are turned ON. Meanwhile, the column driver provides analog signals corresponding to the color information to be displayed in the respective pixels 15 which are turned on through the signal lines (SL1 to SL6) to the corresponding pixels (15).

As described in Fig. 1, the gate driving apparatus 100 sequentially provides pulses from the top to the bottom. In this regard, the gate driving apparatus 100 may be regarded as a kind of shift register. FIG. 2 is a block diagram showing an exemplary structure of a shift register for implementing such a gate driving apparatus 100. Referring to FIG.

2, the gate driving apparatus 100 of the shift register structure includes a clock generator 110, a plurality of cascaded stages 101 to 104, A plurality of switches C4 to C6 for delivering a current to be discharged at a subsequent stage to the output of the subsequent stage and a switch control unit 120 for controlling the closing operation of the plurality of switches C4 to C5 . Here, the clock generator 110 may be an internal component of the gate driving apparatus 100, but may be, for example, a clock generator in a display device. Therefore, the gate driving apparatus 100 may not have its own clock generator but may use an external clock generator. The clock generator 110 may, for example, repeatedly generate three sequentially phase-shifted clock signals C1-C3 to provide them to the respective stages 101-104.

Each of the plurality of cascaded stages 101 to 104 may have two clock input terminals 112 and 113, one input terminal 114 and one output terminal 115. Here, the first clock input terminal 112 may be a terminal receiving a signal to be output by each of the stages 101 to 104. The input terminal 114 is connected to the first clock input terminal 112 and the second clock input terminal 112. The input terminal 114 receives a set signal that makes each stage 101 to 104 output a signal input from the first clock input terminal 112 to the output terminal 115, Terminal. In addition, the second clock input terminal 113 may be a kind of reset terminal in which each of the stages 101 to 104 is in a state before receiving the signal from the input terminal 112. [

The output terminals 115 of the stages 101 to 104 are connected to the input terminals 114 of the subsequent stages 101 to 104 since the stages 101 to 104 are cascade-connected. For example, the output terminal 115 of the first stage 101 is connected to the input terminal 114 of the second stage 102, the output terminal 115 of the second stage 102 is connected to the input terminal 114 of the second stage 102, And is connected to the input terminal 114 of the amplifier 103. However, in the case of the first stage 101 at the front, the input signal is separately received because there is no preceding stage. That is, the gate driving apparatus 100 forcibly provides the input signal to the input terminal of the first stage 101 for the output operation of the first stage 101. [ The output terminals 115 of the stages 101 to 104 may be connected to the corresponding gate lines GL1 to GL4 in the display panel. Although only four stages 101 to 104 are shown in Fig. 2, in actuality, as many gate stages as the number of gate lines GL1 to GL4 in the display panel are provided in the gate driving device 100. Fig.

The plurality of stages 101 to 104 may all be composed of transistor circuits of the same structure having the same function. For example, when a signal is input from the input terminal 114, each of the stages 101 to 104 may be ready to output the signal input from the first clock input terminal 112 to the output terminal 115 . When a signal is input from the first clock input terminal 112, each of the stages 101 to 104 can output the input signal to the output terminal 115. A part of the signal output from the output terminal 115 is transferred to the input terminal 114 of the next stage, and the remaining part is transferred to the gate line of the corresponding pixel row. If the signal input from the first clock input terminal 112 is interrupted, the current remaining in the pixels 15 in the corresponding pixel row begins to discharge. For example, the residual current is partially discharged along the path from the output terminal 115 to the first clock input terminal 112 again. At this time, signals are input from the second clock input terminal 113 to each of the stages 101 to 104, and the remaining residual current can be discharged along the path to the first clock input terminal 112. At the same time, each of the stages 101 to 104 receiving the signal from the second clock input terminal 113 is initialized to a state before receiving the input signal from the input terminal 114.

The plurality of stages 101 to 104 are cascade-connected so that the above operation can be sequentially performed for each pixel row, and each of the stages 101 to 104 is connected to the adjacent stages 101 to 104 And receives a pair of clock signals different from the pair of input clock signals. 2, the first stage 101 receives the first clock signal C1 from the first clock input terminal 112, and the second clock input terminal 113 receives the second clock signal C1 from the second clock input terminal 113. As shown in FIG. 2, And receives the clock signal C2. The second stage 102 receives the second clock signal C2 from the first clock input terminal 112 and receives the third clock signal C3 from the second clock input terminal 113 . The third stage 103 receives the third clock signal C3 from the first clock input terminal 112 and receives the first clock signal C1 from the second clock input terminal 113 . The fourth stage 104 receives the first clock signal C1 from the first clock input terminal 112 and the second clock signal C1 from the second clock input terminal 113 in the same manner as the first stage 101, C2. Likewise, a fifth stage (not shown) subsequent to the fourth stage 104 receives a clock signal in the same manner as the second stage 102, and a sixth stage (not shown) The clock signal can be input in the same manner as the clock signal generator 103 shown in FIG. Therefore, it can be considered that the stages of the gate driving apparatus 100 are repeated from the first stage 101 to the third stage 103.

On the other hand, as described above, the residual current remaining in the pixels 15 of each pixel row can be discharged along the first clock input terminal 112 of each of the stages 101 to 104. The discharge current causes a waste of electric current, which may increase the power consumption of the display device. In the case of the gate driving apparatus 100 disclosed in FIG. 2, the switching control unit 120 may further include a plurality of switches C4 to C6 and a switch control unit 120 for reusing the discharged current. 2, a first switch (OUTPUT1) is connected between the output line OUTPUT1 of the first stage 101 of the gate driving apparatus 100 and the output line OUTPUT2 of the second stage 102, for example, C4 may be disposed. The second switch C5 may be disposed between the output line OUTPUT2 of the second stage 102 and the output line OUTPUT3 of the third stage 103 and the output of the third stage 103 A third switch C6 may be disposed between the line OUTPUT3 and the output line OUTPUT4 of the fourth stage 104. [ That is, the switches C4 to C6 are connected between the output lines of two adjacent stages. Further, a switch control unit 120 for individually controlling the closing operation of each of the switches C4 to C5 may be provided.

In this structure, by connecting the output of the current stage to the output of the succeeding stage, the current discharged at the present stage is partially supplied to the succeeding stage . ≪ / RTI > For example, when the signal input from the first clock input terminal 112 in the first stage 101 is interrupted and the discharge starts, the switch control unit 120 closes the first switch C4. A portion of the discharged current may then be provided to the output line OUTPUT2 of the second stage 102. [ Immediately before the second clock signal C2 is input to the second clock input terminal 113 of the first stage 101 and the first clock input terminal 112 of the second stage 102, 120 opens the first switch C4 to disconnect the connection between the first output line OUTPUT1 and the second output line OUTPUT2. This is to prevent the output from the second output line OUTPUT2 from being transferred to the first output line OUTPUT1. In this case, since a certain amount of current is already supplied to the pixel 15 through the second output line OUTPUT2, the output from the second stage 102 can be reduced accordingly. Subsequently, when the signal input from the first clock input terminal 112 is interrupted at the second stage 102 to start the discharge, the switch control unit 120 closes the second switch C5. A portion of the current discharged in the second stage 102 may then be provided to the output line OUTPUT3 of the third stage 103. [ Likewise, when the discharge is started at the third stage 103, the third switch C6 is closed so that a part of the current discharged at the third stage 103 is supplied to the output line OUTPUT4 at the fourth stage 104 can do.

3 is a timing chart showing the sequential operation of the gate driving apparatus 100 described above. Referring to FIG. 3, in order to apply a signal to the gate line of the first pixel row in the display device, the gate driving device 100 first provides an input signal to the input terminal 114 of the first stage 101. Then, the first stage 101 may be ready to output the signal input from the first clock input terminal 112 to the output terminal 115. The first clock signal C1 is input to the first stage 101 from the first clock input terminal 112 and the first stage 101 receives the input signal through the output terminal 115, To the line (OUTPUT1). At this time, a part of the output pulse of the first stage 101 is input to the input terminal 114 of the second stage 102. Thus, the second stage 102 may be ready to output a signal. When the input of the first clock signal C1 is interrupted, a part of the current discharged in the first stage 101 is supplied to the output line OUTPUT2 of the second stage 102 when the first switch C4 is closed .

The first switch C4 is then opened and the second clock signal C2 is applied to the second clock input terminal 113 of the first stage 101 and the first clock input terminal 112 of the second stage 102 . The remaining residual current in the first pixel row is then completely discharged through the first clock input terminal 112 of the first stage 101. At the same time, the second stage 102 outputs the input second clock signal C2 to the second output line OUTPUT2 via the output terminal 115. [ At this time, the total current applied to the second pixel row of the display device is the sum of the current discharged from the first stage 101 and the current from the output terminal 115 of the second stage 102. On the other hand, a part of the signal output to the second output line OUTPUT2 is input to the input terminal 114 of the third stage 103, so that the third stage 103 is ready to output a signal do. When the input of the second clock signal C2 is stopped, the second output line OUTPUT2 and the third output line OUTPUT3 are connected while the second switch C5 is closed. Then, a part of the current discharged in the second stage 102 is provided to the output line OUTPUT3 of the third stage 103. [

In this way, signals are sequentially output to the last stage, which is not shown. When the signal is output at the last stage, the image of one frame is completely displayed. Therefore, after the signal is output at the last stage, the gate driving apparatus 100 resumes the operation of providing the input signal to the input terminal 114 of the first stage 101 to display the image of the next frame do.

As described above, in the case of using the gate driving apparatus 100 shown in FIG. 2, during the selection of the next pixel row after selecting the previous pixel row, the current discharged from the previous pixel row is supplied to the next pixel row can do. Therefore, the current discarded in the previous pixel row can be recycled in the next pixel row, so that the current required to select each pixel row can be reduced. As a result, the power consumption of the display device can be reduced overall.

4 is a block diagram showing the structure of another example of the gate driving device 100 '. Referring to FIG. 4, a plurality of switches C4 to C6 for delivering a current discharged at a preceding stage to an output of a subsequent stage are disposed together in a clock generator 110 '. In FIG. 4, a switch control unit 120 (see FIG. 2) for controlling the closing operation of the plurality of switches C4 to C5 is omitted for the sake of convenience. In the example of FIG. 4, the switch controller 120 may also be included in the clock generator 110 ', but may be separate from the clock generator 110', as in the example of FIG. The structure and operation of the plurality of stages 101 to 104 cascaded in the gate driving device 100 'of FIG. 4 are the same as those described in FIG.

Referring to FIG. 4, the first switch C4 may be disposed within the clock generator 110 'between the line of the first clock signal C1 and the line of the second clock signal C2. The second switch C5 may be disposed between the line of the second clock signal C2 and the line of the third clock signal C3 in the clock generator 110 ' May be connected between the line of the first clock signal (C1) and the line of the third clock signal (C3). In the structure in which the switches C4 to C6 are connected in this manner, the gate driving apparatus 100 'shown in FIG. 4 can operate in the same manner as the gate driving apparatus 100 described with reference to FIGS. 2 and 3 have.

For example, if the input of the first clock signal C1 to the first clock input terminal 112 of the first stage 101 is interrupted, the residual current remaining in the pixel row is the first And is discharged through the clock input terminal 112. At this time, when the first switch C4 is closed, the line of the first clock signal C1 and the line of the second clock signal C2 are electrically connected to each other. The current discharged through the first clock input terminal 112 of the first stage 101 is supplied to the first clock input terminal 112 of the second stage 102 through the line of the second clock signal C2 . Since the second stage 102 has received an input signal from the output of the first stage 101, the discharged current flows through the output terminal 115 of the second stage 102 to the second output line OUTPUT2 Can be provided. The first switch C4 is then opened and the second clock signal C2 is applied to the second clock input terminal 113 of the first stage 101 and the first clock input terminal 112 of the second stage 102, The second stage 102 outputs the inputted second clock signal C2 to the second output line OUTPUT2 via the output terminal 115. [ At this time, the total current applied to the second pixel row of the display device is the sum of the current discharged from the first stage 101 and the output of the second stage 102.

When the input of the second clock signal C2 is stopped at the first clock input terminal 112 of the second stage 102 and the second switch C5 is closed, The lines of the third clock signal C3 are electrically connected to each other. In this case, the current discharged through the first clock input terminal 112 of the second stage 102 flows through the line of the second clock signal C2 and the line of the third clock signal C3 to the third stage 103 to the first clock input terminal 112 thereof. Similarly, when the input of the third clock signal C3 is stopped at the first clock input terminal 112 of the third stage 103, when the third switch C6 is closed, the line of the first clock signal C1 The lines of the third clock signal C3 are electrically connected to each other. In this case, the current discharged through the first clock input terminal 112 of the third stage 102 flows through the line of the third clock signal C3 and the line of the first clock signal C1 to the fourth stage 104, respectively.

Up to now, exemplary embodiments of a gate driving apparatus and a gate driving method have been described and shown in the accompanying drawings to assist in understanding the present invention. It should be understood, however, that such embodiments are merely illustrative of the present invention and not limiting thereof. And it is to be understood that the invention is not limited to the details shown and described. Since various other modifications may occur to those of ordinary skill in the art.

1 shows a connection relationship between a gate driving device and a plurality of pixels.

2 is a block diagram showing an exemplary structure of a gate driving device.

3 is a timing chart for explaining the operation of the gate driving apparatus shown in Fig.

4 is a block diagram showing an exemplary structure of another gate driving device.

Description of the Related Art

15 ..... pixel 16 ..... thin film transistor

100 .... Gate driving device 100 '.... Gate driving device

101, 102, 103, 104 .... stage

101 ', 102', 103 ', 104' .... stage

110 .... clock generator 112,113 ... clock input terminal

114 .... input terminal 115 .... output terminal

120 .... switch control section

Claims (15)

A plurality of cascaded stages each having a set signal input terminal, a first clock input terminal, a second clock input terminal and an output terminal, respectively; A plurality of switches connected to deliver a residual current discharged at each of the stages to an output of the other stage subsequent thereto; And And a switch control unit for controlling the closing operation of the plurality of switches, Each switch being connected between the output terminals of two adjacent stages and two different output lines respectively connected thereto. delete The method according to claim 1, And the output terminal of each stage is connected to the set signal input terminal of the other stage succeeding thereto. The method of claim 3, When a signal is input through the set signal input terminal, each of the stages becomes a state capable of outputting a signal input from the first clock input terminal to the output terminal. 5. The method of claim 4, And when the signal is input through the second clock input terminal, each of the stages is reset to a state before receiving the signal from the set signal input terminal. 6. The method of claim 5, And the residual current is discharged along the path from the output terminal of each stage to the first clock input terminal of the stage. The method according to claim 1, And a clock generator for generating a plurality of clocks to be input to the first clock input terminal and the second clock input terminal. 8. The method of claim 7, Wherein the clock generator repeatedly generates three clock signals sequentially phase-shifted and inputs the clock signals to the first clock input terminal and the second clock input terminal of each stage. 9. The method of claim 8, Wherein each of the stages receives a pair of clock signals different from a pair of clock signals input to the other adjacent stage. A plurality of cascaded stages each having a set signal input terminal, a first clock input terminal, a second clock input terminal and an output terminal, respectively; A plurality of switches connected to deliver a residual current discharged at each of the stages to an output of the other stage subsequent thereto; A switch control unit for controlling the closing operation of the plurality of switches; And And a clock generator for generating a plurality of clocks to be input to the first clock input terminal and the second clock input terminal, Wherein the clock generator is configured to repeatedly generate three clock signals sequentially phase-shifted and to input the first clock input terminal and the second clock input terminal of each stage, Wherein the plurality of switches are disposed in the clock generator. 11. The method of claim 10, The plurality of switches including three switches, wherein the first switch is arranged between the line of the first clock signal and the line of the second clock signal in the clock generator, the second switch is arranged between the line of the second clock signal and the line of the second clock signal, 3 clock signal, and the third switch is disposed between the line of the first clock signal and the line of the third clock signal. 12. The method of claim 11, The first stage receives the first clock signal from the first clock input terminal, receives the second clock signal from the second clock input terminal and receives the second clock signal from the second clock input terminal The second stage receives the second clock signal from the first clock input terminal and receives the third clock signal from the second clock input terminal, the third stage receives the third clock signal from the first clock input terminal, And a first clock signal from the second clock input terminal. 13. The method of claim 12, The output terminal of each stage is connected to the set signal input terminal of the other stage succeeding thereto, When a signal is input through the set signal input terminal, each of the stages becomes a state capable of outputting a signal input from the first clock input terminal to the output terminal, When a signal is inputted through the second clock input terminal, each of the stages is reset to a state before receiving the signal from the set signal input terminal, And the residual current is discharged along the path from the output terminal of each stage to the first clock input terminal of the stage. A step of inputting a set signal to any one of a plurality of cascade-connected stages of a gate driving apparatus for sequentially outputting a pulse so that a pulse can be outputted when a clock is input; Inputting a clock to one of the stages and outputting a pulse, and inputting a part of the output pulse as a set signal to the succeeding stage; Stopping the input of the clock to interrupt the output of the pulse and discharging the residual current; Transferring the residual current to be discharged to the output of the subsequent stage; Resetting and initializing any one of the stages; And And inputting a clock to the succeeding other stage to output a pulse. The method according to claim 1, The plurality of stages including neighboring first and second stages, The plurality of switches including a first switch connected between the output line of the first stage and the output line of the second stage, When a signal input from the first clock input terminal is interrupted and a discharge is started at the first end, the switch control unit controls the switch so that a part of the current discharged at the first end is supplied to the output line of the second end, 1 switch, and immediately before the second clock signal is input to the second clock input terminal of the first stage and the first clock input terminal of the second stage, the switch control section opens the first switch, And disconnects the connection between the first output line and the second output line.

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