JP4759908B2 - Flat display device - Google Patents

Description

  The present invention relates to a flat display device and can be applied to, for example, a liquid crystal display device in which a drive circuit is integrally formed on an insulating substrate. The present invention drives a signal line by a source follower circuit using PMOS or NMOS and sets the potential of the signal line to a constant potential at a constant period so as to correspond to the driving of the signal line. Thus, the configuration can be simplified and miniaturized.

  In recent years, in a liquid crystal display device which is a flat display device applied to a portable terminal device such as a PDA or a mobile phone, a driving circuit for the liquid crystal display panel is integrated on a glass substrate which is an insulating substrate constituting the liquid crystal display panel. What is integrated and configured is provided.

  That is, in this type of liquid crystal display device, a display unit is formed by arranging pixels by a liquid crystal cell, a polysilicon TFT (Thin Film Transistor) which is a switching element of the liquid crystal cell, and a storage capacitor in a matrix shape. The display unit is driven by various drive circuits arranged around the display unit to display various images. In a liquid crystal display device, as disclosed in Japanese Patent Application Laid-Open No. 7-295521, etc., a precharge process is performed, for example, for each line, the signal line of each pixel is set to a predetermined potential to fill a storage capacitor. After discharging, each pixel is driven by an analog signal based on gradation data indicating the gradation of each pixel, thereby effectively avoiding deterioration of the liquid crystal and displaying a desired image.

  In the liquid crystal display device, the pixels formed in the display unit are sequentially selected in units of lines by driving the gate lines by the vertical driving circuit while performing the precharge process. Gradation data indicating gradation is sequentially sampled cyclically by a horizontal drive circuit to perform digital-to-analog conversion processing in units of lines, and each signal line is driven by this digital-to-analog conversion result and selected by the gate line The pixel is driven.

  In an analog buffer circuit used for driving a signal line based on such a digital-analog conversion result, a source follower circuit using a P-channel MOS (hereinafter referred to as PMOS) and a source using an N-channel MOS (hereinafter referred to as NMOS) have been conventionally used. The signal line is driven using a PMOS source follower circuit or an NMOS source follower circuit in accordance with the polarity setting related to the precharge processing.

  By the way, when one analog buffer circuit is composed of a PMOS source follower circuit and an NMOS source follower circuit as described above, the occupied area on the substrate becomes large, and there is a problem that the size of the liquid crystal display device increases accordingly. In particular, in the case of using a low-temperature polysilicon TFT, the occupied area is increased due to the rough design rule, and in the liquid crystal display device, there is a problem that a so-called frame width is increased.

On the other hand, in a liquid crystal display device in which a drive circuit is integrated on an insulating substrate of such a liquid crystal display panel, it is used for a mobile phone or the like, and a simplified configuration and a reduction in size are required. ing.
Japanese Patent Laid-Open No. 7-295521

  The present invention has been made in consideration of the above points, and an object of the present invention is to propose a flat display device capable of simplifying and downsizing the configuration as compared with the conventional one.

  In order to solve such a problem, in the invention of claim 1, when applied to a flat display device, driving of a signal line by an analog signal is driving of a signal line by a source follower circuit by PMOS or a source follower circuit by NMOS, The potential of the signal line is set to a constant potential at a constant period so as to correspond to the driving of the signal line by the source follower circuit by PMOS or the source follower circuit by NMOS.

  According to the configuration of the first aspect, the driving of the signal line by the analog signal is the driving of the signal line by the source follower circuit by PMOS or the source follower circuit by NMOS, and the signal line by the source follower circuit by PMOS or the source follower circuit by NMOS If the signal line potential is set to a constant potential at a constant cycle so as to correspond to the drive, the signal line drive by the analog signal is executed between a predetermined potential based on the constant potential. As a result, the configuration of the analog buffer circuit used for driving the signal line can be simplified, and the configuration can be simplified and miniaturized as compared with the conventional configuration.

  According to the present invention, the configuration can be simplified and miniaturized as compared with the prior art.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment 1 FIG. 2 is a block diagram showing a liquid crystal display device according to Embodiment 1 of the present invention. In this liquid crystal display device 1, pixels are formed by a liquid crystal cell 2, a polysilicon TFT 3 that is a switching element of the liquid crystal cell 2, and a storage capacitor 4, and the display unit 6 is formed by arranging these pixels in a matrix. The In the liquid crystal display device 1, each pixel forming the display unit 6 is connected to a horizontal drive circuit 7 and a vertical drive circuit 8 through a signal line LS and a gate line LG, respectively, and the vertical drive circuit 8 sequentially selects the pixels. A desired image is displayed by setting the gradation of each pixel by a drive signal from the horizontal drive circuit 7.

  For this reason, the vertical drive circuit 8 sequentially drives the gate lines LG by timing signals output from a timing generation circuit (not shown), and sequentially selects pixels in line units in conjunction with the processing in the horizontal drive circuit 7.

  The horizontal driving circuit 7 sequentially and cyclically takes in the gradation data D1 indicating the gradation of each pixel to generate a driving signal for each signal line LS. That is, in the horizontal drive circuit 7, the shift register 9 sequentially samples the gradation data D1 in a circular manner, thereby collecting the gradation data D1 in units of lines and collecting the gradation data D1 for one line in the horizontal blanking period. The data is output to the digital-analog converter circuit (DAC) 10 at a predetermined timing.

  The digital-analog conversion circuit 10 performs digital-analog conversion processing on the gradation data D1 output from the shift register 9, and outputs the result. The buffer circuit unit 11 drives each signal line LS with the output signal of the digital-analog conversion circuit 10, so that in the horizontal drive circuit 7, each pixel of the display unit 6 is displayed with a gradation corresponding to the gradation data D 1. A desired image can be displayed by driving. In this way, the buffer circuit unit 11 drives each signal line LS with the output signal of the digital-analog conversion circuit 10, and also drives each signal line LS so as to be used for so-called precharge processing.

  FIG. 3 is a block diagram showing in detail the digital-analog conversion circuit 10 and the buffer circuit unit 11 of the horizontal drive circuit 7. In the digital-analog converter circuit 10, the reference voltage generation circuit 15 generates and outputs a plurality of reference voltages V0 to V63 corresponding to gradations based on the gradation data D1, for example, by dividing a predetermined generation reference voltage by resistance. . The reference voltage selector 16 receives each of the plurality of reference voltages V0 to V63, and selectively outputs one of the reference voltages according to the gradation data D1 output from the shift register 9. Thus, the digital / analog conversion circuit 10 performs digital / analog conversion processing on the gradation data D1 by selecting a reference voltage corresponding to the gradation data D1.

  The buffer circuit unit 11 processes the output signal of the reference voltage selector 16 by each buffer circuit 18 operated by various timing signals output from the timing generation circuit 17 and outputs the processed signal to each signal line LS. In FIG. 3, symbols R, G, and B respectively indicate systems corresponding to red, green, and blue pixels.

  FIG. 1 is a connection diagram showing the configuration of the buffer circuit 18 in detail. In the buffer circuit 18, the output signal (indicated by reference numeral Vin) of the reference voltage selector 16 is input to the analog buffer circuit 20, and the corresponding signal line LS is driven by this input signal Vin. Further, during the horizontal blanking period, the potential of the signal line LS is switched together with the CS drive circuit (not shown) for each line to execute the precharge process. For this reason, the buffer circuit 18 includes an analog buffer circuit 20 that executes processing related to pixel gradation setting based on the input signal Vin, and a precharge circuit 21 that relates to precharging processing. In the following description, the switch circuit is composed of a PMOS transistor or an NMOS transistor, and the timing signal output from the timing generation circuit 17 is given a sign to each switch circuit, etc., to control each switch circuit, etc. A timing signal is shown.

  That is, in the liquid crystal display device 1, as shown in FIG. 4, the display unit 6 is driven by so-called line inversion, and precharge processing is executed during the horizontal blanking period. The terminal voltage of the storage capacitor 4 on the side where the transistor 3 is not provided (see FIG. 2, shown in FIG. 4 by the potential of the CS line, which is the wiring on the terminal side by the symbol CS), for each horizontal scanning period Switching between the ground level and the predetermined positive potential (FIG. 4A). Therefore, the analog buffer circuit 20 is disconnected from the signal line LS by a switch circuit 22 provided in the output stage during a period (hereinafter referred to as a precharge period) T1 in which the precharge process is executed (FIG. 4 ( F) and (G)).

In the precharge circuit 21, the switch circuits 23 and 24 connected to the signal line LS are turned on by the timing signals PCG1 and PCG2 output from the timing generation circuit 17, respectively, during substantially the first half of the precharge period T1. and set in the oFF state (FIG. 4 (B) ~ (E) ), thereby switching the potential of the CS line CS by connecting the CS line CS to the signal line LS CS driving circuit (Fig. 4 (H)). As a result, the precharge circuit 21 switches the potential of the CS line CS by effectively using the charges accumulated in the signal line LS and the storage capacitor 4, thereby reducing the overall power consumption. .

Further, subsequently, the timing signals PCG1 and PCG2 set the switch circuits 23 and 24 to the OFF state and the ON state, respectively (FIGS. 4B to 4E), thereby separating the signal line LS from the CS line CS, The potential of the signal line LS is set to the ground level (FIG. 4H). As a result, in this embodiment, the potential of the CS line CS is switched between the ground level and the predetermined positive potential, and the signal control LS is set to the ground potential in this precharge cycle. The signal line LS can be driven only on the positive power supply side, and the configuration of the analog buffer circuit 20 related to driving of the signal line LS can be simplified accordingly, as will be described later.

  The analog buffer circuit 20 includes a source follower including an NMOS transistor Q11, and a constant current circuit 26 shown in FIG. 5A is connected to the source of the NMOS transistor Q11. In this constant current circuit 26, a reference current source is formed by a PMOS transistor Q13 formed by inputting a timing signal xNcnt1 to the gate, and an NMOS transistor Q14 is connected in series to the PMOS transistor Q13. It is formed so that the reference current from the PMOS transistor Q13 flows.

Further, the constant current circuit 26 is provided with a sampling capacitor C3 between the gate and source of the NMOS transistor Q14, and a switch circuit 27 is provided for allowing a reference current from the PMOS transistor Q13 to flow into the sampling capacitor C3. ing. In the constant current circuit 26, the switch circuit 27 is turned on by a predetermined timing signal Ncnt 2, and the gate-source voltage Vgs of the NMOS transistor Q 14 in a state where the reference current from the PMOS transistor Q 13 is supplied to the NMOS transistor Q 14. Sampling is performed by the sampling capacitor C3, and thereafter, the sampling capacitor C3 is switched to an OFF state to hold the gate-source voltage Vgs sampled by the sampling capacitor C3.

The constant current circuit 26 through the switching circuit 28, the drain of the N MOS transistor Q14 is connected to the source of the NMOS transistor Q11 which constitutes a buffer circuit. The constant current circuit 26, the gate of the NMOS transistor Q14 in the sampling capacitor C3 by a predetermined timing signal Ncnt2 - sampling the voltage Vgs between the source, the reference current from the PMOS transistor Q13 is not output by the further timing signal xNcnt1 Thereafter, the switch circuit 28 is set to be switched on . As a result , the constant current circuit 26 causes the current due to the gate-source voltage Vgs sampled by the sampling capacitor C3 to flow out of the transistor Q11.

FIG. 6 is a time chart showing the transition of the timing signals xNcnt1, Nact, Ncnt2, the switch circuits 27 and 28 , and the transistor Q13 related to the control of the constant current circuit 26. Immediately after starting the operation in the initial state, the constant current circuit 26 holds the timing signal xNcnt1 at the H level and the transistor Q13 in the off state as shown in FIG. 5B (FIG. 6). (A) and (B)), and the timing signals Nact and Ncnt2 are held at the H level and the L level, respectively, whereby the switch circuits 27 and 28 are held in the off state and the on state, respectively (FIG. 6C). To (F)). As a result, the constant current circuit 26 is maintained in a state in which no current flows from the transistor Q11 in this case.

In the constant current circuit 26, the logical values of these timing signals xNcnt1, Nact, and Ncnt2 are simultaneously switched at a predetermined timing, whereby the switch circuits 27 and 28 are turned on and off, respectively, as shown in FIG. 5C. The transistor Q13 starts operating and starts outputting the reference current. Thereby, in the constant current circuit 26, the reference current I1 from the transistor Q13 charges the sampling capacitor C3 and flows out through the transistor Q14. The charging current of the sampling capacitor C3 gradually decreases as the voltage across the sampling capacitor C3 rises as a result of charging, and the gate-source voltage of the transistor Q14 required to cause the reference current I1 to flow out of the transistor Q14. When Vgs, the charging current does not flow into the sampling capacitor C3, and in this state, all of the reference current I1 from the transistor Q13 flows into the transistor Q14. Thus, in the constant current circuit 26, the reference current I1 flows into the transistor Q14, and the sampling capacitor C3 connected between the gate and the source of the transistor Q14 is charged with the reference current I1, whereby the reference current I is supplied to the transistor Q14. The gate-source voltage Vgs of the transistor Q14 required to flow I1 is set in the sampling capacitor C3.

The constant current circuit 26 switches the logic values of the timing signals xNcnt1, Nact, and Ncnt2 in this way, and when the period sufficient to hold the gate-source voltage Vgs of the transistor Q14 in the sampling capacitor C3 has elapsed, xNcnt1 and Ncnt2 return to their original logic values, whereby the supply of the reference current I1 is stopped, and the sampling capacitor C3 and the gate of the transistor Q14 are disconnected from the drain of the transistor Q14. Subsequently, the timing signal Nact returns to the original logical value, and the drain of the transistor Q14 is connected to the transistor Q11 that is the driving target of the constant current circuit 26. As a result, the constant current circuit 26 causes the current to flow out from the transistor Q11 by the gate-source voltage Vgs of the transistor Q14 by the reference current I1 set in the sampling capacitor C3, as shown in FIG. It is designed to function as a constant current circuit.

  Therefore, as described above with reference to FIG. 4, the liquid crystal display device 1 is required to function as a constant current circuit by executing precharge processing from the precharge period T1 provided in the horizontal blanking period. A period T3 in which the gate-source voltage Vgs of the transistor Q14 by the reference current I1 is set in the sampling capacitor C3 is assigned to the precharge period T1, and functions as a constant current circuit with the period T3 in which the gate-source voltage Vgs is set. The timing signals xNcnt1, Nact, and Ncnt2 are supplied so as to operate by repeating the period T4.

  In the analog buffer circuit 20 (FIG. 1), capacitors C1 and C2 each including switch circuits 31 and 32 are provided on the source side between the gate and source of the transistor Q11. Further, switch circuits 33, 34, 35 are provided on the side of the switch circuit 31, 32 of the gate of the transistor Q11 and the capacitors C1, C2, respectively, and a signal from the reference voltage selector 16 is connected to the other end of these switch circuits 33, 34, 35. Vin is input. The analog buffer circuit 20 is configured to cancel the variation of the transistor Q11 by switching the switch circuits 31 to 35 and drive the signal line LS by the input signal Vin.

  That is, as shown in FIG. 7 in comparison with the processing related to the precharge described above with reference to FIGS. 4 and 6 and the processing related to the constant current circuit 26, the buffer circuit 18 starts the precharge period T1 in the precharge circuit 21. Corresponding to (FIGS. 7A, 7J to 7L), the constant current circuit 26 starts the sampling process for the transistor Q13 (FIGS. 7C to 7E). In the analog buffer circuit 20, when these processes are started, all the switch circuits 22, 31 to 35 are set to an off state.

  Thereafter, when the constant current circuit 26 starts functioning as a constant current circuit after a lapse of the period T3, as shown in FIG. 8, the switch circuits 31, 32, and 33 are turned on. In FIG. 7, the ON state is indicated by the rise of the timing signals N1 to N5 for controlling the switch circuits 22, 31 to 35. As a result, the analog buffer circuit 20 samples the gate-source voltage VosA of the transistor Q11 in this state by the capacitors C1 and C2, and detects an offset when operating by the source follower.

  Subsequently, as shown in FIG. 9, the switch circuit 33 is switched to the off state, and the switch circuit 35 is switched to the on state. Thus, in the analog buffer circuit 20, the transistor Q11 is driven by the current from the constant current circuit 26 with the gate voltage of the transistor Q11 being offset by the voltage VosA sampled in the capacitor C1 with respect to the input voltage Vin. In operation, the gate-source voltage VosB of the transistor Q11 in this state is sampled by C2. As a result, the source voltage of the transistor Q11 becomes Vin + (VosA−VosB). As a result, the analog buffer circuit 20 detects the offset when operating by the source follower with the capacitor C2 while canceling the offset voltage previously detected by the capacitor C1.

  Subsequently, in the analog buffer circuit 20, as shown in FIG. 10, after all the switch circuits 22, 31 to 35 are turned off, the switch circuits 22, 34 are set to the on state as shown in FIG. The As a result, the buffer circuit 20 is configured to offset the input voltage Vin by the offset voltage detected by the capacitor C2 and drive the signal line LS by the source follower. The signal line LS is driven by reducing the offset voltage with respect to the input voltage Vin for accuracy, and the influence of the variation of the transistor Q11 is made sufficiently small.

  Thus, in the state shown in FIG. 11, the analog buffer circuit 20 outputs a source current from the transistor Q11 to the constant current circuit 26 and the signal line LS, and charges the storage capacitor 4 by the output of the source current. When the source potential rises due to charging of the storage capacitor 4, the source current output from the transistor Q11 is gradually reduced by that amount, and when the source potential becomes equal to the input potential Vin, the output of the source current signal line LS is stopped. Thus, the source current is output only to the constant current circuit 26, whereby the corresponding signal line LS is driven according to the input signal Vin.

In the analog buffer circuit 20, the period for driving the signal line LS in the state shown in FIG. 11 is set to a period after the precharge period T1.
(2) Operation of Embodiment 1 In the above configuration, in the liquid crystal display device 1 (FIG. 2), gradation data D1 indicating the gradation of each pixel is input from the controller for drawing or the like in the order of raster scanning. The gradation data D1 is sequentially sampled by the shift register 9 of the horizontal drive circuit 7 and collected in units of lines, and transferred to the digital / analog conversion circuit 10. The gradation data D1 is converted into an analog signal by the digital-analog conversion circuit 10, and each signal line LS of the display unit 6 is driven by the analog signal. Thus, in the liquid crystal display device 1, each pixel of the display unit 6 that is sequentially selected by the control of the gate line LG by the vertical drive circuit 8 is driven by the horizontal drive circuit 7, and an image based on the gradation data D 1 is displayed on the display unit 6. Is displayed.

  In the horizontal drive circuit 7 that drives the signal line LS of the display unit 6 in this way (FIG. 3), the reference signals V0 to V63 corresponding to the respective gradations of the gradation data D1 are generated by the reference voltage generation circuit 15, The reference voltage selector 16 selects the reference signals V0 to V63 according to each gradation data D1, whereby the gradation data D1 is subjected to digital-analog conversion processing, and the digital-analog conversion processing result is input to the buffer circuit 18. Thus, each signal line LS is driven.

  In the buffer circuit 18 (FIGS. 1 and 4), the analog buffer circuit 20 is disconnected from the signal line LS during the horizontal blanking period, and is opposite to the transistor 3 of the storage capacitor 4 by the setting of the switch circuit 23. In a state where the CS line CS on the side is connected to the signal line LS, the CS line CS is set to the positive side predetermined potential or the ground potential every horizontal scanning cycle. Thereafter, the CS line CS is disconnected from the signal line LS, and the signal line LS is held at the ground potential by the setting of the switch circuit 24.

  That is, in a predetermined line selected by the gate line LG at a predetermined timing, the CS line CS and the signal line LS are connected, and both end electrodes of the storage capacitor 4 related to this line are set to the ground level. While the signal line LS is set to the ground level and driven by the analog signal output from the reference voltage selector 16, in the subsequent line, the potential on both ends of the storage capacitor 4 is set to the positive predetermined potential. The signal line LS is set to the ground level and is driven by an analog signal output from the reference voltage selector 16, and in this manner, in the liquid crystal display device 1, a precharge process is performed by so-called line inversion driving. The deterioration of the cell 2 is prevented.

  Thus, after the CS line CS is connected to the signal line LS in this way and alternately set to the positive side predetermined potential or the ground potential for each horizontal scanning cycle, the signal line LS is set to the ground potential, whereby the signal line In the LS, a fixed potential corresponding to the configuration of the analog buffer circuit 20 including an NMOS source follower circuit is set at a fixed period related to the line inversion, whereby the liquid crystal display device 1 has a one-sided power supply based on the ground potential. Each pixel is driven only on the side, and the configuration of the analog buffer circuit 20 is simplified accordingly. That is, with this configuration, in the analog buffer circuit 20, it is sufficient to drive the signal line LS between the ground potential and the positive side predetermined potential. The analog buffer circuit 20 is configured by the NMOS source follower circuit configuration, and the negative side power supply from the ground potential. The configuration relating to the driving on the side can be omitted.

  Therefore, in the liquid crystal display device 1, the peripheral configuration of the display unit 6 can be simplified and the frame can be narrowed accordingly, and power consumption can be reduced.

  When the precharge process is completed in this way, in the liquid crystal display device 1, the corresponding signal line LS is driven by the analog buffer circuit 20, and the gray level of the pixel corresponding to the gray level corresponding to the gray level data D1. Is set.

  In driving the signal line LS, the analog buffer circuit 20 (FIGS. 7 to 11) performs a process of correcting the offset during the precharge processing period. By this process, the signal line LS is corrected by correcting the offset. Driven. That is, in the analog buffer circuit 20 (FIGS. 7 and 8), first, the transistor Q11 is driven by a constant current from the constant current circuit 26, and the gates and sources of the transistor Q11 are connected in parallel by setting the switch circuits 31 and 32. In this state, the digital-analog conversion circuit output Vin is supplied to the transistor Q11, whereby the gate-source voltage of the transistor Q11 related to this driving is set in the capacitors C1 and C2.

  Also, by setting the switch circuits 31, 33 and 35, the digital-analog conversion circuit output Vin is supplied to the gate of the transistor Q11 through the capacitor C2 which holds the gate-source voltage in this way, and thereby the capacitor The voltage between the gate and the source of the transistor Q11 in a state where the offset is canceled by the voltage held in C2 is set in the capacitor C1.

  In the analog buffer circuit 20 (FIGS. 10 and 11), when the precharge process is completed, the digital-analog converter circuit output Vin is offset by the voltage thus held in the capacitor C1 and supplied to the gate of the transistor Q11. Thus, each signal line LS can be driven by sufficiently suppressing the influence due to the variation of the transistor Q11.

  As a result, in the liquid crystal display device 1, the analog buffer circuit 20 is configured with a simple configuration using an NMOS source follower circuit, and accordingly, the frame is narrowed and power consumption is reduced.

When the signal line LS is driven in this way, the constant current circuit 26 of the analog buffer circuit 20 (FIG. 1) has a precharge period and an operation start period in the analog buffer circuit 20 of the transistor Q14. The sampling capacitor C3 connected between the gate and the source and the gate of the transistor Q14 are connected to the reference current source Q13 . The constant current circuit 26 further sets the voltage across the sampling capacitor C3 to the voltage between the gate and the source when the transistor Q14 is driven by the reference current I1, and then the sampling capacitor C3 and the gate of the transistor Q14 and the reference current The connection with the source Q13 is cut off, and the drain of the transistor Q14 is connected to the drive target . Thereby, the constant current circuit 26 drives the drive target with the current of the transistor Q14 by the gate-source voltage set in the sampling capacitor C3.

As a result, in the constant current circuit 26, even if the characteristics of the transistor Q14 vary, the drive target can be driven by the reference current I1 without being affected by the variation. In practice, the constant current circuit 26 of this, only variations in transistor Q13 of the reference current source Ru affect the output current.

Further, since it is possible to avoid the setting that increases the reference current value in order to reduce the variation, the entire power consumption can be reduced accordingly.
(3) Effect of Embodiment 1 According to the above configuration, the signal line is driven by the PMOS source follower circuit, and the potential of the signal line is set to a constant potential at a constant period so as to correspond to the driving of the signal line. Therefore, the configuration of the analog buffer circuit can be simplified, and accordingly, the configuration can be simplified and reduced in size compared to the conventional one, and in particular, a so-called narrow frame can be achieved.

  FIG. 12 is a block diagram showing a configuration of an analog buffer circuit applied to the liquid crystal display device according to Embodiment 2 of the present invention. The analog buffer circuit 40 includes a PMOS source follower circuit instead of the analog buffer formed by the NMOS source follower circuit according to the first embodiment. For this reason, in the liquid crystal display device according to the second embodiment, the ground potential and the negative side are replaced with the precharge processing related to the switching between the ground potential and the predetermined positive potential in the liquid crystal display device 1 according to the first embodiment. Precharge processing related to switching between predetermined potentials is executed.

  The analog buffer circuit 40 is configured by a PMOS transistor in place of the NMOS transistor, and the analog buffer circuit according to the first embodiment except that the connections of the respective parts to the positive power source and the negative power source are different corresponding to this configuration. 20 and the same configuration. As shown in FIG. 13, the constant current circuit 46 also includes a PMOS transistor in place of the NMOS transistor, and correspondingly, except that the connection of each part to the positive power source and the negative power source is different. The same configuration as the constant current circuit 26 of Example 1 is adopted.

  A time chart relating to the analog buffer circuit is shown in FIG. 14 in comparison with FIG. In FIG. 12, the description of the precharge circuit is omitted, and the connection relating to the storage capacitor and the like is indicated by reference numerals Csig and the like.

  Even when the analog buffer circuit is configured by the source follower circuit using PMOS as in this embodiment, the same configuration as that of the first embodiment can be obtained.

FIG. 15 is a block diagram showing a configuration of an analog-digital conversion circuit and a buffer circuit applied to the liquid crystal display device according to Embodiment 3 of the present invention. In the liquid crystal display device according to this embodiment, the analog buffer circuit having the same configuration as that of the analog buffer circuit 20 described above with respect to the first or second embodiment with respect to the reference voltages V0 to V63 output from the reference voltage generating circuit 15. After processing by 57, each reference voltage selector 16 makes a selection. In the precharge circuit, it is provided at the output of each reference voltage selector 16.

  Even if the present invention is applied to the case where the reference voltage generated by the reference voltage generation circuit 15 is processed by the analog buffer circuit as in this embodiment, the same effect as in the above-described embodiment can be obtained.

  In the above-described embodiment, the case where the analog buffer circuit is configured using the constant current circuit related to the sampling of the gate-source voltage has been described. However, the present invention is not limited thereto, and the current mirror circuit according to the conventional configuration is used. The present invention can be widely applied to a case where an analog buffer circuit is configured using a constant current circuit having a configuration.

  In the above-described embodiments, the case where the display unit is driven by line inversion has been described. However, the present invention is not limited to this and can be widely applied to the case of driving by field inversion.

  In the above-described embodiments, the case where the storage capacitor is precharged has been described. However, the present invention is not limited to this, and the present invention can be widely applied to a configuration in which the precharge process is omitted.

  In the above-described embodiments, the case where the signal line is driven with reference to the ground potential has been described. However, the present invention is not limited to this, and for example, between the negative potential and the ground potential with reference to the negative potential. The reference potential can be set to various potentials as required, for example, when the signal line is driven with the potential of.

  In the above-described embodiments, the case where the present invention is applied to a flat display device using a TFT liquid crystal in which a display unit or the like is formed on a glass substrate has been described. However, the present invention is not limited thereto, and the CGS (Continuous Grain) is used. It can be widely applied to various liquid crystal display devices such as (Silicon) liquid crystal, and various flat display devices such as EL (Electro Luminescence) display devices.

  The present invention can be applied to various flat display devices such as liquid crystal display devices using active elements such as TFT and CGS, and EL display devices.

It is a connection diagram which shows the buffer circuit applied to Example 1 of this invention. It is a block diagram which shows the liquid crystal display device which concerns on Example 1 of this invention. FIG. 3 is a block diagram illustrating a part of a horizontal drive circuit of the liquid crystal display device of FIG. 2. 5 is a time chart for explaining the operation of a precharge circuit in the buffer circuit of FIG. FIG. 2 is a connection diagram illustrating a constant current circuit applied to the buffer circuit of FIG. 1. 6 is a time chart for explaining the operation of the constant current circuit of FIG. 5. 2 is a time chart for explaining an operation of an analog buffer circuit in the buffer circuit of FIG. FIG. 2 is a connection diagram for explaining an operation of an analog buffer circuit in the buffer circuit of FIG. 1. FIG. 9 is a connection diagram for explanation following FIG. 8. FIG. 10 is a connection diagram for explanation following FIG. 9. FIG. 11 is a connection diagram for explanation following FIG. 10. It is a connection diagram which shows the analog buffer circuit applied to Example 2 of this invention. FIG. 13 is a connection diagram illustrating a constant current circuit applied to the analog buffer circuit of FIG. 12. 13 is a time chart for explaining the operation of the analog buffer circuit of FIG. It is a block diagram which shows a partial structure of the horizontal drive circuit applied to Example 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device, 2 ... Liquid crystal cell, 3, Q11-Q14C ... Transistor, 4 ... Holding capacity, 6 ... Display part, 7 ... Horizontal drive circuit, 8 ... Vertical drive circuit, 9 ... ... Shift register, 10... Digital / analog conversion circuit, 11... Buffer circuit section, 15... Reference voltage generation circuit, 16. 57 ... Analog buffer circuit, 21 ... Precharge circuit, 22, 23, 24, 31-35 ... Switch circuit, 26, 46 ... Constant current circuit, C1-C3, C3A-C3C ... Capacitor

Claims (2)

A display unit in which pixels are arranged in a matrix;
A vertical driving circuit for sequentially selecting pixels of the display portion by gate lines;
Gradation data indicating pixel gradation is sequentially sampled and converted into an analog signal, and the signal line of the display unit is driven by the analog signal, thereby integrating the horizontal drive circuit that drives the pixel selected by the gate line. A flat display device formed on a substrate,
The horizontal drive circuit has a source follower circuit made of a MOS FET, a buffer circuit having a constant current circuit, and a precharge unit connected to the signal line,
The drain of the MOS FET constituting the source follower circuit is grounded in an alternating manner, and an analog signal is output to the source based on the analog signal supplied to the gate of the MOS FET constituting the source follower circuit.
The constant current circuit is connected to the source of the MOS type FET constituting the source follower circuit, and sets the operating current of the MOS type FET.
In the period after the precharge period, the signal line is driven so as to correspond to the analog signal output from the source of the MOS type FET constituting the source follower circuit,
The precharge unit sets the potential of the signal line to a reference potential after setting the potential of the signal line to a precharge potential in a predetermined precharge period for every predetermined period for performing the precharge process,
Constant current circuit
A reference current source that outputs a reference current, a sampling capacitor that samples a voltage based on the reference current output from the reference current source in the first half of the precharge period, and a reference current that is output from the reference current source in the second half of the precharge period A transistor that sets a current based on the voltage sampled in the sampling capacitor as the operating current of the MOS type FET that constitutes the source follower circuit,
The sampling capacitor gate of the transistor - which is connected between the source,
The drain of the transistor is connected to a reference current source,
In the precharge period and the operation start period in the buffer circuit, the sampling capacitor and the gate of the transistor are connected to the reference current source,
After setting the voltage across the sampling capacitor to the voltage between the gate and the source when the transistor is driven by the reference current from the reference current source, the connection between the sampling capacitor and the gate of the transistor and the reference current source is cut off. A flat display device for driving a MOS FET by a transistor current by a gate-source voltage set in a sampling capacitor by connecting the drain of the transistor to a driving target. A display unit in which pixels are arranged in a matrix;
A vertical driving circuit for sequentially selecting pixels of the display portion by gate lines;
Gradation data indicating pixel gradation is sequentially sampled and converted into an analog signal, and the signal line of the display unit is driven by the analog signal, thereby integrating the horizontal drive circuit that drives the pixel selected by the gate line. A flat display device formed on a substrate,
The horizontal drive circuit has a source follower circuit made of a MOS FET, a buffer circuit having a constant current circuit, and a precharge unit connected to the signal line,
The drain of the MOS FET constituting the source follower circuit is grounded in an alternating manner, and an analog signal is output to the source based on the analog signal supplied to the gate of the MOS FET constituting the source follower circuit.
The constant current circuit is connected to the source of the MOS type FET constituting the source follower circuit, and sets the operating current of the MOS type FET.
In the period after the precharge period, the signal line is driven so as to correspond to the analog signal output from the source of the MOS type FET constituting the source follower circuit,
The precharge unit sets the potential of the signal line to a reference potential after setting the potential of the signal line to a precharge potential in a predetermined precharge period for every predetermined period for performing the precharge process,
Constant current circuit
A reference current source for generating a reference current; a MOS FET for current supply in which the gate is connected to the output side of the reference current source, and the operating current of the MOS FET constituting the source follower circuit is set by the current from the drain; A sampling capacitor connected between the gate and source of the current supply MOS FET, and between the connection point of the sampling capacitor and the gate of the current supply MOS FET and the output side of the reference current source A first switch provided between the source of the MOS FET constituting the source follower circuit and the drain of the current supply MOS FET, and a reference current by the reference current source Generating a signal for controlling the output timing of the first switch, the on / off timing of the first switch, and the on / off timing of the second switch And a timing generator,
The drain of the transistor is connected to a reference current source,
In the precharge period and the operation start period in the buffer circuit, the first switch is turned on, the sampling capacitor and the gate of the transistor are connected to the reference current source,
After setting the voltage across the sampling capacitor to the voltage between the gate and the source when the transistor is driven by the reference current from the reference current source, the first switch is turned off and the sampling capacitor and the gate of the transistor and the reference current By disconnecting the connection with the source and turning on the second switch to connect the drain of the transistor to the drive target, the transistor current is determined by the voltage between the gate and the source set in the sampling capacitor. Flat display device that drives

Images