KR101623514B1 - Iommu에 의해 아키텍트되는 tlb 지원 - Google Patents

Iommu에 의해 아키텍트되는 tlb 지원 Download PDF

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KR101623514B1
KR101623514B1 KR1020127024276A KR20127024276A KR101623514B1 KR 101623514 B1 KR101623514 B1 KR 101623514B1 KR 1020127024276 A KR1020127024276 A KR 1020127024276A KR 20127024276 A KR20127024276 A KR 20127024276A KR 101623514 B1 KR101623514 B1 KR 101623514B1
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KR20130009781A (ko
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앤드류 케겔
마크 훔멜
에리크 볼레인
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1081Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60Details of cache memory
    • G06F2212/6028Prefetching based on hints or prefetch instructions
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65Details of virtual memory and virtual address translation
    • G06F2212/654Look-ahead translation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Stored Programmes (AREA)
KR1020127024276A 2010-02-17 2011-02-16 Iommu에 의해 아키텍트되는 tlb 지원 Active KR101623514B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/707,341 US8244978B2 (en) 2010-02-17 2010-02-17 IOMMU architected TLB support
US12/707,341 2010-02-17
PCT/US2011/025075 WO2011103184A2 (en) 2010-02-17 2011-02-16 Iommu architected tlb support

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KR20130009781A KR20130009781A (ko) 2013-01-23
KR101623514B1 true KR101623514B1 (ko) 2016-05-23

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US (1) US8244978B2 (enExample)
EP (2) EP3486788A1 (enExample)
JP (1) JP5650766B2 (enExample)
KR (1) KR101623514B1 (enExample)
CN (1) CN103026348B (enExample)
WO (1) WO2011103184A2 (enExample)

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KR20220078132A (ko) 2020-12-03 2022-06-10 삼성전자주식회사 어드레스 변환을 수행하는 시스템 온 칩 및 이의 동작 방법
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JP2013519965A (ja) 2013-05-30
WO2011103184A2 (en) 2011-08-25
JP5650766B2 (ja) 2015-01-07
WO2011103184A3 (en) 2012-10-11
US20110202724A1 (en) 2011-08-18
EP3486788A1 (en) 2019-05-22
CN103026348A (zh) 2013-04-03
US8244978B2 (en) 2012-08-14
CN103026348B (zh) 2016-03-16
EP2537098B1 (en) 2018-11-21
KR20130009781A (ko) 2013-01-23
EP2537098A2 (en) 2012-12-26

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