CN103026348B - Iommu架构的tlb支持 - Google Patents

Iommu架构的tlb支持 Download PDF

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Publication number
CN103026348B
CN103026348B CN201180009059.1A CN201180009059A CN103026348B CN 103026348 B CN103026348 B CN 103026348B CN 201180009059 A CN201180009059 A CN 201180009059A CN 103026348 B CN103026348 B CN 103026348B
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Prior art keywords
address translation
translation information
memory
management unit
cache
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Chinese (zh)
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CN103026348A (zh
Inventor
安德鲁·克格尔
马克·赫梅尔
埃里克·博林
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/654—Look-ahead translation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Stored Programmes (AREA)
CN201180009059.1A 2010-02-17 2011-02-16 Iommu架构的tlb支持 Active CN103026348B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/707,341 2010-02-17
US12/707,341 US8244978B2 (en) 2010-02-17 2010-02-17 IOMMU architected TLB support
PCT/US2011/025075 WO2011103184A2 (en) 2010-02-17 2011-02-16 Iommu architected tlb support

Publications (2)

Publication Number Publication Date
CN103026348A CN103026348A (zh) 2013-04-03
CN103026348B true CN103026348B (zh) 2016-03-16

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Application Number Title Priority Date Filing Date
CN201180009059.1A Active CN103026348B (zh) 2010-02-17 2011-02-16 Iommu架构的tlb支持

Country Status (6)

Country Link
US (1) US8244978B2 (enExample)
EP (2) EP3486788A1 (enExample)
JP (1) JP5650766B2 (enExample)
KR (1) KR101623514B1 (enExample)
CN (1) CN103026348B (enExample)
WO (1) WO2011103184A2 (enExample)

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US10459847B1 (en) * 2015-07-01 2019-10-29 Google Llc Non-volatile memory device application programming interface
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Also Published As

Publication number Publication date
US20110202724A1 (en) 2011-08-18
JP5650766B2 (ja) 2015-01-07
CN103026348A (zh) 2013-04-03
JP2013519965A (ja) 2013-05-30
KR20130009781A (ko) 2013-01-23
WO2011103184A2 (en) 2011-08-25
EP3486788A1 (en) 2019-05-22
WO2011103184A3 (en) 2012-10-11
US8244978B2 (en) 2012-08-14
EP2537098A2 (en) 2012-12-26
EP2537098B1 (en) 2018-11-21
KR101623514B1 (ko) 2016-05-23

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