JP5650766B2 - Ｔｌｂサポート設計のｉｏｍｍｕ - Google Patents

Ｔｌｂサポート設計のｉｏｍｍｕ Download PDF

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Publication number
JP5650766B2
JP5650766B2 JP2012553997A JP2012553997A JP5650766B2 JP 5650766 B2 JP5650766 B2 JP 5650766B2 JP 2012553997 A JP2012553997 A JP 2012553997A JP 2012553997 A JP2012553997 A JP 2012553997A JP 5650766 B2 JP5650766 B2 JP 5650766B2
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address translation
translation information
cache
management unit
memory management
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JP2013519965A5 (enExample
JP2013519965A (ja
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ケーゲル アンドルー
ケーゲル アンドルー
ハメル マーク
ハメル マーク
ブーレン エーリヒ
ブーレン エーリヒ
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/654—Look-ahead translation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Stored Programmes (AREA)
JP2012553997A 2010-02-17 2011-02-16 Ｔｌｂサポート設計のｉｏｍｍｕ Active JP5650766B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/707,341 2010-02-17
US12/707,341 US8244978B2 (en) 2010-02-17 2010-02-17 IOMMU architected TLB support
PCT/US2011/025075 WO2011103184A2 (en) 2010-02-17 2011-02-16 Iommu architected tlb support

Publications (3)

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JP2013519965A JP2013519965A (ja) 2013-05-30
JP2013519965A5 JP2013519965A5 (enExample) 2014-04-03
JP5650766B2 true JP5650766B2 (ja) 2015-01-07

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JP2012553997A Active JP5650766B2 (ja) 2010-02-17 2011-02-16 Ｔｌｂサポート設計のｉｏｍｍｕ

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US (1) US8244978B2 (enExample)
EP (2) EP3486788A1 (enExample)
JP (1) JP5650766B2 (enExample)
KR (1) KR101623514B1 (enExample)
CN (1) CN103026348B (enExample)
WO (1) WO2011103184A2 (enExample)

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Also Published As

Publication number Publication date
KR20130009781A (ko) 2013-01-23
WO2011103184A2 (en) 2011-08-25
EP2537098A2 (en) 2012-12-26
US20110202724A1 (en) 2011-08-18
EP2537098B1 (en) 2018-11-21
KR101623514B1 (ko) 2016-05-23
EP3486788A1 (en) 2019-05-22
US8244978B2 (en) 2012-08-14
JP2013519965A (ja) 2013-05-30
WO2011103184A3 (en) 2012-10-11
CN103026348B (zh) 2016-03-16
CN103026348A (zh) 2013-04-03

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