KR101622311B1 - 적응가능한 수의 오픈 로우들을 갖는 메모리 디바이스 - Google Patents

적응가능한 수의 오픈 로우들을 갖는 메모리 디바이스 Download PDF

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KR101622311B1
KR101622311B1 KR1020157021212A KR20157021212A KR101622311B1 KR 101622311 B1 KR101622311 B1 KR 101622311B1 KR 1020157021212 A KR1020157021212 A KR 1020157021212A KR 20157021212 A KR20157021212 A KR 20157021212A KR 101622311 B1 KR101622311 B1 KR 101622311B1
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row
rows
command
memory
address
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KR20150104169A (ko
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지안 센
리용 왕
레우 추아- 오안
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0653—Monitoring storage devices or systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
KR1020157021212A 2013-01-08 2014-01-07 적응가능한 수의 오픈 로우들을 갖는 메모리 디바이스 Expired - Fee Related KR101622311B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/736,662 2013-01-08
US13/736,662 US9281036B2 (en) 2013-01-08 2013-01-08 Memory device having an adaptable number of open rows
PCT/US2014/010544 WO2014110050A1 (en) 2013-01-08 2014-01-07 Memory device having an adaptable number of open rows

Publications (2)

Publication Number Publication Date
KR20150104169A KR20150104169A (ko) 2015-09-14
KR101622311B1 true KR101622311B1 (ko) 2016-05-18

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Country Status (6)

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US (2) US9281036B2 (enExample)
EP (1) EP2943956B1 (enExample)
JP (1) JP5956089B2 (enExample)
KR (1) KR101622311B1 (enExample)
CN (1) CN104903962B (enExample)
WO (1) WO2014110050A1 (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9281036B2 (en) 2013-01-08 2016-03-08 Qualcomm Incorporated Memory device having an adaptable number of open rows
KR102106064B1 (ko) * 2013-07-11 2020-05-28 에스케이하이닉스 주식회사 반도체 장치 및 이의 제어 방법
CN106155577B (zh) * 2015-04-23 2019-03-26 华为技术有限公司 扩展内存的访问方法、设备以及系统
US10082964B2 (en) 2016-04-27 2018-09-25 Micron Technology, Inc Data caching for ferroelectric memory
CN108139994B (zh) * 2016-05-28 2020-03-20 华为技术有限公司 内存访问方法及内存控制器
CN108139992B (zh) * 2016-08-09 2020-06-16 华为技术有限公司 访问存储设备的方法和存储设备
GB2553338B (en) * 2016-09-02 2019-11-20 Advanced Risc Mach Ltd Serial communication control
KR102792986B1 (ko) * 2019-03-07 2025-04-11 에스케이하이닉스 주식회사 시스톨릭 어레이 및 프로세싱 시스템
KR102679774B1 (ko) * 2019-04-10 2024-06-28 에스케이하이닉스 주식회사 히스토리 기반 메모리 시스템 및 그 제어 방법
US11935601B2 (en) * 2019-08-14 2024-03-19 Supermem, Inc. Bit line sensing circuit comprising a sample and hold circuit
WO2022132475A1 (en) * 2020-12-17 2022-06-23 Micron Technology, Inc. Memory activation timing management
US11704049B2 (en) * 2021-02-11 2023-07-18 Micron Technology, Inc. Optimized command sequences
US11568932B2 (en) * 2021-02-22 2023-01-31 Micron Technology, Inc. Read cache for reset read disturb mitigation
US11775197B2 (en) * 2021-03-25 2023-10-03 Kyocera Document Solutions Inc. Single command for reading then clearing dynamic random access memory
US11600312B1 (en) 2021-08-16 2023-03-07 Micron Technology, Inc. Activate commands for memory preparation
KR20240076574A (ko) * 2022-11-22 2024-05-30 삼성전자주식회사 메모리 컨트롤러, 이를 포함하는 전자 시스템 및 메모리 액세스 제어 방법
WO2024182288A1 (en) * 2023-02-27 2024-09-06 Kove Ip, Llp Cache-coherent memory extension with cpu stall avoidance
CN117608498B (zh) * 2024-01-22 2024-10-18 北京象帝先计算技术有限公司 一种dram的访问处理方法、缓存控制模块及dram控制器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6061759A (en) 1996-02-09 2000-05-09 Apex Semiconductor, Inc. Hidden precharge pseudo cache DRAM
US6389514B1 (en) 1999-03-25 2002-05-14 Hewlett-Packard Company Method and computer system for speculatively closing pages in memory
US20080282028A1 (en) 2007-05-09 2008-11-13 International Business Machines Corporation Dynamic optimization of dynamic random access memory (dram) controller page policy

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0700050A3 (en) * 1994-08-17 1997-07-23 Oak Technology Inc Multi-page storage
GB2293668B (en) * 1994-09-30 1999-09-29 Advanced Risc Mach Ltd Accessing data memories
JP3248500B2 (ja) * 1998-11-12 2002-01-21 日本電気株式会社 半導体記憶装置およびそのデータ読み出し方法
JP3930195B2 (ja) * 1999-04-09 2007-06-13 株式会社ルネサステクノロジ データ処理システム
US6625685B1 (en) 2000-09-20 2003-09-23 Broadcom Corporation Memory controller with programmable configuration
JP2003108438A (ja) * 2001-09-28 2003-04-11 Supreme Magic:Kk データ処理装置
US7007133B2 (en) 2002-05-29 2006-02-28 Micron Technology, Inc. Synchronous memory open page register
US7082514B2 (en) * 2003-09-18 2006-07-25 International Business Machines Corporation Method and memory controller for adaptive row management within a memory subsystem
US7433258B2 (en) 2003-10-10 2008-10-07 Datasecure Llc. Posted precharge and multiple open-page RAM architecture
KR20050035699A (ko) * 2003-10-14 2005-04-19 삼성전자주식회사 메모리 시스템의 에너지 절감 방법 및 장치
US7162567B2 (en) 2004-05-14 2007-01-09 Micron Technology, Inc. Memory hub and method for memory sequencing
US7389402B2 (en) 2005-06-07 2008-06-17 Advanced Micro Devices, Inc. Microprocessor including a configurable translation lookaside buffer
US20070014168A1 (en) 2005-06-24 2007-01-18 Rajan Suresh N Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies
US7917676B2 (en) 2006-03-10 2011-03-29 Qualcomm, Incorporated Efficient execution of memory barrier bus commands with order constrained memory accesses
US7606988B2 (en) 2007-01-29 2009-10-20 International Business Machines Corporation Systems and methods for providing a dynamic memory bank page policy
US7958301B2 (en) 2007-04-10 2011-06-07 Marvell World Trade Ltd. Memory controller and method for memory pages with dynamically configurable bits per cell
US8184487B2 (en) * 2010-08-30 2012-05-22 Micron Technology, Inc. Modified read operation for non-volatile memory
WO2012116369A2 (en) 2011-02-25 2012-08-30 Fusion-Io, Inc. Apparatus, system, and method for managing contents of a cache
US9281036B2 (en) * 2013-01-08 2016-03-08 Qualcomm Incorporated Memory device having an adaptable number of open rows

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6061759A (en) 1996-02-09 2000-05-09 Apex Semiconductor, Inc. Hidden precharge pseudo cache DRAM
US6389514B1 (en) 1999-03-25 2002-05-14 Hewlett-Packard Company Method and computer system for speculatively closing pages in memory
US20080282028A1 (en) 2007-05-09 2008-11-13 International Business Machines Corporation Dynamic optimization of dynamic random access memory (dram) controller page policy

Also Published As

Publication number Publication date
EP2943956B1 (en) 2018-10-03
CN104903962A (zh) 2015-09-09
KR20150104169A (ko) 2015-09-14
WO2014110050A1 (en) 2014-07-17
EP2943956A1 (en) 2015-11-18
US20140195764A1 (en) 2014-07-10
US20160133306A1 (en) 2016-05-12
JP2016506009A (ja) 2016-02-25
CN104903962B (zh) 2017-08-25
US9343127B1 (en) 2016-05-17
US9281036B2 (en) 2016-03-08
JP5956089B2 (ja) 2016-07-20

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