KR101615101B1 - Clock recovery circuit and sampling signal generator including the same - Google Patents

Abstract

The clock recovery circuit includes a clock code detection unit and a clock signal generation unit. The clock code detection unit receives the transmission signal including the clock code, detects the edge of the clock code in the transmission signal in response to the clock window signal, and generates a clock transition signal based on the edge of the clock code. The clock signal generator generates a restored clock signal in response to the clock transition signal. The clock recovery circuit can accurately recover the clock signal from the clock embedded data.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a clock recovery circuit and a sampling signal generator including the clock recovery circuit.

The present invention relates to a clock recovery circuit, and more particularly, to a clock recovery circuit for recovering a clock signal from clock embedded data and a sampling signal generator including the same.

Serial interfaces are widely used for high-speed signal transmission between devices, between integrated circuits (ICs), between modules, or between systems. The serial interface can reduce the number of signal lines and can eliminate skew between signals as compared with a conventional interface for transmitting data in parallel through a plurality of signal lines.

Recently, a clock embedding technique has been studied in which a clock signal is transmitted together with data to a data signal line so as to further reduce the number of signal lines and speed up signal transmission. However, in the conventional interface system using clock embedding, data is encoded and transmitted at 8B / 10B or the like so as to have a continuous transition for transmission of a clock signal, and the receiving apparatus transmits the encoded signal to recover the clock signal transmitted through the data signal line There is a problem that data overhead is large and the circuit becomes complicated.

In order to solve the above problems, an object of the present invention is to provide a clock recovery circuit capable of accurately recovering a clock signal from clock embedded data.

Another object of the present invention is to provide a sampling signal generator including the clock recovery circuit.

In order to accomplish the object of the present invention, a clock recovery circuit according to embodiments of the present invention includes a clock code detection unit and a clock signal generation unit.

The clock code detection section receives a transmission signal including a clock code, detects an edge of the clock code in the transmission signal in response to a clock window signal, and generates a clock transition signal based on an edge of the clock code. The clock signal generator generates a restored clock signal in response to the clock transition signal.

In one embodiment, the clock code detecting section includes: a rising detector for detecting a rising edge of the clock code in the transmission signal to generate a rising edge detecting signal; a falling edge detecting unit for detecting a falling edge of the clock code in the transmission signal, A falling detector for generating a falling edge signal; a rising-falling determiner for determining whether the clock code has a rising edge or a falling edge to generate a rising-falling decision signal; and a rising- And a selector for selectively outputting the rising edge detection signal or the falling edge detection signal as a signal.

Wherein the rising detector includes a first latch that outputs the clock window signal as the rising edge detection signal when the clock window signal has a logic high level and the transmission signal has a logic high level, And a second latch for outputting the clock window signal as the falling edge detection signal when the clock window signal has a logic high level and the transmission signal has a logic low level, And a flip-flop for outputting the transmission signal as the rising-and-falling determination signal in response to a rising edge of the clock window signal, wherein the selector receives the rising-falling determination signal as a selection signal, In response to the determination signal, the rising edge detection signal or the falling edge detection signal The signal may comprise a multiplexer for selectively outputting.

In one embodiment, the clock generation unit may generate the restored clock signal that rises in response to the clock transition signal and falls in response to the delayed clock transition signal that delayed the clock transition signal.

In one embodiment, the clock generator may generate the restored clock signal that makes a rising transition in response to the clock transition signal and a falling transition in response to a clock falling signal received from the delay locked loop circuit.

In one embodiment, the clock recovery circuit may further include a delay unit that delays the transmission signal by a delay time of the clock code detection unit and the clock signal generation unit.

In one embodiment, the clock recovery circuit includes a clock output unit for selectively outputting the restored clock signal output from the clock signal generation unit or the transmission signal output from the delay unit in response to a lock detection signal, And a data output unit for selectively outputting the transmission signal output from the delay circuit in response to the lock detection signal.

According to another aspect of the present invention, a sampling signal generator includes a clock recovery circuit and a delay locked loop circuit.

The clock recovery circuit receives a transmission signal comprising a clock code, detects an edge of the clock code in the transmission signal in response to a clock window signal, and generates a clock signal based on an edge of the clock code. The delay locked loop circuit generates a multi-phase clock signal based on the clock signal, generates the clock window signal based on the multi-phase clock signal, and outputs the multi-phase clock signal as a sampling signal.

In one embodiment, the delay locked loop circuit includes a delay line that includes a plurality of delay cells for sequentially delaying the clock signal to generate the multi-phase clock signal, the delay line generating the delayed clock signal, A phase frequency detector for generating an up signal and a down signal based on the phase difference between the clock signal and the delayed clock signal, a delay control signal for adjusting the delay time of the delay line in response to the up signal and the down signal A lock detector for generating a lock detection signal in response to the up signal and the down signal, and a clock window generator for performing a logic operation on the multi-phase clock signal to generate the clock window signal have.

In one embodiment, the clock window generator generates a first window signal by performing a logic operation on two clock signals of the multi-phase clock signal, and generates two clock signals each adjacent to the two clock signals A window signal generator for generating a second window signal by selectively performing a logic operation on the first window signal and the second window signal and selectively outputting the first window signal or the second window signal in response to a window selection signal, And a window signal selector for detecting the interval between edges of the code and generating the window selection signal based on the detected interval.

The clock recovery circuit and the sampling signal generator according to embodiments of the present invention can accurately recover the clock signal from the clock embedded data.

In addition, the clock recovery circuit and the sampling signal generator according to the embodiments of the present invention can speed up signal transmission by using an adaptively generated clock window signal.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and the embodiments of the invention may be embodied in various forms And should not be construed as limited to the embodiments described in the text.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same or similar reference numerals are used for the same components in the drawings.

1 is a block diagram illustrating a clock recovery circuit according to an embodiment of the present invention.

1, the clock recovery circuit 100 includes a clock code detection unit 110, a clock signal generation unit 130, a delay circuit 150, and an output unit 170.

The clock code detection unit 110 receives the transmission signal RX including the clock code. The transmission signal RX may comprise serialized data bits and the clock code. The clock code may be periodically included in the transmission signal RX and may be added with a length of 1 bit or 2 bits for N (N is a natural number of 2 or more) data bits. Also, the clock code may have a value that is opposite to the value of the adjacent data bits. For example, if an adjacent data bit has a logic high level, the clock code may have a logic low level, and if the adjacent data bit has a logic low level, the clock code may have a logic high level. In one embodiment, the clock code may have a value that is inverse to the value of the immediately preceding data bit. In another embodiment, the clock code may have a value that is opposite to the value of the next data bit. The clock code having a value opposite to the value of the adjacent data bit may have an edge rising or falling between the clock code and the adjacent data bit.

The clock code detection unit 110 can detect the edge of the clock code in the transmission signal RX in response to the clock window signal CLKWIN. For example, the clock code detector 110 may receive a clock window signal CLKWIN from a delay locked loop (DLL) circuit. The clock window signal CLKWIN has a logic high level when the clock code transitions upward or downward. The clock code detection section 110 can detect the edge of the clock code in the transmission signal RX by detecting the edge of the transmission signal RX when the clock window signal CLKWIN has a logic high level. The clock window signal CLKWIN may generate a clock transition signal (CTS) that transitions upward when the clock code transitions based on the detected edge of the clock code.

The clock signal generator 130 generates a restored clock signal RCLK in response to a clock transition signal CTS. The clock signal generator 130 may generate a restored clock signal RCLK that periodically transitions in response to the clock transition signal CTS. Accordingly, the clock signal generator 130 can generate the restored clock signal RCLK having a period substantially equal to the period of the clock transition signal CTS.

The clock signal generator 130 may control the restored clock signal RCLK such that the restored clock signal RCLK rises and rises when the clock transition signal CTS rises. The clock signal generator 130 also controls the restored clock signal RCLK so that the restored clock signal RCLK falls in response to the delayed clock transition signal delayed by the clock transition signal CTS, It is possible to control the restored clock signal RCLK so that the restored clock signal RCLK falls in response to the clock falling signal received from the circuit.

The delay circuit 150 delays the transmission signal RX and outputs a delay transmission signal DRX. The delay circuit 150 outputs the delayed clock training signal by delaying the transmission signal RX including the clock training signal during the training interval, delays the transmission signal RX including the data bits during the data interval, Bits. ≪ / RTI >

The delay circuit 150 may delay the transmission signal RX by the delay time of the clock code detection unit 110 and the clock signal generation unit 130. [ The delay circuit 150 may delay the recovery clock signal RCLK generated by the clock code detection unit 110 and the clock signal generation unit 130 during the data interval, The data bits can be delayed. In addition, the delay circuit 150 may delay the clock training signal during the training interval by the delay time of the restored clock signal RCLK.

The output unit 170 outputs the restored clock signal RCLK received from the clock signal generation unit 130 or the delayed transmission signal DRX received from the delay circuit 150 as the clock signal CLK, And outputs the delayed transmission signal DRX received from the delay circuit 150. [ The output unit 170 may output the delayed transmission signal DRX, which is the delayed clock training signal received from the delay circuit 150 during the training interval, as the clock signal CLK. The output unit 170 outputs the restored clock signal RCLK received from the clock signal generation unit 130 during the data period as the clock signal CLK and outputs the delayed data bit And outputs the delayed transmission signal DRX as data DATA.

Since the clock recovery circuit 100 receives the transmission signal RX that is not encoded by the code such as 8B / 10B, the clock recovery circuit 100 may not perform separate decoding. In addition, the clock recovery circuit 100 can accurately and efficiently restore the clock signal by detecting the edge of the clock code from the transmission signal RX using the clock window signal CLKWIN.

2 is a timing chart for explaining the operation of the clock recovery circuit of FIG.

1 and 2, during a training interval, the delay circuit 150 receives the transmission signal RX, which is a clock training signal, by the delay time TD of the clock code detection unit 110 and the clock signal generation unit 130 And the output unit 170 outputs the delayed transmission signal DRX received from the delay circuit 150 as the clock signal CLK. For example, the pulse 202 of the delayed transmission signal DRX is delayed by the delay time TD from the pulse 201 of the clock training signal and is output as the pulse 203 of the clock signal CLK.

The clock code detection unit 110 and the clock signal generation unit 130 detect the edge of the transmission signal RX to generate the restored clock signal RCLK. The predetermined time may be the time from when the delay locked loop circuit receiving the clock signal CLK as an input to when it receives the clock training signal until it is locked. That is, the clock code detection unit 110 and the clock signal generation unit 130 can generate the restored clock signal RCLK after the delay locked loop circuit is locked. For example, the clock code detection section 110 and the clock signal generation section 130 may detect the rising edge of the pulse 204 of the clock training signal to generate the pulse 206 of the restored clock signal RCLK. Output 170 may output pulse 205 of delayed transmission signal DRX as pulse 207 of clock signal CLK or pulse 206 of restored clock signal RCLK as clock It can be outputted as the pulse 207 of the signal (CLK).

During the data interval, the transmit signal RX includes data bits 209 and a clock code 208 appended to the data bits 209. The delay circuit 150 delays the transmission signal RX by a delay time TD and outputs a delay transmission signal DRX. The output unit 170 outputs the delayed transmission signal DRX received from the delay circuit 150 as data DATA. For example, the clock code 210 and the data bits 211 in which the clock code 208 and the data bits 209 are delayed by the delay time TD can be output as the data DATA. The clock code 212 and / or data bits 213 output as data (DATA) may be parallelized by a sampler.

The clock code detection unit 110 and the clock signal generation unit 130 detect the edge of the clock code 208 to generate the restored clock signal RCLK and the output unit 170 outputs the restored clock signal RCLK as the clock signal CLK. For example, the clock code detection unit 110 detects an edge between the clock code 208 and the data bits 209 to generate a clock transition signal CTS, and the clock signal generation unit 130 generates a clock transition signal And generates a pulse 214 of the restored clock signal RCLK in response to the reset signal CTS and the output 170 outputs a pulse 214 of the restored clock signal RCLK as a pulse 215 of the clock signal CLK Can be output.

FIG. 3A is a timing chart for explaining an example of the operation of the clock code detecting unit and the clock signal generating unit included in the clock recovery circuit of FIG. 1; FIG.

Referring to FIGS. 1 and 3A, the clock codes 214 and 219 included in the transmission signal RX have a length of 1 bit and have values opposite to the values of the next data bits 215 and 221. For example, the clock code 214 has a logic low level opposite to the next data bit 215 having a logic high level, and the clock code 219 has a logic low level as opposed to the next data bit 220 having a logic low level. It can have a logic high level. Accordingly, the clock codes 214 and 219 may have edges 216 and 221 between the clock codes 214 and 219 and the next data bits 215 and 220. [ For example, the clock code 214 may have a rising edge 216 and the clock code 219 may have a falling edge 221.

The clock code detection unit 110 can detect the edge of the transmission signal RX when the clock window signal CLKWIN has a logic high level. In addition, the clock window signal CLKWIN may have a logic high level from one point in the clock code 214, 215 to one point in the next data bit 219, 220. Accordingly, the clock code detecting unit 110 can detect edges of the clock codes 214 and 219. [ For example, the clock code detection unit 110 detects the rising edge 216 of the clock code 214 in response to the pulse 217 of the clock window signal CLKWIN and detects the rising edge 216 of the clock window signal CLKWIN, The falling edge 221 of the clock code 219 can be detected. The clock code detection unit 110 outputs a clock transition signal CTS which is ascending and transient at the edges 216 and 221 of the clock codes 214 and 219 as a detection result.

The clock signal generator 130 generates a restored clock signal RCLK in response to a clock transition signal CTS. The clock signal generator 130 may generate a restored clock signal RCLK periodically rising and falling in response to each of the pulses 218 and 223 of the clock transition signal CTS.

3B is a timing chart for explaining another example of the operation of the clock code detecting unit and the clock signal generating unit included in the clock recovery circuit of FIG.

Referring to FIGS. 1 and 3B, the clock code 224 included in the transmission signal RX has a length of 1 bit and has a value opposite to the value of the previous data bit 225. For example, the clock code 224 may have a logic low level opposite to the previous data bit 225 having a logic high level, and may have a falling edge 226 with the previous data bit 225. The clock code detection section 110 detects the clock code 224 in response to the pulse 227 of the clock window signal CLKWIN having a logic high level up to a point in the clock code 224 up to a point in the previous data bit 225. [ And generate a clock transition signal (CTS) that transitions upward at the edge 226 of the clock code 224. The clock signal generation unit 130 may generate a restored clock signal RCLK that makes a rising transition in response to the pulse 228 of the clock transition signal CTS.

3C is a timing chart for explaining another example of the operation of the clock code detecting unit and the clock signal generating unit included in the clock recovery circuit of FIG.

Referring to FIGS. 1 and 3C, the clock code 229 included in the transmission signal RX has a length of 2 bits and has a value opposite to the value of the next data bit 230. For example, the clock code 229 may have a logic low level opposite to the next data bit 230 having a logic high level, and may have a rising edge 231 with the next data bit 230. The clock code detection unit 110 generates a clock code 229 in response to a pulse 232 of a clock window signal CLKWIN having a logic high level from one point of the first bit of the clock code 229 to one point of the next data bit 230, It is possible to detect the edge 231 of the clock signal 229 and generate a clock transition signal CTS that transitions upward at the edge 231 of the clock code 229. [ The clock signal generation unit 130 may generate a restored clock signal RCLK that makes a rising transition in response to the pulse 233 of the clock transition signal CTS.

FIG. 3D is a timing chart for explaining another example of the operation of the clock code detection unit and the clock signal generation unit included in the clock recovery circuit of FIG.

Referring to FIGS. 1 and 3, the clock code 234 included in the transmission signal RX has a length of 2 bits, and has a value opposite to the value of the previous data bit 235. For example, the clock code 234 may have a logic low level opposite to the previous data bit 235 having a logic high level, and may have a falling edge 236 with the previous data bit 235. The clock code detection unit 110 generates a clock signal CLKWIN in response to a pulse 238 of a clock window signal CLKWIN having a logic high level from one point of the previous data bit 235 to one point of the second bit of the clock code 234, It is possible to detect the edge 236 of the code 234 and generate a clock transition signal CTS that transitions upward at the edge 236 of the clock code 234. [ The clock signal generation unit 130 may generate a restored clock signal RCLK which is caused to rise and rise in response to the pulse 238 of the clock transition signal CTS.

As shown in Figs. 3A to 3D, the clock code may have a length of one bit or more, and may have an edge between previous or next bits. For convenience of explanation, although the delay by the clock code detection unit and the clock signal generation unit is not shown in Figs. 3A to 3D, the restored clock signal may be delayed with respect to the edge of the clock code by the clock code detection unit and the clock signal generation unit . In addition, the clock recovery circuit can use a clock window signal that is adaptively selected according to the data rate and / or delay amount, as described later with reference to Figs. 17 to 21B, so that even if the clock code is delayed, So that a restored clock signal can be generated.

4 is a block diagram showing a clock code detection unit included in the clock recovery circuit of FIG.

4, the clock code detecting unit 110 includes a rising detector 111, a falling detector 113, a rising-falling determiner 115, and a selector 117. [

The rise detector 111 detects the rising edge of the clock code included in the transmission signal RX based on the clock window signal CLKWIN to generate the rising edge detection signal REDS. The falling detector 113 detects the falling edge of the clock code included in the transmission signal RX based on the clock window signal CLKWIN and generates the falling edge detection signal FEDS. When the clock code has a rising edge, the rising edge detection signal (REDS) is activated in response to the rising edge of the clock code, and when the clock code has a falling edge, the falling edge detection signal (FEDS) May be activated in response to an edge.

In one embodiment, the rising detector 111 includes a data terminal to which the clock window signal CLKWIN is applied, an enable terminal to which the transmission signal RX is applied, an inverted reset terminal to which the clock window signal CLKWIN is applied, And a first gated latch having an output terminal to which an edge detection signal REDS is output. The rising detector 111 can be reset when the clock window signal CLKWIN has a logic low level. The rising detector 111 outputs the clock window signal CLKWIN as it is when the clock window signal CLKWIN has a logic high level and the transmission signal RX has a logic high level and the transmission signal RX You can keep the previous output when you have a logic low level.

The falling detector 113 includes a data terminal to which the clock window signal CLKWIN is applied, an inverted enable terminal to which the transmission signal RX is applied, an inverted reset terminal to which the clock window signal CLKWIN is applied, And a second gated latch having an output terminal to which the FEDS is output. The falling detector 113 can be reset when the clock window signal CLKWIN has a logic low level. The falling detector 113 outputs the clock window signal CLKWIN as it is when the clock window signal CLKWIN has a logic high level and the transmission signal RX has a logic low level and the transmission signal RX You can keep the previous output when you have a logic high level.

The rising-falling determiner 115 determines whether the clock code included in the transmission signal RX has a rising edge or a falling edge based on the clock window signal CLKWIN and outputs a rising-falling determination signal RFDS . For example, the rising-falling determiner 115 generates a rising-falling decision signal RFDS having a logic low level when the clock code has a rising edge, and generates a rising-falling decision signal RFDS when the clock code has a falling edge, Down decision signal RFDS having a rising edge and a falling edge.

In one embodiment, the rising-and-falling determiner 115 includes a data terminal to which the transmission signal RX is applied, a clock terminal to which the clock window signal CLKWIN is applied, and an output terminal to which the rising- And a rising edge triggered flip-flop. The rising-falling determiner 115 can output the transmission signal RX as the rising-falling determination signal RFDS in response to the rising edge of the clock window signal CLKWIN.

The selector 117 selects either the rising edge detection signal REDS received from the rising detector 111 as the clock transition signal CTS or the falling edge detection signal RDSR received from the rising detector 111 in response to the rising-falling decision signal RFDS received from the rising- And selectively outputs the falling edge detection signal (FEDS) received from the detector (113).

In one embodiment, the selector 117 includes a first input terminal to which the rising edge detection signal REDS is applied, a second input terminal to which the falling edge detection signal FEDS is applied, And a multiplexer having an output terminal for outputting a clock transition signal CTS. For example, the selector 117 outputs the rising edge detection signal REDS as a clock transition signal CTS when the rising-down decision signal RFDS has a logic low level, and outputs the rising-edge determination signal RFDS The falling edge detection signal FEDS can be output as the clock transition signal CTS.

The clock code detection unit 110 can detect the edge of the clock code irrespective of whether the clock code has a rising edge or a falling edge.

5 is a timing chart for explaining the operation of the clock code detecting unit of FIG.

Referring to Figures 4 and 5, the rising detector 111 maintains the previous output and outputs a rising edge detection signal (" 1 ") having a logic low level when the clock code 239 having a logic low level is applied to the enable terminal REDS). When the data bit 240 having the logic high level is applied to the enable terminal of the rising detector 111, the rising detector 111 outputs the clock window signal CLKWIN having the logic high level as it is, It is possible to output the rising edge detection signal REDS. When the clock window signal CLKWIN transitions to a logic low level, the rising detector 111 resets and outputs a rising edge detection signal REDS having a logic low level again. As such, the rising detector 111 may generate a rising edge detection signal REDS having a pulse 243 that transitions upward in response to the rising edge of the clock code 239. [ Similarly, the falling detector 113 may generate a falling edge detection signal (FEDS) having a pulse 247 that transitions upward in response to the falling edge of the clock code.

The rising-falling determiner 115 can output the transmission signal RX as the rising-falling determination signal RFDS in response to the rising edge of the clock window signal CLKWIN. For example, the rise-and-fall determiner 115 may be configured to have a logic low level 245 by latching a clock code 239 having a logic low level in response to the rising edge of the pulse 242 of the clock window signal CLKWIN It is possible to output the rising-falling decision signal RFDS.

The selector 117 selectively outputs the rising edge detection signal REDS or the falling edge detection signal FEDS as the clock transition signal CTS in response to the rising-falling determination signal RFDS. For example, the selector 117 outputs the rising edge detection signal REDS as the clock transition signal CTS when the rising-and-fall determination signal RFDS has the logic low level 245, When the determination signal RFDS has the logic high level 248, the falling edge detection signal FEDS can be output as the clock transition signal CTS. Accordingly, the clock transition signal CTS may have pulses 246, 249 that rise and fall at the edge of the clock code.

6 is a diagram illustrating a clock signal generator included in the clock recovery circuit of FIG.

Referring to FIG. 6, the clock signal generator 130 includes an SR latch 131 and a delay circuit 132.

The delay circuit 132 delays the clock transition signal CTS and outputs a delay clock transition signal DCTS. The delayed clock transition signal DCTS may have a pulse delayed by a predetermined delay time with respect to the pulse of the clock transition signal CTS.

The SR latch 131 has a set terminal to which a clock transition signal CTS is applied, a reset terminal to which a delay clock transition signal DCTS is applied, and an output terminal to which a restored clock signal RCLK is output. The SR latch 131 outputs a restored clock signal RCLK having a logic high level when the clock transition signal CTS is at a logic high level and outputs a logic low level when the delayed clock transition signal DCTS is at a logic high level And retains the previous output when both the clock transition signal CTS and the delayed clock transition signal DCTS have a logic low level. Accordingly, the SR latch 131 can make a rising transition when the clock transition signal CTS makes a rising transition and a restoring clock signal RCLK that makes a falling transition when the delay clock transition signal DCTS makes an up transition .

7 is a timing chart for explaining the operation of the clock signal generator of FIG.

6 and 7, the clock signal generator 130 transitions from a logic low level to a logic high level 254 in response to a rising edge of a pulse 252 of a clock transition signal (CTS) May generate a restored clock signal (RCLK) that transitions from a logic high level (254) to a logic low level (255) in response to a rising edge of a pulse (253) of a clock transition signal (DCTS). Accordingly, the clock signal generator 130 can generate the periodic restored clock signal RCLK that transitions upward at the edge of the clock code 250. [

8 is a block diagram showing a delay circuit included in the clock recovery circuit of FIG.

8, the delay circuit 150 includes a detector replica delay 151, a selector replica delay 153, and a latch replica delay 155.

The detector replica retarder 151 delays the transmission signal RX by the delay time of the rising detector 111 or the falling detector 111 of Figure 4 and the selector replica retarder 153 is delayed by the selector 117 of Figure 4, The latch replica delayer 155 can further delay the transmission signal RX by the delay time of the SR latch 131 of FIG. The delay circuit 150 may delay the transmission signal RX by the time delayed by the recovery clock signal RCLK generated by the clock code detection unit 110 and the clock signal generation unit 130 of FIG. Accordingly, the clock recovery circuit 100 of FIG. 1 can output the clock signal CLK and the data DATA delayed by substantially the same delay time.

9 is a block diagram showing an output section included in the clock recovery circuit of FIG.

Referring to FIG. 9, the output unit 170 includes a clock output unit 171 and a data output unit 173.

The clock output section 171 can selectively output the restored clock signal RCLK or the delayed transmission signal DRX as the clock signal CLK. For example, the clock output unit 171 may output the delayed transmission signal DRX as the clock signal CLK during the training interval and output the restored clock signal RCLK as the clock signal CLK during the data interval have.

In one embodiment, the clock output section 171 includes a first input terminal to which the restored clock signal RCLK is applied, a second input terminal to which the delay transmission signal DRX is applied, and a second input terminal to which the inversion lock detection signal LDSB is applied A selection terminal, and a multiplexer having an output terminal to which the clock signal CLK is output. The inversion lock detection signal LDSB may be output from the delay locked loop circuit which receives the clock signal CLK as an inverted signal of the lock detection signal LDS. The delay locked loop circuit can output a lock detection signal LDS having a logic high level when it is locked by the clock signal CLK. Accordingly, the clock output section 171 outputs the delayed transmission signal DRX as the clock signal CLK before the delay locked loop circuit is locked, and after the delay locked loop circuit is locked, the restored clock signal RCLK ) As the clock signal CLK. The data output unit 173 can selectively output the delayed transmission signal DRX as the data DATA. For example, the data output unit 173 may output the delayed transmission signal DRX as data (DATA) during the data interval without outputting the data (DATA) during the training interval.

In one embodiment, the data output 173 may include a transmission gate controlled by a lock detect signal LDS and an inverse lock detect signal LDSB. The data output section 173 can output the delayed transmission signal DRX when the lock detection signal LDS has a logic high level and the inversion lock detection signal LDSB has a logic low level. Accordingly, the data output unit 173 can output the data DATA during the data interval.

10 is a block diagram illustrating a sampling signal generator including the clock recovery circuit of FIG.

Referring to FIG. 10, the sampling signal generator 300 includes a clock recovery circuit 100 and a delay locked loop circuit 400. The delay locked loop circuit 400 includes a phase frequency detector 410, a lock detector 420, a control signal generator 430, a delay line 440 and a clock window generator 450.

The clock recovery circuit 100 receives the transmission signal RX including the clock code and generates the clock signal CLK by detecting the edge of the clock code in response to the clock window signal CLKWIN. In addition, the clock recovery circuit 100 may output the transmission signal RX as data DATA during the data interval.

The phase frequency detector 410 detects the phase difference between the clock signal CLK received from the clock recovery circuit 100 and the delayed clock signal DCLK received from the delay line 440 and generates a clock signal CLK and a delay And generates the up signal UP and the down signal DN based on the detected phase difference of the clock signal DCLK. The control signal generator 430 generates a delay control signal CTRL in response to the up signal UP and the down signal DN received from the phase frequency detector 410. The control signal generator 430 includes a charge pump that generates a charge current in response to the up signal UP and generates a discharge current in response to the down signal DN, And a delay filter for generating a delay control signal CTRL corresponding to the phase difference between the clock signal CLK and the delayed clock signal DCLK.

For example, when the delayed clock signal DCLK is later than the clock signal CLK, the phase frequency detector 410 generates an up signal UP having a logic high level, and the control signal generator 430 generates an up signal UP (CTRL) that reduces the delay time of the delay line 440 in response to the refresh signal UP. When the delayed clock signal DCLK is ahead of the clock signal CLK, the phase frequency detector 410 generates a down signal DN having a logic high level, and the control signal generator 430 generates a down signal DN The delay control signal CTRL may be generated to increase the delay time of the delay line 440 in response to the delay control signal CTRL.

The lock detector 420 generates a lock detection signal LDS indicating whether the delay locked loop circuit 400 is locked based on the up signal UP and the down signal DN. For example, the lock detector 420 generates a lock detection signal LDS having logic high levels when the up signal UP and the down signal DN have logic high levels or when the difference is less than a predetermined time can do.

The delay line 440 delays the clock signal CLK received from the clock recovery circuit 100 to generate a delayed clock signal DCLK. The delay line 440 also includes a plurality of delay cells that sequentially delay the clock signal CLK and generates a multi-phase clock signal MPCS including clock signals output from the plurality of delay cells, respectively . The delay line 440 may also provide a multi-phase clock signal MPCS to the clock window generator 450 and provide the multi-phase clock signal MPCS to the external sampler as the sampling signal SS .

The clock window generator 450 generates the clock window signal CLKWIN based on the multi-phase clock signal MPCS received from the delay line 440. The clock window generator 450 may perform a logic operation on the multi-phase clock signal (MPCS) to produce the clock window signal CLKWIN. In addition, the clock window generator 450 may adaptively generate the clock window signal CLKWIN according to the data rate of the transmission signal RX and / or the delay amount of the clock recovery circuit 100. 10, clock window generator 450 is shown included in delay locked loop circuit 400, but some or all of clock window generator 450 may be external to delay locked loop circuit 400 , And may be included in the clock recovery circuit 100.

The sampling signal generator 300 can accurately and efficiently restore the clock signal CLK from the transmission signal RX by using the clock window signal CLKWIN and outputs the sampling signal SS corresponding to the data DATA Can be generated.

11 is a block diagram showing a delay line included in the sampling signal generator of FIG.

Referring to FIG. 11, the delay line 440 includes first through N + 3 delay cells 441, 442, 443, 444, 445, 446, 447, and 448.

The first through N + 3 delay cells 441, 442, 443, 444, 445, 446, 447 and 448 sequentially delay the clock signal CLK to sequentially output the first through third clock signals CLK_1, CLK_2, CLK_A, CLK_B, CLK_N, CLK_N + 1, CLK_N + 2, and CLK_N + 3, respectively. The first through N + 3 delay cells 441, 442, 443, 444, 445, 446, 447, and 448 may delay the clock signal input by substantially the same delay time. The first to N + 3 delay cells 441, 442, 443, 444, 445, 446, 447 and 448 can be controlled to increase or decrease the delay time by the delay control signal CTRL.

Each of the first through N + 3 delay cells 441, 442, 443, 444, 445, 446, 447, and 448 may include a plurality of sub-delay cells. For example, the second delay cell 442 includes a first sub-delay cell 442a, a second sub-delay cell 442b, a third sub-delay cell 442c, and a fourth sub-delay cell 442d can do. Each of the first to N + 3 delay cells 441, 442, 443, 444, 445, 446, 447 and 448 includes first through third clock signals CLK_1, CLK_2, CLK_A , CLK_B, CLK_N, CLK_N + 1, CLK_N + 2, CLK_N + 3). For example, the second delay cell 442 may output the second clock signal CLK_2 at the output node of the second sub-delay cell 442b, that is, at the input node of the third sub-delay cell 442c.

In one embodiment, the delay line 440 includes N + 3 delay cells 441, 442, and 444 when the transmission signal includes N data bits and a 2-bit length clock code added for every N data bits. 443, 444, 445, 446, 447, 448). The delay line 440 may output a delayed clock signal DCLK at the output node of the (N + 2) th delay cell 447, that is, at the input node of the (N + 3) th delay cell 448. Accordingly, since the transmission signal includes N + 2 bits each and the delay line 440 delays the clock signal CLK by the delay time of N + 2 delay cells and outputs the delay clock signal DCLK , And the delay time of each delay cell may correspond to one bit length of the transmission signal.

12 is a diagram illustrating an example of a clock window generator included in the sampling signal generator of FIG.

Referring to FIG. 12, the clock window generator 450 includes an AND gate 451 and an inverter 452.

The inverter 452 inverts the (N + 3) -th clock signal CLK_N + 3. The AND gate 451 performs an AND operation on the inversion signals of the (N + 1) -th clock signal (CLK_N + 1) and the (N + 3) -th clock signal (CLK_N + 3). The AND gate 451 outputs a clock signal having a logic high level when the (N + 1) th clock signal CLK_N + 1 has a logic high level and the (N + 3) It is possible to generate the window signal CLKWIN. Accordingly, the clock window generator 450 generates a clock window signal CLKWIN having a logic high level from the rising edge of the (N + 1) -th clock signal CLK_N + 1 to the rising edge of the (N + 3) Can be generated.

FIG. 13 is a timing chart for explaining the operation of the delay line of FIG. 11 and the clock window generator of FIG. 12;

11-13, the clock signal CLK rises at edge 256 of the clock code, and the delayed clock signal DCLK may have substantially the same phase as the clock signal CLK. The first clock signal CLK_1 output from the middle of the sub-delay cells included in the first delay cell 441 may transition up in the middle of the first data bit D1. Further, the second to Nth clock signals CLK_2, CLK_A, CLK_B and CLK_N may each be shifted up in the middle of the second to Nth data bits D2, DA, DB and DN. Accordingly, the first to Nth clock signals CLK_1, CLK_2, CLK_A, CLK_B, and CLK_N may be used to sample the first to Nth data bits D1, D2, DA, DB, have.

The (N + 1) th clock signal (CLK_N + 1) can rise up in the middle of the first bit of the clock code (CC) It is possible to make a rising transition in the middle of the bit. Further, the (N + 3) -th clock signal CLK_N + 3 may be transited to the first data bit D1 of the next cycle in the middle. That is, the (N + 3) th delay cell 448 can output the (N + 3) -th clock signal CLK_N + 3 delayed by one cycle from the first clock signal CLK_1 output from the first delay cell 441.

The clock window generator 450 may generate a clock window signal CLKWIN by performing a logical operation on the (N + 1) -th clock signal (CLK_N + 1) and the (N + 3) -th clock signal (CLK_N + 3). For example, the clock window generator 450 inverts the (N + 3) -th clock signal CLK_N + 3 and outputs the (N + 1) th clock signal CLK_N + An AND operation can be performed on the inverted signal to generate the clock window signal CLKWIN. Accordingly, the clock window signal CLKWIN is set so that the (N + 1) th clock signal CLK_N + 1 has a logic high level 258 and the (N + 3) (260), as shown in FIG. The clock recovery circuit 100 of Figure 1 detects the edge 256 of the transmission signal RX based on the clock window signal CLKWIN with a logic high level 260 and detects the edge 256 of the transmission signal RX The clock signal CLK having the rising edge 257 can be generated.

As such, the clock recovery circuit and the sampling signal generator according to the embodiment of the present invention can accurately recover the clock signal from the clock embedded data by detecting the edge of the clock code using the clock window signal.

14 is a diagram illustrating a clock signal generator included in a clock recovery circuit according to another embodiment of the present invention.

Referring to FIG. 14, the clock signal generator 130 includes an SR latch 131.

The SR latch 131 has a set terminal to which a clock transition signal CTS is applied, a reset terminal to which a clock falling signal CFS is applied, and an output terminal to which a recovered clock signal RCLK is output. The SR latch 131 outputs a restored clock signal RCLK having a logic high level when the clock transition signal CTS is at a logic high level and outputs a logic low level when the clock falling signal CFS is at a logic high level (RCLK) and maintains the previous output when both the clock transition signal (CTS) and the clock falling signal (CFS) have a logic low level. Accordingly, the SR latch 131 can generate the restored clock signal RCLK that is caused to rise when the clock transition signal CTS makes an up transition and fall down when the clock falling signal CFS makes an up transition.

The clock signal generator 130 may receive the clock falling signal CFS from the delay locked loop circuit 400 of FIG. 10 according to another embodiment of the present invention. The delay locked loop circuit 400 of FIG. 10 may further include a circuit for generating a clock falling signal CFS based on the multi-phase clock signal MPCS. For example, the circuit for generating the clock falling signal (CFS) may have a similar configuration to the clock window generator 450 of FIG.

Referring again to FIG. 13, the clock falling signal CFS can be generated by performing an AND operation on the inverted signals of the A clock signal CLK_A and the B clock signal CLK_B. The clock falling signal CFS is set to a logic high level 262 when the A clock signal CLK_A has a logic high level 262 and the B clock signal CLK_B has a logic low level 263. [ 264). The A-th clock signal CLK_A and the B-th clock signal CLK_B may be signals respectively output from two delay cells located in the middle of the delay line 440 in Fig. For example, the A th clock signal CLK_A is a signal output from the N / 2 + 1 th delay cell among N + 3 delay cells included in the delay line 440, and the B th clock signal CLK_B is N / 2 + 2 < th > delay cell. The clock recovery circuit including the clock signal generator 130 according to another embodiment of the present invention includes a clock signal CLK having a falling edge 261 in response to a clock falling signal CFS having a logic high level 264, Can be generated.

The clock signal generator 130 of FIG. 14 according to another embodiment of the present invention is different from the clock signal generator 130 of FIG. 6 in that the clock signal generator 130 of FIG. And can generate the restored clock signal RCLK based on the clock falling signal CFS.

15 is a diagram illustrating a clock window generator included in a sampling signal generator according to another embodiment of the present invention.

Referring to FIGS. 10 and 15, the clock window generator 450 includes a window signal generator 460 and a window signal selector 470.

The window signal generator 460 receives at least part of the multi-phase clock signal from the delay line 440. For example, the window signal generator 460 generates the window signal CLK_N, the (N + 1) -th clock signal CLK_N + 1, the (N + 2) -th clock signal CLK_N + 2, And can receive the (N + 3) -th clock signal (CLK_N + 3).

The window signal generator 460 generates an Nth delayed clock signal DCLK by delaying the Nth delayed clock signal DCLK by about 0.5 bits with respect to the delayed clock signal DCLK, 3 clock signal CLK_N + 3 to generate a logic low level between the rising edge of the (N + 1) -th clock signal CLK_N + 1 and the rising edge of the (N + 3) The first window signal CLKWIN1 may be generated. The window signal generator 460 generates the window signal CLK_N and the delayed clock signal DCLK by about 2.5 bits long with respect to the delayed clock signal DCLK, A second window signal having a logic high level between the rising edge of the Nth clock signal CLK_N and the rising edge of the (N + 2) th clock signal CLK_N + 2 by performing a logic operation on the clock signal CLK_N + CLKWIN2 < / RTI >

The window signal selector 470 may receive the first window signal CLKWIN1 and / or the second window signal CLKWIN2 from the window signal generator 460. The window signal selector 470 can detect the interval between the edges of the clock code included in the first window signal CLKWIN1 and / or the second window signal CLKWIN2 and the transmission signal RX. The window signal selector 470 may generate a window selection signal WINSEL indicating the first window signal CLKWIN1 or the second window signal CLKWIN2 by determining whether the detected interval is equal to or greater than a predetermined value.

In one embodiment, the window signal selector 470 can determine whether the first window signal CLKWIN1 has a certain margin with respect to the edge of the clock code included in the transmission signal RX. For example, when the rising edge of the first window signal CLKWIN1 is ahead of the margin of the clock code by about 0.5 bit length as the predetermined margin, the window signal selector 470 outputs the first window signal CLKWIN1, The window selection signal WINSEL may be generated. The window signal selector 470 outputs the second window signal CLKWIN2 when the rising edge of the first window signal CLKWIN1 is not ahead of the transmission signal RX by about 0.5 bit length with respect to the edge of the clock code (WINSEL) indicating the window selection signal (WINSEL).

The window signal generator 460 generates a first window signal CLKWIN1 or a second window signal CLKWIN2 as a clock window signal CLKWIN in response to the window selection signal WINSEL received from the window signal selector 470 And can selectively output it.

When the transmission rate of the transmission signal RX is high and the delay time of the delay clock signal DCLK corresponding to the clock signal CLK or the clock signal CLK by the clock recovery circuit 100 is significant, The clock window signal CLKWIN generated based on the clock signal CLKWIN may not be suitable for edge detection of the clock code included in the transmission signal RX. However, the sampling signal generator 300 including the clock window generator 450 according to another embodiment of the present invention generates the clock window signal CLKWIN adaptively according to the rate and / or delay amount, The edge of the code can be detected to generate the clock signal CLK and the sampling signal SS.

16 is a diagram illustrating a window signal generator included in the clock window generator of FIG.

16, the included window signal generator 460 includes a first inverter 461, a first AND gate 462, a second inverter 463, a second AND gate 464, and a multiplexer 465, .

The first inverter 461 inverts the (N + 3) -th clock signal CLK_N + 3. The first AND gate 462 performs an AND operation on the inversion signals of the (N + 1) -th clock signal (CLK_N + 1) and the (N + 3) -th clock signal (CLK_N + 3). When the (N + 1) -th clock signal CLK_N + 1 has a logic high level and the (N + 3) th clock signal CLK_N + 3 has a logic low level, the first AND gate 462 has a logic high level The first window signal CLKWIN1 can be generated. Accordingly, the first window signal CLKWIN1 may have a logic high level from the rising edge of the (N + 1) -th clock signal CLK_N + 1 to the rising edge of the (N + 3) -th clock signal CLK_N + 3.

The second inverter 463 inverts the (N + 2) -th clock signal CLK_N + 2. The second AND gate 464 performs an AND operation on the inversion signals of the N-th clock signal CLK_N and the (N + 2) -th clock signal CLK_N + 2. The second AND gate 464 outputs a second window signal having a logic high level when the Nth clock signal CLK_N has a logic high level and the (N + 2) th clock signal CLK_N + 2 has a logic low level. (CLKWIN2). Thus, the second window signal CLKWIN2 may have a logic high level from the rising edge of the Nth clock signal CLK_N to the rising edge of the (N + 2) th clock signal CLK_N + 2.

The multiplexer 465 receives a first input terminal to which the first window signal CLKWIN1 is applied, a second input terminal to which the second window signal CLKWIN2 is applied, a window selection signal 470 from the window signal selector 470 And an output terminal to which a clock window signal CLKWIN is output. The multiplexer 465 selectively outputs the first window signal CLKWIN1 or the second window signal CLKWIN2 as the window selection signal WINSEL in response to the window selection signal WINSEL. For example, the multiplexer 465 outputs the first window signal CLKWIN1 as a clock window signal CLKWIN when the window selection signal WINSEL has a logic high level, and outputs the first window signal CLKWIN2 as a clock signal CLKWIN when the window selection signal WINSEL is logic low Level, the second window signal CLKWIN2 can be output as the clock window signal CLKWIN.

17 is a diagram showing an example of a window signal selector included in the clock window generator of FIG.

17, the window signal selector 470 includes a delay circuit 471, a first flip-flop 472, a second flip-flop 473, and an XOR gate 474.

The delay circuit 471 receives the first window signal CLKWIN1 received from the window signal generator 460 in Fig. The delay circuit 471 may delay the first window signal CLKWIN1 by about half the length of the delay signal of the delay cell included in the delay line. The delay time of the delay circuit 471 can be determined according to the margin for the edge of the clock code in which the first window signal CLKWIN1 is included in the transmission signal RX.

The first flip-flop 472 latches the transmission signal RX in response to the first window signal CLKWIN1 delayed by the delay circuit 471. [ The first flip-flop 472 includes a data terminal to which the transmission signal RX is applied, a clock terminal to which the first window signal CLKWIN1 delayed by the delay circuit 471 is applied, and a rising edge trigger Flip-flop. Thus, the first flip-flop 472 can output the value of the transmission signal RX at the rising edge of the first window signal CLKWIN1 delayed by the delay circuit 471. [

The second flip-flop 473 latches the transmission signal RX in response to the first window signal CLKWIN1 delayed by the delay circuit 471. [ The second flip-flop 473 has a data terminal to which the transmission signal RX is applied, a clock terminal to which the first window signal CLKWIN1 delayed by the delay circuit 471 is applied, and a falling edge trigger Flip-flop. Thus, the second flip-flop 473 can output the value of the transmission signal RX at the falling edge of the first window signal CLKWIN1 delayed by the delay circuit 471. [

The XOR gate 474 performs an XOR operation on the output signal of the first flip-flop 472 and the output signal of the second flip-flop 473. When the output signal of the first flip-flop 472 and the output signal of the second flip-flop 473 have the same logic level, the first window signal CLKWIN1 is the clock signal of the clock signal included in the transmission signal RX Not suitable for edge detection. Accordingly, the XOR gate 474 generates a window selection signal WINSEL having a logic low level, and the multiplexer 465 of FIG. 18 can output the second window signal CLKWIN2 as a clock window signal CLKWIN have.

When the output signal of the first flip-flop 472 and the output signal of the second flip-flop 473 have the same logic level, the first window signal CLKWIN1 is the clock signal of the clock signal included in the transmission signal RX Has a margin equal to the delay time of the delay circuit 471 with respect to the edge, and is suitable for edge detection of the clock code. Accordingly, the XOR gate 474 generates a window selection signal WINSEL having a logic high level, and the multiplexer 465 of FIG. 16 can output the first window signal CLKWIN1 as a clock window signal CLKWIN have.

In this manner, the clock window generator including the window signal selector 470 can generate a clock window signal having a certain margin with respect to the edge of the clock code. Accordingly, the clock window generator including the window signal selection unit 470 can accurately detect the edge of the clock code even if the delay during clock recovery is large or the data is transmitted at a high speed.

In one embodiment, the window signal selector 470 performs an operation of adaptively selecting a clock window signal (CLKWIN) during a training interval in which a clock training signal is transmitted, and when the data including the clock code And may operate as a clock error detector to detect transmission errors during the interval. During the data interval, the window signal selector 470 receives the transmission signal RX and the first window signal CLKWIN1 or the second window signal CLKWIN2 selected during the training interval and transmits a transmission error, An error in which the clock code is not included in the clock RX can be detected. When the transmission signal RX does not include a clock code, the reception apparatus including the window signal selection unit 470 of FIG. 17 notifies the transmission apparatus of the transmission error, and the transmission apparatus transmits the clock training signal and the clock signal to the reception apparatus RX. And / or retransmit the data.

FIG. 18A is a timing chart for explaining an example of the operation of the window signal selecting unit of FIG. 17; FIG.

17 and 18A, after the delay locked loop circuit 400 of FIG. 10 is locked during the training interval, that is, when the lock detection signal LDS has a logic high level 268 An adaptive window selection operation is performed. The clock signal CLK generated by the clock recovery circuit 100 of FIG. 10 is delayed by the recovery delay time TRD from the transmission signal RX. The pulse 267 of the first window signal CLKWIN1 with the leading rising edge by about 1.5 bits long and the falling edge by about 0.5 bits longer than the rising edge of the clock signal CLK is about 1.5 And has a margin (M1) that limits the recovery delay time (TRD) in the bit length. In this case, when the margin M1 of the first window signal CLKWIN1 is equal to or longer than a predetermined time, for example, about 0.5 bit length, the window signal selector 470 outputs the first window signal CLKWIN as the clock window signal CLKWIN CLKWIN1) can be selected. Accordingly, during the data period, the edge of the clock code included in the transmission signal RX can be accurately detected using the pulse 269 of the clock window signal CLKWIN with the predetermined margin M1.

FIG. 18B is a timing chart for explaining another example of the operation of the window signal selecting unit of FIG. 17; FIG.

17 and 18B, the pulse 267 of the first window signal CLKWIN1 has a predetermined margin M1 for the transmission signal RX. At this time, when the margin M1 of the first window signal CLKWIN1 is less than a predetermined time, for example, about 0.5 bit length, the first window signal CLKWIN1 is not suitable for clock code detection. Accordingly, the second window signal CLKWIN2, which is about one bit long with respect to the first window signal CLKWIN1, can be selected as the clock window signal CLKWIN. The pulse 275 of the second window signal CLKWIN2 may precede the predetermined margin M2, for example, about 0.5 bit length, for the transmission signal RX. Thus, during the data period, the edge of the clock code contained in the transmission signal RX can be accurately detected using the pulse 276 of the clock window signal CLKWIN with a predetermined margin M2.

As described above, the clock window generator 450 of FIG. 15 according to another embodiment of the present invention adapts the clock window signal CLKWIN having a predetermined margin to the transmission signal RX according to the transmission rate and / It can be created as an object. Accordingly, the clock recovery circuit according to another embodiment of the present invention can accurately detect the clock code even during high-speed transmission using the adaptively generated clock window signal CLKWIN. In addition, the sampling signal generator according to another embodiment of the present invention is suitable for high-speed operation.

19 is a diagram illustrating a window signal selector included in a sampling signal generator according to still another embodiment of the present invention.

19, the window signal selector 470 includes a delay circuit 471, a first flip-flop 472, a second flip-flop 473, an XOR gate 474, a third flip-flop 475, a counter 476, and a comparator 477.

The delay circuit 471 delays the first window signal CLKWIN1 by a desired margin. The first flip-flop 472 outputs the value of the transmission signal RX at the rising edge of the first window signal CLKWIN1 delayed by the delay circuit 471. [ The second flip-flop 473 outputs the value of the transmission signal RX at the falling edge of the first window signal CLKWIN1 delayed by the delay circuit 471. [ The XOR gate 474 performs an XOR operation on the output signal of the first flip-flop 472 and the output signal of the second flip-flop 473 to generate a first window signal CLKWIN1 delayed by the delay circuit 471 The edge of the clock code included in the transmission signal RX is present between the rising edge and the falling edge of the clock signal RX.

The third flip-flop 475 latches the output signal of the XOR gate 474 in response to a clock signal, e.g., the clock falling signal CFS of FIG. The third flip-flop 475 has a data terminal to which the output signal of the XOR gate 474 is applied, a clock terminal to which the clock signal is applied, an inverted reset terminal to which the lock detection signal LDS is applied, A rising edge triggered flip-flop. The third flip-flop 475 can operate when the lock detector 420 of FIG. 10 outputs a lock detection signal LDS having a logic high level. In addition, the third flip-flop 475 may be synchronized with the counter 476 and the comparator 477 using the clock signal.

The counter 476 performs the counting operation in response to the output signal of the third flip-flop 475. [ For example, the counter 476 may comprise a plurality of serially connected flip-flops. The comparator 477 compares the counting result of the counter 476 with a predetermined reference value. Accordingly, the counter 476 and the comparator 477 compare the output signal of the third flip-flop 475 with the output signal of the third flip-flop 475 when the output signal of the third flip- A window selection signal WINSEL can be generated. For example, when the output signal of the third flip-flop 475 holds a logic high level for a predetermined time, the counter 476 and the comparator 477 compare the window selection signal (CLKWIN1) indicating the first window signal CLKWIN1 The counter 476 and the comparator 477 output a window signal indicating the second window signal CLKWIN2 when the output signal of the third flip-flop 475 holds a logic low level for a predetermined time, Signal (WINSEL).

In one embodiment, the window signal selector 470 performs an operation of adaptively selecting a clock window signal (CLKWIN) during a training interval in which a clock training signal is transmitted, and when the data including the clock code And may operate as a clock error detector to detect transmission errors during the interval.

As described above, the clock window generator 450 shown in FIG. 19 according to still another embodiment of the present invention generates a clock window signal CLKWIN having a predetermined margin with respect to the transmission signal RX according to the transmission rate and / or the delay amount It can be generated adaptively.

20 is a block diagram illustrating an interface system including a sampling signal generator in accordance with embodiments of the present invention.

Referring to FIG. 20, an interface system 500 includes a transmission apparatus 510, a transmission line 520, and a reception apparatus 530.

The transmitting device 510 transmits the clock embedded data to the receiving device 530 through the transmission line 520. The transmitting apparatus 510 transmits a clock training signal through the transmission line 520 during the training interval and transmits the data to which the clock code is added through the transmission line 520 during the data interval.

The receiving apparatus 530 includes a sampling signal generator 300 and a sampler 550. The sampling signal generator 300 restores the clock signal CLK from the transmission signal RX transmitted through the transmission line 520 and outputs the data DATA delayed by the recovery delay of the clock signal CLK to the sampler 550 to provide. The sampling signal generator 300 includes a clock recovery circuit 100 that restores the clock signal CLK from the transmission signal RX based on the clock window signal CLKWIN and a clock window signal CLKWIN for clock recovery, And a delay locked loop circuit 400 for generating a sampling signal SS for sampling. The sampler 550 may sample and / or parallelize the data DATA provided from the clock recovery circuit 100 in response to the sampling signal SS provided from the delay locked loop circuit 400. [ The parallel data PD sampled by the sampler 550 and the clock signal CLK / delayed clock signal DCLK recovered by the sampling signal generator 300 are supplied to other components inside or outside the receiving apparatus 530 Data and clock signals.

20 shows an example in which the transmission apparatus 510 and the reception apparatus 530 are connected through a single transmission line 520. The transmission apparatus 510 and the reception apparatus 530 may be connected through two or more transmission lines. In addition, the interface system 500 may be a system using a serial interface. The interface system 500 includes a low voltage differential signaling (LVDS) interface, a transition minimized differential signaling (TMDS) interface, a reduced swing differential signaling (RSDS) interface, a point-to-point differential signaling (PPDS) attachment interface may be employed.

As described above, the clock recovery circuit and the sampling signal generator according to the embodiments of the present invention can accurately recover the clock signal from the clock embedded data. In addition, the clock recovery circuit and the sampling signal generator according to the embodiments of the present invention can speed up signal transmission by using an adaptively generated clock window signal.

The present invention can be usefully used in any interface device and system. In addition, the present invention can be applied to a low voltage differential signaling (LVDS) interface system, a transition minimized differential signaling (TMDS) interface system, a reduced swing differential signaling (RSDS) interface system, a point-to- serial advanced technology attachment) interface systems.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. You will understand.

1 is a block diagram illustrating a clock recovery circuit according to an embodiment of the present invention.

2 is a timing chart for explaining the operation of the clock recovery circuit of FIG.

FIG. 3A is a timing chart for explaining an example of the operation of the clock code detecting unit and the clock signal generating unit included in the clock recovery circuit of FIG. 1; FIG.

3B is a timing chart for explaining another example of the operation of the clock code detecting unit and the clock signal generating unit included in the clock recovery circuit of FIG.

3C is a timing chart for explaining another example of the operation of the clock code detecting unit and the clock signal generating unit included in the clock recovery circuit of FIG.

FIG. 3D is a timing chart for explaining another example of the operation of the clock code detection unit and the clock signal generation unit included in the clock recovery circuit of FIG.

4 is a block diagram showing a clock code detection unit included in the clock recovery circuit of FIG.

5 is a timing chart for explaining the operation of the clock code detecting unit of FIG.

6 is a diagram illustrating a clock signal generator included in the clock recovery circuit of FIG.

7 is a timing chart for explaining the operation of the clock signal generator of FIG.

8 is a block diagram showing a delay circuit included in the clock recovery circuit of FIG.

9 is a diagram showing an output part included in the clock recovery circuit of FIG.

10 is a block diagram illustrating a sampling signal generator including the clock recovery circuit of FIG.

11 is a diagram showing a delay line included in the sampling signal generator of FIG.

12 is a diagram illustrating a clock window generator included in the sampling signal generator of FIG.

FIG. 13 is a timing chart for explaining the operation of the delay line of FIG. 11 and the clock window generator of FIG. 12;

14 is a diagram illustrating a clock signal generator included in a clock recovery circuit according to another embodiment of the present invention.

15 is a diagram illustrating a clock window generator included in a sampling signal generator according to another embodiment of the present invention.

16 is a diagram illustrating a window signal generator included in the clock window generator of FIG.

17 is a diagram illustrating a window signal selector included in the clock window generator of FIG.

FIG. 18A is a timing chart for explaining an example of the operation of the window signal selecting unit of FIG. 17; FIG.

FIG. 18B is a timing chart for explaining another example of the operation of the window signal selecting unit of FIG. 17; FIG.

19 is a view showing a window signal selector included in the sampling signal generator according to still another embodiment of the present invention.

20 is a block diagram illustrating an interface system including a sampling signal generator in accordance with embodiments of the present invention.

Description of the Related Art

100: clock recovery circuit 110: clock code detection unit

111: rising detector 113: falling detector

115: rising-falling determiner 117: selector

130: clock signal generator 150: delay circuit

170: Output section 171: Clock output section

173: Data output unit 300: Sampling signal generator

400: delay locked loop circuit 410: phase frequency detector

420: lock detector 430: control signal generator

441, 442, 443, 444, 445, 446, 447, 448:

440: Delay Line 450: Clock Window Generator

460: Window signal generator 470: Window signal selector

Claims (17)

delete delete delete delete delete delete delete A clock recovery circuit for receiving a transmission signal comprising a clock code, detecting an edge of the clock code in the transmission signal in response to a clock window signal, and generating a clock signal based on an edge of the clock code; And And a delay locked loop circuit for generating a multi-phase clock signal based on the clock signal, generating the clock window signal based on the multi-phase clock signal, and outputting the multi-phase clock signal as a sampling signal, The delay locked loop circuit comprising: A delay line including a plurality of delay cells for sequentially delaying the clock signal to generate the multi-phase clock signal, the delay line generating a delayed clock signal in which the clock signal is delayed; A phase frequency detector for generating an up signal and a down signal based on a phase difference between the clock signal and the delayed clock signal; A control signal generator for generating a delay control signal for adjusting a delay time of the delay line in response to the up signal and the down signal; A lock detector for generating a lock detection signal in response to the up signal and the down signal; And And a clock window generator for performing a logic operation on the multi-phase clock signal to generate the clock window signal. delete 9. The apparatus of claim 8, wherein the clock window generator comprises: A first window signal is generated by performing a logic operation on two clock signals of the multiphase clock signal and a logical operation is performed on two clock signals adjacent to the two clock signals to generate a second window signal A window signal generator for selectively outputting the first window signal or the second window signal in response to a window selection signal; And And a window signal selector for detecting an interval between the edge of the first window signal and the clock code and generating the window selection signal based on the detected interval. 9. The clock recovery circuit according to claim 8, A clock code detector for receiving the transmission signal including the clock code, detecting an edge of the clock code in the transmission signal in response to the clock window signal, and generating a clock transition signal based on an edge of the clock code, ; And And a clock signal generator for generating the clock signal in response to the clock transition signal. The apparatus of claim 11, wherein the clock code detector comprises: A rising detector for detecting a rising edge of the clock code in the transmission signal and generating a rising edge detection signal; A falling detector for detecting a falling edge of the clock code in the transmission signal and generating a falling edge detection signal; A rising-falling determiner for determining whether the clock code has a rising edge or a falling edge and generating a rising-falling determining signal; And And a selector for selectively outputting the rising edge detection signal or the falling edge detection signal as the clock transition signal in response to the rising-falling determination signal. 13. The method of claim 12, Wherein the rising detector includes a first latch that outputs the clock window signal as the rising edge detection signal when the clock window signal has a logic high level and the transmission signal has a logic high level, Wherein the falling detector comprises a second latch for outputting the clock window signal as the falling edge detection signal when the clock window signal has a logic high level and the transmission signal has a logic low level, Wherein the rising-falling determiner comprises a flip-flop for outputting the transmission signal as the rising-falling decision signal in response to a rising edge of the clock window signal, Wherein the selector includes a multiplexer for receiving the rising-falling determination signal as a selection signal and selectively outputting the rising edge detection signal or the falling edge detection signal as the clock transition signal in response to the rising-falling determination signal Wherein the sampling signal generator comprises: The apparatus of claim 11, wherein the clock signal generator comprises: And generates the clock signal that makes a rising transition in response to the clock transition signal and a falling transition in response to a delayed clock transition signal in which the clock transition signal is delayed. The apparatus of claim 11, wherein the clock signal generator comprises: And generates the rising edge of the clock signal in response to the clock falling signal and the falling signal in response to the falling clock signal received from the delay locked loop circuit. 12. The clock recovery circuit according to claim 11, And a delay circuit for delaying the transmission signal by a delay time of the clock code detection unit and the clock signal generation unit. 17. The clock recovery circuit according to claim 16, A clock output unit for selectively outputting the clock signal output from the clock signal generation unit or the transmission signal output from the delay circuit in response to the lock detection signal; And And a data output section for selectively outputting the transmission signal output from the delay circuit in response to the lock detection signal.

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