KR20110017275A - Clock recovery circuit and sampling signal generator including the same - Google Patents

Abstract

PURPOSE: A clock recovery circuit and a sampling signal generating device including the same are provided to use an adaptively generated clock window signal, thereby transmitting a signal at high speed. CONSTITUTION: A clock code detecting unit(110) receives a transmission signal with a clock code to detect an edge of the clock code. The clock code detecting unit generates a clock transition signal based on an edge of the clock code. A clock signal generating unit(130) generates a restoration clock signal in response to the clock transition signal.

Description

CLOCK RECOVERY CIRCUIT AND SAMPLING SIGNAL GENERATOR INCLUDING THE SAME}

The present invention relates to a clock recovery circuit, and more particularly, to a clock recovery circuit for recovering a clock signal from clock embedded data and a sampling signal generator including the same.

Serial interfaces are widely used for high-speed signal transmission between devices, integrated circuits (ICs), modules, or systems. The serial interface can reduce the number of signal lines and eliminate skew between signals as compared with the conventional interface for transmitting data in parallel through a plurality of signal lines.

In recent years, a clock embedding technique for transferring a clock signal along with data to a data signal line has been studied to further reduce the number of signal lines and to speed up signal transmission. However, in the conventional interface system using clock embedding, data is encoded and transmitted to 8B / 10B, etc. so as to have a continuous transition for clock signal transmission, and the receiving device is encoded to recover the clock signal transmitted through the data signal line. Since data needs to be decoded, data overhead is large and circuitry is complicated.

In order to solve the above problems, it is an object of the present invention to provide a clock recovery circuit that can accurately recover a clock signal from the clock embedded data.

Another object of the present invention is to provide a sampling signal generator including the clock recovery circuit.

In order to achieve the object of the present invention, the clock recovery circuit according to the embodiments of the present invention includes a clock code detector and a clock signal generator.

The clock code detector receives a transmission signal including a clock code, detects an edge of the clock code in the transmission signal in response to a clock window signal, and generates a clock transition signal based on the edge of the clock code. The clock signal generator generates a recovery clock signal in response to the clock transition signal.

In one embodiment, the clock code detector, a rising detector for detecting a rising edge of the clock code in the transmission signal to generate a rising edge detection signal, detecting a falling edge of the clock code in the transmission signal A falling detector that generates a signal, a rising-falling determinant that generates a rising-falling decision signal by determining whether the clock code has a rising edge or a falling edge, and the clock transition in response to the rising-falling decision signal The signal may include a selector for selectively outputting the rising edge detection signal or the falling edge detection signal.

The rising detector includes a first latch for outputting the clock window signal as the rising edge detection signal when the clock window signal has a logic high level and the transmission signal has a logic high level; And a second latch for outputting the clock window signal as the falling edge detection signal when the clock window signal has a logic high level and the transmission signal has a logic low level, wherein the rising-falling determiner A flip-flop for outputting the transmission signal as the rising-falling determination signal in response to the rising edge of the clock window signal, wherein the selector receives the rising-falling determination signal as a selection signal, and the rising-falling The rising edge detection signal or the falling edge detection as the clock transition signal in response to a determination signal; The signal may comprise a multiplexer for selectively outputting.

In an example embodiment, the clock generator may generate the reconstructed clock signal that rises in response to the clock transition signal and falls in response to a delayed clock transition signal that delays the clock transition signal.

In an example embodiment, the clock generator may generate the recovery clock signal that rises and shifts in response to the clock transition signal and falls and transitions in response to the clock falling signal received from the delay locked loop circuit.

The clock recovery circuit may further include a delay unit configured to delay the transmission signal by a delay time of the clock code detector and the clock signal generator.

In one embodiment, the clock recovery circuit, the clock output unit for selectively outputting the recovery clock signal output from the clock signal generation unit or the transmission signal output from the delay unit in response to the lock detection signal, and the The apparatus may further include a data output unit configured to selectively output the transmission signal output from the delay circuit in response to the lock detection signal.

In order to achieve the above another object, the sampling signal generator according to embodiments of the present invention includes a clock recovery circuit and a delay locked loop circuit.

The clock recovery circuit receives a transmission signal comprising a clock code, detects an edge of the clock code in the transmission signal in response to a clock window signal, and generates a clock signal based on the edge of the clock code. The delay locked loop circuit generates a multi-phase clock signal based on the clock signal, generates the clock window signal based on the multi-phase clock signal, and outputs the multi-phase clock signal as a sampling signal.

In one embodiment, the delay lock loop circuit comprises: a delay line including a plurality of delay cells for sequentially delaying the clock signal to generate the multi-phase clock signal, the delay line generating a delayed clock signal delayed by the clock signal; A phase frequency detector for generating an up signal and a down signal based on a phase difference between the clock signal and the delayed clock signal, and generating a delay control signal for adjusting a delay time of the delay line in response to the up signal and the down signal A control signal generator, a lock detector generating a lock detection signal in response to the up signal and the down signal, and a clock window generator generating a clock window signal by performing a logical operation on the multi-phase clock signal. have.

In one embodiment, the clock window generator generates a first window signal by performing a logic operation on two clock signals of the multi-phase clock signal, and two clock signals adjacent to the two clock signals, respectively. Generating a second window signal by performing a logical operation on the window signal, and selectively outputting the first window signal or the second window signal in response to a window selection signal, and the first window signal and the clock. And a window signal selector configured to detect an interval between edges of a code and generate the window selection signal based on the detected interval.

The clock recovery circuit and the sampling signal generator according to the embodiments of the present invention can accurately recover the clock signal from the clock embedded data.

In addition, the clock recovery circuit and the sampling signal generator according to the embodiments of the present invention can speed up signal transmission by using an adaptively generated clock window signal.

With respect to the embodiments of the present invention disclosed herein, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms It should not be construed as limited to the embodiments set forth herein.

As the inventive concept allows for various changes and numerous modifications, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is said to be "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may exist in the middle. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same or similar reference numerals are used for the same components in the drawings.

1 is a block diagram illustrating a clock recovery circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the clock recovery circuit 100 includes a clock code detector 110, a clock signal generator 130, a delay circuit 150, and an output unit 170.

The clock code detector 110 receives a transmission signal RX including a clock code. The transmission signal RX may comprise serialized data bits and the clock code. The clock code may be periodically included in the transmission signal RX, and may be added in length of 1 bit or 2 bits for every N data bits (N is a natural number of 2 or more). In addition, the clock code may have a value opposite to that of an adjacent data bit. For example, if adjacent data bits have a logic high level, the clock code may have a logic low level, and if adjacent data bits have a logic low level, the clock code may have a logic high level. In one embodiment, the clock code may have a value opposite to the value of the immediately preceding data bit. In another embodiment, the clock code may have a value that is opposite to the value of the next data bit. The clock code having a value opposite to the value of an adjacent data bit may have a rising or falling edge between the clock code and the adjacent data bit.

The clock code detector 110 may detect an edge of the clock code from the transmission signal RX in response to the clock window signal CLKWIN. For example, the clock code detector 110 may receive the clock window signal CLKWIN from a delay locked loop (DLL) circuit. The clock window signal CLKWIN has a logic high level when the clock code rises or falls. The clock code detector 110 may detect an edge of the clock code in the transmission signal RX by detecting an edge of the transmission signal RX when the clock window signal CLKWIN has a logic high level. The clock window signal CLKWIN may generate a clock transition signal CTS that rises and shifts when the clock code transitions based on the detected edge of the clock code.

The clock signal generator 130 generates a recovery clock signal RCLK in response to the clock transition signal CTS. The clock signal generator 130 may generate a recovery clock signal RCLK that periodically transitions in response to the clock transition signal CTS. Accordingly, the clock signal generator 130 may generate the recovery clock signal RCLK having a period substantially the same as the period of the clock transition signal CTS.

The clock signal generator 130 may control the recovery clock signal RCLK so that the recovery clock signal RCLK rises and shifts when the clock transition signal CTS rises. In addition, the clock signal generator 130 controls the recovery clock signal RCLK so that the recovery clock signal RCLK falls in response to the delayed clock transition signal that delayed the clock transition signal CTS, or delay-locked loop. The recovery clock signal RCLK may be controlled to fall back in response to the clock falling signal received from the circuit.

The delay circuit 150 outputs the delayed transmission signal DRX by delaying the transmission signal RX. The delay circuit 150 outputs the delayed clock training signal by delaying the transmission signal RX including the clock training signal during the training period, and delays the transmission signal RX including the data bits during the data period, thereby delaying the data. You can output the bits.

The delay circuit 150 may delay the transmission signal RX by the delay time of the clock code detector 110 and the clock signal generator 130. Accordingly, the delay circuit 150 includes the delay signal 150 included in the transmission signal RX by a time delayed by the recovery clock signal RCLK generated by the clock code detector 110 and the clock signal generator 130 during the data period. It may delay the data bits. In addition, the delay circuit 150 may delay the clock training signal by the time that the recovery clock signal RCLK is delayed during the training period.

The output unit 170 outputs the recovered clock signal RCLK received from the clock signal generator 130 or the delayed transmission signal DRX received from the delay circuit 150 as the clock signal CLK, and the data DATA. ) May output the delayed transmission signal DRX received from the delay circuit 150. The output unit 170 may output the delayed transmission signal DRX, which is the delayed clock training signal received from the delay circuit 150, during the training period, as a clock signal CLK. In addition, the output unit 170 outputs the restored clock signal RCLK received from the clock signal generator 130 as the clock signal CLK during the data period, and the delayed data bit received from the delay circuit 150. The delayed transmission signal DRX including the data may be output as data DATA.

Since the clock recovery circuit 100 receives the transmission signal RX which is not encoded by a code such as 8B / 10B, the clock recovery circuit 100 may not perform separate decoding. In addition, the clock recovery circuit 100 may accurately and efficiently recover the clock signal by detecting the edge of the clock code from the transmission signal RX using the clock window signal CLKWIN.

FIG. 2 is a timing diagram for describing an operation of the clock recovery circuit of FIG. 1.

1 and 2, during the training period, the delay circuit 150 transmits the transmission signal RX, which is a clock training signal, by the delay time TD of the clock code detector 110 and the clock signal generator 130. The delayed output signal DRX is output by delaying, and the output unit 170 outputs the delayed transmission signal DRX received from the delay circuit 150 as the clock signal CLK. For example, the pulse 202 of the delayed transmission signal DRX is delayed by the delay time TD from the pulse 201 of the clock training signal and output as the pulse 203 of the clock signal CLK.

After a predetermined time has passed since the training period starts, the clock code detector 110 and the clock signal generator 130 detect the edge of the transmission signal RX to generate a recovery clock signal RCLK. The predetermined time may be a time from when the delay locked loop circuit, which receives the clock signal CLK as an input, receives the clock training signal until it is locked. That is, the clock code detector 110 and the clock signal generator 130 may generate a recovery clock signal RCLK after the delay lock loop circuit is locked. For example, the clock code detector 110 and the clock signal generator 130 may detect the rising edge of the pulse 204 of the clock training signal to generate the pulse 206 of the restored clock signal RCLK. According to an embodiment, the output unit 170 outputs the pulse 205 of the delayed transmission signal DRX as the pulse 207 of the clock signal CLK, or clocks the pulse 206 of the recovery clock signal RCLK. It can output as the pulse 207 of the signal CLK.

During the data period, the transmission signal RX includes data bits 209 and a clock code 208 added to the data bits 209. The delay circuit 150 outputs the delayed transmission signal DRX by delaying the transmission signal RX by the delay time TD. The output unit 170 outputs the delayed transmission signal DRX received from the delay circuit 150 as data DATA. For example, the clock code 210 and the data bits 211 in which the clock code 208 and the data bits 209 are delayed by the delay time TD may be output as the data DATA. The clock code 212 and / or data bits 213 output as data DATA may be parallelized by a sampler.

During the data period, the clock code detector 110 and the clock signal generator 130 detect the edge of the clock code 208 to generate a recovery clock signal RCLK, and the output unit 170 generates a recovery clock signal ( RCLK) is output as the clock signal CLK. For example, the clock code detector 110 detects an edge between the clock code 208 and the data bits 209 to generate a clock transition signal CTS, and the clock signal generator 130 generates a clock transition signal. In response to CTS, a pulse 214 of the recovery clock signal RCLK is generated, and the output unit 170 uses the pulse 214 of the recovery clock signal RCLK as the pulse 215 of the clock signal CLK. You can print

3A is a timing diagram illustrating an example of operations of a clock code detector and a clock signal generator included in the clock recovery circuit of FIG. 1.

1 and 3A, the clock codes 214 and 219 included in the transmission signal RX have a length of 1 bit and have values opposite to the values of the next data bits 215 and 221. For example, clock code 214 has a logic low level as opposed to the next data bit 215 having a logic high level, and clock code 219 is opposed to the next data bit 220 having a logic low level. It may have a logic high level. Accordingly, clock codes 214 and 219 may have edges 216 and 221 between clock codes 214 and 219 and next data bits 215 and 220. For example, clock code 214 can have rising edge 216 and clock code 219 can have falling edge 221.

The clock code detector 110 may detect an edge of the transmission signal RX when the clock window signal CLKWIN has a logic high level. In addition, the clock window signal CLKWIN may have a logic high level from one time point of the clock codes 214 and 215 to one time point of the next data bits 219 and 220. Accordingly, the clock code detector 110 may detect edges of the clock codes 214 and 219. For example, the clock code detector 110 detects the rising edge 216 of the clock code 214 in response to the pulse 217 of the clock window signal CLKWIN, and the pulse 222 of the clock window signal CLKWIN. ), The falling edge 221 of the clock code 219 can be detected. The clock code detector 110 outputs a clock transition signal CTS that rises and transitions at the edges 216 and 221 of the clock codes 214 and 219 as a detection result.

The clock signal generator 130 generates a recovery clock signal RCLK in response to the clock transition signal CTS. The clock signal generator 130 may generate a recovery clock signal RCLK that periodically rises and shifts in response to the pulses 218 and 223 of the clock transition signal CTS.

3B is a timing diagram illustrating another example of operations of the clock code detector and the clock signal generator included in the clock recovery circuit of FIG. 1.

1 and 3B, the clock code 224 included in the transmission signal RX has a length of one bit and has a value opposite to the value of the previous data bit 225. For example, clock code 224 may have a logic low level as opposed to previous data bit 225 having a logic high level, and may have falling edge 226 between previous data bits 225. The clock code detector 110 may respond to the clock code 224 in response to the pulse 227 of the clock window signal CLKWIN having a logic high level up to one point of the clock code 224 until one point of the previous data bit 225. Edge 226 may be detected, and a clock transition signal CTS that rises and transitions at edge 226 of clock code 224 may be generated. The clock signal generator 130 may generate a restored clock signal RCLK that rises and shifts in response to the pulse 228 of the clock transition signal CTS.

3C is a timing diagram illustrating another example of operations of a clock code detector and a clock signal generator included in the clock recovery circuit of FIG. 1.

1 and 3C, the clock code 229 included in the transmission signal RX is two bits long and has a value opposite to the value of the next data bit 230. For example, clock code 229 may have a logic low level as opposed to next data bit 230 having a logic high level, and may have a rising edge 231 between the next data bit 230. The clock code detection unit 110 responds to the clock code in response to the pulse 232 of the clock window signal CLKWIN having a logic high level from one time point of the first bit of the clock code 229 to one time point of the next data bit 230. The edge 231 of 229 may be detected, and a clock transition signal CTS that rises and transitions at the edge 231 of the clock code 229 may be generated. The clock signal generator 130 may generate a restored clock signal RCLK that rises and shifts in response to the pulse 233 of the clock transition signal CTS.

FIG. 3D is a timing diagram illustrating another example of operations of the clock code detector and the clock signal generator included in the clock recovery circuit of FIG. 1.

1 and 3D, the clock code 234 included in the transmission signal RX is two bits long and has a value opposite to the value of the previous data bit 235. For example, clock code 234 may have a logic low level as opposed to previous data bit 235 having a logic high level, and may have falling edge 236 between previous data bits 235. The clock code detector 110 clocks in response to the pulse 238 of the clock window signal CLKWIN having a logic high level from one time point of the previous data bit 235 to one time point of the second bit of the clock code 234. The edge 236 of the code 234 can be detected and a clock transition signal CTS that generates a rising transition at the edge 236 of the clock code 234 can be generated. The clock signal generator 130 may generate a restored clock signal RCLK that rises and shifts in response to the pulse 238 of the clock transition signal CTS.

As shown in FIGS. 3A-3D, the clock code may have a length of at least one bit and may have an edge between the previous or next bit. For convenience of explanation, although the delays due to the clock code detector and the clock signal generator are not illustrated in FIGS. 3A to 3D, the reconstructed clock signal may be delayed with respect to the edge of the clock code by the clock code detector and the clock signal generator. . In addition, the clock recovery circuit uses a clock window signal that is adaptively selected according to the transmission rate and / or the delay amount, as will be described later with reference to FIGS. 17 to 21B, so that the clock code edge is accurately corrected even if the clock code is delayed. Can be detected to generate a recovered clock signal.

4 is a block diagram illustrating a clock code detector included in the clock recovery circuit of FIG. 1.

Referring to FIG. 4, the clock code detector 110 includes a rise detector 111, a fall detector 113, a rise-fall determiner 115, and a selector 117.

The rising detector 111 detects the rising edge of the clock code included in the transmission signal RX based on the clock window signal CLKWIN to generate the rising edge detection signal REDS. The falling detector 113 detects the falling edge of the clock code included in the transmission signal RX based on the clock window signal CLKWIN to generate the falling edge detection signal FEDS. The rising edge detection signal REDS is activated in response to the rising edge of the clock code if the clock code has a rising edge, and the falling edge detection signal FEDS is falling the clock code when the clock code has a falling edge. It may be activated in response to the edge.

In one embodiment, the rising detector 111 includes a data terminal to which the clock window signal CLKWIN is applied, an enable terminal to which the transmission signal RX is applied, an inverting reset terminal to which the clock window signal CLKWIN is applied, and a rising edge. It may include a first gated latch having an output terminal to which the edge detection signal (REDS) is output. The rising detector 111 may be reset when the clock window signal CLKWIN has a logic low level. The rising detector 111 outputs the clock window signal CLKWIN as it is when the clock window signal CLKWIN has a logic high level, and the transmission signal RX has a logic high level, and the transmission signal RX The previous output can be retained when having a logic low level.

The falling detector 113 includes a data terminal to which the clock window signal CLKWIN is applied, an inverting enable terminal to which the transmission signal RX is applied, an inverting reset terminal to which the clock window signal CLKWIN is applied, and a falling edge detection signal ( FEDS) may include a second gated latch having an output terminal to which the FEDS is output. The falling detector 113 may be reset when the clock window signal CLKWIN has a logic low level. The falling detector 113 outputs the clock window signal CLKWIN as it is when the clock window signal CLKWIN has a logic high level, and the transmission signal RX has a logic low level, and the transmission signal RX The previous output can be retained when it has a logic high level.

The rising-falling determiner 115 determines whether the clock code included in the transmission signal RX has the rising edge or the falling edge based on the clock window signal CLKWIN to generate the rising-falling determination signal RFDS. Create For example, the rise-fall determiner 115 generates a rise-fall decision signal (RFDS) having a logic low level when the clock code has a rising edge and a logic high level when the clock code has a falling edge. A rising-falling decision signal (RFDS) may be generated.

In one embodiment, the rise-fall determiner 115 is a data terminal to which the transmission signal RX is applied, a clock terminal to which the clock window signal CLKWIN is applied, and an output terminal to which the rise-fall determination signal RFDS is output. And a rising edge triggered flip-flop having: The rising-falling determiner 115 may output the transmission signal RX as a rising-falling determination signal RFDS in response to the rising edge of the clock window signal CLKWIN.

The selector 117 is a rising edge detection signal (REDS) or falling edge received from the rising detector (111) as a clock transition signal (CTS) in response to the rising-falling determination signal (RFDS) received from the rising-falling determiner (115). The falling edge detection signal FEDS received from the detector 113 is selectively output.

In one embodiment, the selector 117 is applied with the rising edge detection signal (REDS), the first input terminal, the second input terminal to which the falling edge detection signal (FEDS) is applied, the rising-fall determination signal (RFDS) is applied. It may include a multiplexer having a selection terminal and an output terminal to which the clock transition signal (CTS) is output. For example, the selector 117 outputs the rising edge detection signal REDS as the clock transition signal CTS when the rising-falling determination signal RFDS has a logic low level, and the rising-falling determination signal RFDS. ) May output the falling edge detection signal FEDS as the clock transition signal CTS.

The clock code detector 110 may detect an edge of the clock code regardless of whether the clock code has a rising edge or a falling edge.

FIG. 5 is a timing diagram for describing an operation of the clock code detector of FIG. 4.

4 and 5, when the clock code 239 having the logic low level is applied to the enable terminal, the rising detector 111 maintains the previous output to maintain the previous output and has the rising edge detection signal having the logic low level. REDS) is printed. When a data bit 240 having a logic high level is applied to an enable terminal of the rise detector 111, the rise detector 111 outputs a clock window signal CLKWIN having a logic high level as it is to have a logic high level. The rising edge detection signal REDS may be output. When the clock window signal CLKWIN transitions to the logic low level, the rising detector 111 is reset to output the rising edge detection signal Reds having the logic low level again. Accordingly, the rising detector 111 may generate a rising edge detection signal REDS having a pulse 243 that rises in response to the rising edge of the clock code 239. Similarly, falling detector 113 may generate falling edge detection signal FEDS having a pulse 247 rising in response to the falling edge of the clock code.

The rising-falling determiner 115 may output the transmission signal RX as a rising-falling determination signal RFDS in response to the rising edge of the clock window signal CLKWIN. For example, the rise-fall determiner 115 has a logic low level 245 by latching a clock code 239 having a logic low level in response to the rising edge of the pulse 242 of the clock window signal CLKWIN. A rise-fall decision signal (RFDS) may be output.

The selector 117 selectively outputs the rising edge detection signal Reds or the falling edge detection signal FEDS as the clock transition signal CTS in response to the rising-falling determination signal RFDS. For example, the selector 117 outputs the rising edge detection signal REDS as the clock transition signal CTS and rises-down when the rising-falling determination signal RFDS has a logic low level 245. When the decision signal RFDS has a logic high level 248, the falling edge detection signal FEDS may be output as the clock transition signal CTS. Accordingly, the clock transition signal CTS may have pulses 246 and 249 rising at the edge of the clock code.

FIG. 6 is a diagram illustrating a clock signal generator included in the clock recovery circuit of FIG. 1.

Referring to FIG. 6, the clock signal generator 130 includes an SR latch 131 and a delay circuit 132.

The delay circuit 132 outputs a delayed clock transition signal DCTS by delaying the clock transition signal CTS. The delayed clock transition signal DCTS may have a pulse delayed by a predetermined delay time with respect to the pulse of the clock transition signal CTS.

The SR latch 131 has a set terminal to which the clock transition signal CTS is applied, a reset terminal to which the delay clock transition signal DCTS is applied, and an output terminal to which the recovery clock signal RCLK is output. The SR latch 131 outputs a recovery clock signal RCLK having a logic high level when the clock transition signal CTS is at a logic high level, and a logic low level when the delay clock transition signal DCTS is at a logic high level. The recovery clock signal RCLK is outputted, and the previous output is maintained when both the clock transition signal CTS and the delay clock transition signal DCTS have a logic low level. Accordingly, the SR latch 131 may generate a recovery clock signal RCLK that rises when the clock transition signal CTS rises and falls when the delay clock transition signal DCTS rises. .

FIG. 7 is a timing diagram for describing an operation of the clock signal generator of FIG. 6.

6 and 7, the clock signal generator 130 transitions from the logic low level to the logic high level 254 in response to the rising edge of the pulse 252 of the clock transition signal CTS, and delays it. In response to the rising edge of the pulse 253 of the clock transition signal DCTS, the reconstructed clock signal RCLK falling from the logic high level 254 to the logic low level 255 may be generated. Accordingly, the clock signal generator 130 may generate a periodic recovery clock signal RCLK that rises and transitions at the edge of the clock code 250.

8 is a block diagram illustrating a delay circuit included in the clock recovery circuit of FIG. 1.

Referring to FIG. 8, the delay circuit 150 includes a detector replication delayer 151, a selector replication delayer 153, and a latch replication delayer 155.

The detector replication delayer 151 delays the transmission signal RX by the delay time of the rising detector 111 or the falling detector 111 of FIG. 4, and the selector replication delayer 153 is the selector 117 of FIG. 4. Further, the transmission signal RX may be further delayed by a delay time, and the latch copy delayer 155 may further delay the transmission signal RX by the delay time of the SR latch 131 of FIG. 6. The delay circuit 150 may delay the transmission signal RX by a time for which the recovery clock signal RCLK generated by the clock code detector 110 and the clock signal generator 130 of FIG. 1 is delayed. Accordingly, the clock recovery circuit 100 of FIG. 1 may output the clock signal CLK and the data DATA delayed by substantially the same delay time.

9 is a block diagram illustrating an output unit included in the clock recovery circuit of FIG. 1.

9, the output unit 170 includes a clock output unit 171 and a data output unit 173.

The clock output unit 171 may selectively output the recovery clock signal RCLK or the delayed transmission signal DRX as the clock signal CLK. For example, the clock output unit 171 may output the delayed transmission signal DRX as the clock signal CLK during the training period, and output the recovery clock signal RCLK as the clock signal CLK during the data period. have.

In an embodiment, the clock output unit 171 may include a first input terminal to which the recovery clock signal RCLK is applied, a second input terminal to which the delay transmission signal DRX is applied, and an inversion lock detection signal LDSB. It may include a multiplexer having a selection terminal and an output terminal to which the clock signal CLK is output. The inverted lock detection signal LDSB is an inverted signal of the lock detection signal LDS and may be output from a delay locked loop circuit that receives the clock signal CLK. The delay locked loop circuit may output a lock detection signal LDS having a logic high level when locked by the clock signal CLK. Accordingly, the clock output unit 171 outputs the delayed transmission signal DRX as the clock signal CLK before the delay locked loop circuit is locked, and restores the recovered clock signal RCLK after the delay locked loop circuit is locked. ) May be output as the clock signal CLK. The data output unit 173 may selectively output the delayed transmission signal DRX as the data DATA. For example, the data output unit 173 may output the delayed transmission signal DRX as the data DATA during the data period without outputting the data DATA during the training period.

In one embodiment, the data output unit 173 may include a transmission gate controlled by the lock detection signal LDS and the inversion lock detection signal LDSB. The data output unit 173 may output the delayed transmission signal DRX when the lock detection signal LDS has a logic high level and the inversion lock detection signal LDSB has a logic low level. Accordingly, the data output unit 173 may output data DATA during the data period.

FIG. 10 is a block diagram illustrating a sampling signal generator including the clock recovery circuit of FIG. 1.

Referring to FIG. 10, the sampling signal generator 300 includes a clock recovery circuit 100 and a delay locked loop circuit 400. The delay locked loop circuit 400 includes a phase frequency detector 410, a lock detector 420, a control signal generator 430, a delay line 440, and a clock window generator 450.

The clock recovery circuit 100 receives the transmission signal RX including the clock code and generates the clock signal CLK by detecting an edge of the clock code in response to the clock window signal CLKWIN. In addition, the clock recovery circuit 100 may output the transmission signal RX as the data DATA during the data period.

The phase frequency detector 410 detects a phase difference between the clock signal CLK received from the clock recovery circuit 100 and the delayed clock signal DCLK received from the delay line 440, and delays the clock signal CLK. The up signal UP and the down signal DN are generated based on the detected phase difference of the clock signal DCLK. The control signal generator 430 generates a delay control signal CTRL in response to the up signal UP and the down signal DN received from the phase frequency detector 410. The control signal generator 430 may include a charge pump generating a charge current in response to the up signal UP and generating a discharge current in response to a down signal DN, and a clock signal charged or discharged by the charge pump. And a loop filter for generating a delay control signal CTRL corresponding to a phase difference between the CLK and the delayed clock signal DCLK.

For example, when the delay clock signal DCLK is later than the clock signal CLK, the phase frequency detector 410 generates an up signal UP having a logic high level, and the control signal generator 430 generates the up signal. In response to UP, a delay control signal CTRL may be generated to reduce the delay time of the delay line 440. In addition, when the delay clock signal DCLK is earlier than the clock signal CLK, the phase frequency detector 410 generates the down signal DN having a logic high level, and the control signal generator 430 generates the down signal DN. ) May generate a delay control signal CTRL that increases the delay time of the delay line 440.

The lock detector 420 generates a lock detection signal LDS indicating whether the delay locked loop circuit 400 is locked based on the up signal UP and the down signal DN. For example, the lock detector 420 generates a lock detection signal LDS having a logic high level when the up signal UP and the down signal DN have a logic high level or when a difference is less than a predetermined time. can do.

The delay line 440 delays the clock signal CLK received from the clock recovery circuit 100 to generate the delayed clock signal DCLK. In addition, the delay line 440 may include a plurality of delay cells that sequentially delay the clock signal CLK, and generate a multi-phase clock signal MPCS including clock signals output from the plurality of delay cells, respectively. Can be. In addition, the delay line 440 may provide the multi-phase clock signal MPCS to the clock window generator 450, and may provide the multi-phase clock signal MPCS to the external sampler as the sampling signal SS. .

The clock window generator 450 generates the clock window signal CLKWIN based on the multi-phase clock signal MPCS received from the delay line 440. The clock window generator 450 may perform a logic operation on the multi-phase clock signal MPCS to generate the clock window signal CLKWIN. In addition, the clock window generator 450 may adaptively generate the clock window signal CLKWIN according to the data rate of the transmission signal RX and / or the delay amount of the clock recovery circuit 100. Although the clock window generator 450 is illustrated in FIG. 10 to be included in the delay locked loop circuit 400, some or all of the clock window generator 450 may be located outside the delay locked loop circuit 400. It may be included in the clock recovery circuit 100.

The sampling signal generator 300 may accurately and efficiently recover the clock signal CLK from the transmission signal RX by using the clock window signal CLKWIN, and may extract the sampling signal SS corresponding to the data DATA. Can be generated.

FIG. 11 is a block diagram illustrating a delay line included in the sampling signal generator of FIG. 10.

Referring to FIG. 11, the delay line 440 includes first through N + 3th delay cells 441, 442, 443, 444, 445, 446, 447, and 448.

The first to N + 3 delay cells 441, 442, 443, 444, 445, 446, 447, and 448 sequentially delay the clock signal CLK, so that the first to third clock signals CLK_1, CLK_2, CLK_A, CLK_B, CLK_N, CLK_N + 1, CLK_N + 2, and CLK_N + 3) are output respectively. The first to N + 3th delay cells 441, 442, 443, 444, 445, 446, 447, and 448 may delay a clock signal input by substantially the same delay time. In addition, the first to N + 3th delay cells 441, 442, 443, 444, 445, 446, 447, and 448 may be controlled to increase or decrease the delay time by the delay control signal CTRL.

Each of the first to N + 3th delay cells 441, 442, 443, 444, 445, 446, 447, and 448 may include a plurality of sub delay cells. For example, the second delay cell 442 includes a first sub delay cell 442a, a second sub delay cell 442b, a third sub delay cell 442c, and a fourth sub delay cell 442d. can do. Each of the first to N + 3 delay cells 441, 442, 443, 444, 445, 446, 447, and 448 may include first to third clock signals CLK_1, CLK_2, and CLK_A in the middle of the plurality of sub delay cells. , CLK_B, CLK_N, CLK_N + 1, CLK_N + 2, and CLK_N + 3) can be output respectively. For example, the second delay cell 442 may output the second clock signal CLK_2 at the output node of the second sub delay cell 442b, that is, the input node of the third sub delay cell 442c.

In one embodiment, when the transmission signal comprises N data bits and a 2-bit long clock code added every N data bits, the delay line 440 may include N + 3 delay cells 441, 442,. 443, 444, 445, 446, 447, 448). The delay line 440 may output the delay clock signal DCLK at an output node of the N + 2th delay cell 447, that is, an input node of the N + 3th delay cell 448. Accordingly, since the transmission signal includes N + 2 bits every period, the delay line 440 outputs the delayed clock signal DCLK by delaying the clock signal CLK by the delay time of the N + 2 delay cells. The delay time of each delay cell may correspond to one bit length of the transmission signal.

FIG. 12 is a diagram illustrating an example of a clock window generator included in the sampling signal generator of FIG. 10.

Referring to FIG. 12, the clock window generator 450 includes an AND gate 451 and an inverter 452.

The inverter 452 inverts the N + 3th clock signal CLK_N + 3. The AND gate 451 performs an AND operation on an inverted signal of the N + 1 th clock signal CLK_N + 1 and the N + 3 th clock signal CLK_N + 3. The AND gate 451 has a logic high level when the N + 1 th clock signal CLK_N + 1 has a logic high level and the N + 3 th clock signal CLK_N + 3 has a logic low level. The window signal CLKWIN can be generated. Accordingly, the clock window generator 450 has a clock window signal CLKWIN having a logic high level from the rising edge of the N + 1 th clock signal CLK_N + 1 to the rising edge of the N + 3 th clock signal CLK_N + 3. ) Can be created.

FIG. 13 is a timing diagram for describing an operation of the delay line of FIG. 11 and the clock window generator of FIG. 12.

11 to 13, the clock signal CLK rises and transitions at the edge 256 of the clock code, and the delay clock signal DCLK may have substantially the same phase as the clock signal CLK. The first clock signal CLK_1 output in the middle of the sub delay cells included in the first delay cell 441 may rise and shift in the middle of the first data bit D1. Also, the second to Nth clock signals CLK_2, CLK_A, CLK_B, and CLK_N may rise and transition in the middle of the second to Nth data bits D2, DA, DB, and DN, respectively. Accordingly, the first to Nth clock signals CLK_1, CLK_2, CLK_A, CLK_B, and CLK_N may be used to sample the first to Nth data bits D1, D2, DA, DB, and DN, respectively. have.

The N + 1 th clock signal CLK_N + 1 may rise and shift in the middle of the first bit of the clock code CC, and the N + 2 th clock signal CLK_N + 2 is the second of the clock code CC. It can rise in the middle of the bit. In addition, the N + 3 th clock signal CLK_N + 3 may rise in the middle of the first data bit D1 of the next period. That is, the N + 3 delay cell 448 may output the N + 3 clock signal CLK_N + 3 delayed by one period from the first clock signal CLK_1 output from the first delay cell 441.

The clock window generator 450 may generate a clock window signal CLKWIN by performing a logic operation on the N + 1 th clock signal CLK_N + 1 and the N + 3 th clock signal CLK_N + 3. For example, the clock window generator 450 inverts the N + 3 th clock signal CLK_N + 3, and the clock window generator 450 inverts the N + 3 th clock signal CLK_N + 1 and the N + 3 th clock signal CLK_N + 3. The clock window signal CLKWIN may be generated by performing an AND operation on the inverted signal. Accordingly, the clock window signal CLKWIN has an N + 1 th clock signal CLK_N + 1 having a logic high level 258 and an N + 3 th clock signal CLK_N + 3 having a logic low level 259. May have a logic high level 260. The clock recovery circuit 100 of FIG. 1 detects the edge 256 of the transmission signal RX based on the clock window signal CLKWIN having the logic high level 260, and the edge 256 of the transmission signal RX. ) May generate a clock signal CLK having a rising edge 257.

As such, the clock recovery circuit and the sampling signal generator according to the embodiment of the present invention can accurately recover the clock signal from the clock embedded data by detecting the edge of the clock code using the clock window signal.

14 is a diagram illustrating a clock signal generator included in a clock recovery circuit according to another exemplary embodiment of the present invention.

Referring to FIG. 14, the clock signal generator 130 includes an SR latch 131.

The SR latch 131 has a set terminal to which the clock transition signal CTS is applied, a reset terminal to which the clock falling signal CFS is applied, and an output terminal to which the recovery clock signal RCLK is output. The SR latch 131 outputs a recovery clock signal RCLK having a logic high level when the clock transition signal CTS is at a logic high level, and outputs a logic low level when the clock falling signal CFS is at a logic high level. The branch outputs a recovery clock signal RCLK and maintains the previous output when both the clock transition signal CTS and the clock falling signal CFS have a logic low level. Accordingly, the SR latch 131 may generate a recovery clock signal RCLK that rises when the clock transition signal CTS rises and falls when the clock fall signal CFS rises.

The clock signal generator 130 may receive the clock falling signal CFS from the delay locked loop circuit 400 of FIG. 10 according to another exemplary embodiment of the present invention. The delay locked loop circuit 400 of FIG. 10 may further include a circuit for generating a clock falling signal CFS based on the multi-phase clock signal MPCS. For example, the circuit for generating the clock falling signal CFS may have a configuration similar to the clock window generator 450 of FIG. 12.

Referring back to FIG. 13, the clock falling signal CFS may be generated by performing an AND operation on the inverted signals of the A-th clock signal CLK_A and the B-th clock signal CLK_B. Accordingly, the clock falling signal CFS has a logic high level when the A clock signal CLK_A has a logic high level 262 and the B clock signal CLK_B has a logic low level 263. 264). The A-th clock signal CLK_A and the B-th clock signal CLK_B may be signals output from two delay cells positioned in the middle of the delay line 440 of FIG. 11. For example, the A-th clock signal CLK_A is a signal output from the N / 2 + 1th delay cell among the N + 3 delay cells included in the delay line 440, and the B-th clock signal CLK_B is N It may be a signal output from the / 2 + 2th delay cell. The clock recovery circuit including the clock signal generator 130 according to another exemplary embodiment of the present invention may include a clock signal CLK having the falling edge 261 in response to the clock falling signal CFS having the logic high level 264. ) Can be created.

According to another embodiment of the present invention, the clock signal generator 130 of FIG. 14 is received from the delay locked loop circuit 400 of FIG. 10 without the delay circuit 132 compared to the clock signal generator 130 of FIG. 6. The recovery clock signal RCLK may be generated based on the clock falling signal CFS.

15 illustrates a clock window generator included in a sampling signal generator according to another embodiment of the present invention.

10 and 15, the clock window generator 450 includes a window signal generator 460 and a window signal selector 470.

The window signal generator 460 receives at least a portion of the multi-phase clock signal from the delay line 440. For example, the window signal generator 460 may include an N-th clock signal CLK_N, an N + 1 th clock signal CLK_N + 1, an N + 2 th clock signal CLK_N + 2, and the multi-phase clock signal. An N + 3 th clock signal CLK_N + 3 may be received.

The window signal generator 460 is Nth plus one clock signal CLK_N + 1 that is about 1.5 bits long with respect to the delayed clock signal DCLK and Nth delayed by about 0.5 bits with respect to the delayed clock signal DCLK. Logic high level is performed between the rising edge of the N + 1th clock signal CLK_N + 1 and the rising edge of the N + 3th clock signal CLK_N + 3 by performing a logic operation on the +3 clock signal CLK_N + 3. The first window signal CLKWIN1 may be generated. In addition, the window signal generation unit 460 may be N-th clock signal CLK_N preceding the delayed clock signal DCLK by about 2.5 bits and N + 2 preceding the delayed clock signal DCLK by about 0.5 bits. By performing a logic operation on the clock signal CLK_N + 2, the second window signal having a logic high level is provided between the rising edge of the Nth clock signal CLK_N and the rising edge of the N + 2th clock signal CLK_N + 2. CLKWIN2) can be created.

The window signal selector 470 may receive the first window signal CLKWIN1 and / or the second window signal CLKWIN2 from the window signal generator 460. The window signal selector 470 may detect an interval between the first window signal CLKWIN1 and / or the second window signal CLKWIN2 and an edge of a clock code included in the transmission signal RX. The window signal selector 470 may determine whether the detected interval is equal to or greater than a predetermined value and generate a window selection signal WINSEL indicating the first window signal CLKWIN1 or the second window signal CLKWIN2.

In an embodiment, the window signal selector 470 may determine whether the first window signal CLKWIN1 has a constant margin with respect to the edge of the clock code included in the transmission signal RX. For example, the window signal selector 470 may include the first window signal CLKWIN1 when the rising edge of the first window signal CLKWIN1 is about 0.5 bit or more long as the constant margin with respect to the edge of the clock code. A window selection signal WINSEL may be generated. The window signal selector 470 may select the second window signal CLKWIN2 when the rising edge of the first window signal CLKWIN1 is not more than about 0.5 bits long from the transmission signal RX with respect to the edge of the clock code. The window selection signal WINSEL may be generated.

The window signal generator 460 may receive the first window signal CLKWIN1 or the second window signal CLKWIN2 as the clock window signal CLKWIN in response to the window selection signal WINSEL received from the window signal selector 470. You can optionally output it.

When the transmission rate of the transmission signal RX is high and the delay time of the clock signal CLK by the clock recovery circuit 100 or the delayed clock signal DCLK corresponding to the clock signal CLK is significant, the delayed clock signal DCLK The clock window signal CLKWIN generated based on the reference may not be suitable for edge detection of the clock code included in the transmission signal RX. However, the sampling signal generator 300 including the clock window generator 450 according to another embodiment of the present invention accurately generates the clock window signal CLKWIN according to the transmission rate and / or the delay amount, thereby accurately correcting the clock. The edge of the code may be detected to generate a clock signal CLK and a sampling signal SS.

FIG. 16 is a diagram illustrating a window signal generator included in the clock window generator of FIG. 15.

Referring to FIG. 16, the included window signal generator 460 includes a first inverter 461, a first AND gate 462, a second inverter 463, a second AND gate 464, and a multiplexer 465. It includes.

The first inverter 461 inverts the N + 3 th clock signal CLK_N + 3. The first AND gate 462 performs an AND operation on an inverted signal of the N + 1 th clock signal CLK_N + 1 and the N + 3 th clock signal CLK_N + 3. The first AND gate 462 has a logic high level when the N + 1 th clock signal CLK_N + 1 has a logic high level and the N + 3 th clock signal CLK_N + 3 has a logic low level. The first window signal CLKWIN1 may be generated. Accordingly, the first window signal CLKWIN1 may have a logic high level from the rising edge of the N + 1 th clock signal CLK_N + 1 to the rising edge of the N + 3 th clock signal CLK_N + 3.

The second inverter 463 inverts the N + 2th clock signal CLK_N + 2. The second AND gate 464 performs an AND operation on an inverted signal of the Nth clock signal CLK_N and the N + 2th clock signal CLK_N + 2. The second AND gate 464 has a second window signal having a logic high level when the N-th clock signal CLK_N has a logic high level and the N + 2 clock signal CLK_N + 2 has a logic low level. You can create (CLKWIN2). Accordingly, the second window signal CLKWIN2 may have a logic high level from the rising edge of the N th clock signal CLK_N to the rising edge of the N + 2 th clock signal CLK_N + 2.

The multiplexer 465 may include a window selection signal from the first input terminal to which the first window signal CLKWIN1 is applied, the second input terminal to which the second window signal CLKWIN2 is applied, and the window signal selection unit 470 of FIG. 17. And a selection terminal to which the WINSEL is applied and an output terminal to which the clock window signal CLKWIN is output. The multiplexer 465 selectively outputs the first window signal CLKWIN1 or the second window signal CLKWIN2 as the window selection signal WINSEL in response to the window selection signal WINSEL. For example, the multiplexer 465 outputs the first window signal CLKWIN1 as the clock window signal CLKWIN when the window select signal WINSEL has a logic high level, and the window select signal WINSEL is logic low. When having a level, the second window signal CLKWIN2 may be output as the clock window signal CLKWIN.

17 is a diagram illustrating an example of a window signal selector included in the clock window generator of FIG. 15.

Referring to FIG. 17, the window signal selector 470 includes a delay circuit 471, a first flip-flop 472, a second flip-flop 473, and an XOR gate 474.

The delay circuit 471 receives the first window signal CLKWIN1 received from the window signal generator 460 of FIG. 17. The delay circuit 471 may delay the first window signal CLKWIN1 by about 0.5 bits in length, that is, half of the delay time of the delay cell included in the delay line. The delay time of the delay circuit 471 may be determined according to the margin for the edge of the clock code in which the first window signal CLKWIN1 is included in the transmission signal RX.

The first flip-flop 472 latches the transmission signal RX in response to the first window signal CLKWIN1 delayed by the delay circuit 471. The first flip-flop 472 is a rising edge triggered having a data terminal to which the transmission signal RX is applied, a clock terminal to which the first window signal CLKWIN1 delayed by the delay circuit 471 is applied, and an output terminal. It may be a flip-flop. Accordingly, the first flip-flop 472 may output the value of the transmission signal RX at the rising edge of the first window signal CLKWIN1 delayed by the delay circuit 471.

The second flip-flop 473 latches the transmission signal RX in response to the first window signal CLKWIN1 delayed by the delay circuit 471. The second flip-flop 473 is a falling edge triggered having a data terminal to which the transmission signal RX is applied, a clock terminal to which the first window signal CLKWIN1 delayed by the delay circuit 471 is applied, and an output terminal. It may be a flip-flop. Accordingly, the second flip-flop 473 may output the value of the transmission signal RX at the falling edge of the first window signal CLKWIN1 delayed by the delay circuit 471.

The XOR gate 474 performs an XOR operation on the output signal of the first flip-flop 472 and the output signal of the second flip-flop 473. When the output signal of the first flip-flop 472 and the output signal of the second flip-flop 473 have the same logic level, the first window signal CLKWIN1 is the clock code included in the transmission signal RX. Not suitable for edge detection. Accordingly, the XOR gate 474 generates the window select signal WINSEL having a logic low level, and the multiplexer 465 of FIG. 18 may output the second window signal CLKWIN2 as the clock window signal CLKWIN. have.

When the output signal of the first flip-flop 472 and the output signal of the second flip-flop 473 have the same logic level, the first window signal CLKWIN1 is the clock code included in the transmission signal RX. It has a margin equal to the delay time of the delay circuit 471 with respect to the edge, and is suitable for edge detection of the clock code. Accordingly, the XOR gate 474 generates the window select signal WINSEL having a logic high level, and the multiplexer 465 of FIG. 16 may output the first window signal CLKWIN1 as the clock window signal CLKWIN. have.

As such, the clock window generator including the window signal selector 470 may generate a clock window signal having a constant margin with respect to the edge of the clock code. Accordingly, the clock window generator including the window signal selector 470 can accurately detect the edge of the clock code even when a delay in clock recovery is large or data is transmitted at high speed.

In one embodiment, the window signal selector 470 adaptively selects the clock window signal CLKWIN during a training period in which the clock training signal is transmitted, and transmits data including a clock code. It can act as a clock error detector that detects transmission errors during the interval. During the data period, the window signal selector 470 receives the transmission signal RX and the first window signal CLKWIN1 or the second window signal CLKWIN2 selected during the training period and transmit a transmission error, for example, a transmission signal. An error in which the clock code is not included in (RX) can be detected. When the clock signal is not included in the transmission signal RX, the reception apparatus including the window signal selection unit 470 of FIG. 17 notifies the transmission apparatus of the transmission error, and the transmission apparatus sends a clock training signal and And / or resend the data.

18A is a timing diagram illustrating an example of an operation of the window signal selector of FIG. 17.

Referring to FIGS. 17 and 18A, the window signal selector 470 may have a logic high level 268 after the delay locked loop circuit 400 of FIG. 10 is locked during the training period, that is, the lock detection signal LDS is locked. Perform an adaptive window selection operation. The clock signal CLK generated by the clock recovery circuit 100 of FIG. 10 is delayed by the recovery delay time TRD than the transmission signal RX. The pulse 267 of the first window signal CLKWIN1 having a rising edge about 1.5 bits long before the rising edge of the clock signal CLK and a falling edge about 0.5 bits long is about 1.5 with respect to the transmission signal RX. It has a margin M1 that limits the recovery delay time TRD in the bit length. At this time, when the margin M1 of the first window signal CLKWIN1 is equal to or longer than a predetermined time, for example, about 0.5 bit in length, the window signal selector 470 is a clock window signal CLKWIN. CLKWIN1) can be selected. Accordingly, during the data period, the edge of the clock code included in the transmission signal RX may be accurately detected by using the pulse 269 of the clock window signal CLKWIN having a predetermined margin M1.

18B is a timing diagram for describing another example of the operation of the window signal selector of FIG. 17.

17 and 18B, the pulse 267 of the first window signal CLKWIN1 has a predetermined margin M1 with respect to the transmission signal RX. At this time, when the margin M1 of the first window signal CLKWIN1 is less than a predetermined time, for example, about 0.5 bit long, the first window signal CLKWIN1 is not suitable for clock code detection. Accordingly, the second window signal CLKWIN2 about 1 bit in length with respect to the first window signal CLKWIN1 may be selected as the clock window signal CLKWIN. The pulse 275 of the second window signal CLKWIN2 may precede the transmission signal RX by a predetermined margin M2, for example, about 0.5 bit or more. Accordingly, during the data period, the edge of the clock code included in the transmission signal RX may be accurately detected by using the pulse 276 of the clock window signal CLKWIN having a predetermined margin M2.

As such, the clock window generator 450 of FIG. 15 according to another embodiment of the present invention adapts the clock window signal CLKWIN having a predetermined margin with respect to the transmission signal RX according to the transmission rate and / or the delay amount. Can be generated as Accordingly, the clock recovery circuit according to another embodiment of the present invention can accurately detect the clock code even at high speed using the adaptively generated clock window signal CLKWIN. In addition, the sampling signal generator according to another embodiment of the invention is suitable for high speed operation.

19 is a diagram illustrating a window signal selector included in a sampling signal generator according to still another embodiment of the present invention.

Referring to FIG. 19, the window signal selector 470 may include a delay circuit 471, a first flip-flop 472, a second flip-flop 473, an XOR gate 474, and a third flip-flop ( 475, counter 476 and comparator 477.

The delay circuit 471 delays the first window signal CLKWIN1 by a desired margin. The first flip-flop 472 outputs a value of the transmission signal RX at the rising edge of the first window signal CLKWIN1 delayed by the delay circuit 471. The second flip-flop 473 outputs a value of the transmission signal RX at the falling edge of the first window signal CLKWIN1 delayed by the delay circuit 471. The XOR gate 474 performs an XOR operation on the output signal of the first flip-flop 472 and the output signal of the second flip-flop 473, so that the first window signal CLKWIN1 delayed by the delay circuit 471. Outputs a signal indicating whether an edge of the clock code included in the transmission signal RX exists between the rising edge and the falling edge.

The third flip-flop 475 latches the output signal of the XOR gate 474 in response to a clock signal, eg, the clock falling signal CFS of FIG. 13. The third flip-flop 475 has a data terminal to which the output signal of the XOR gate 474 is applied, a clock terminal to which the clock signal is applied, an inverting reset terminal to which the lock detection signal LDS is applied, and an output terminal. It may be a rising edge triggered flip-flop. The third flip-flop 475 may perform an operation when the lock detector 420 of FIG. 10 outputs the lock detection signal LDS having a logic high level. In addition, the third flip-flop 475 may be synchronized with the counter 476 and the comparator 477 using the clock signal.

The counter 476 performs a counting operation in response to the output signal of the third flip-flop 475. For example, the counter 476 can include a plurality of flip-flops in series. The comparator 477 compares the counting result of the counter 476 with a predetermined reference value. Accordingly, the counter 476 and the comparator 477 correspond to the output signal of the third flip-flop 475 when the output signal of the third flip-flop 475 maintains a constant value for a predetermined time. The window selection signal WINSEL may be generated. For example, when the output signal of the third flip-flop 475 maintains a logic high level for a predetermined time, the counter 476 and the comparator 477 may use the window selection signal representing the first window signal CLKWIN1. WINSEL) and the output signal of the third flip-flop 475 maintains a logic low level for a predetermined time, the counter 476 and the comparator 477 select a window representing the second window signal CLKWIN2. The signal WINSEL can be output.

In one embodiment, the window signal selector 470 adaptively selects the clock window signal CLKWIN during a training period in which the clock training signal is transmitted, and transmits data including a clock code. It can act as a clock error detector that detects transmission errors during the interval.

As such, the clock window generator 450 of FIG. 19 according to still another exemplary embodiment of the present invention may generate the clock window signal CLKWIN having a predetermined margin with respect to the transmission signal RX according to the transmission rate and / or the delay amount. Can be generated adaptively.

20 is a block diagram illustrating an interface system including a sampling signal generator according to embodiments of the present invention.

Referring to FIG. 20, the interface system 500 includes a transmitter 510, a transmission line 520, and a receiver 530.

The transmitting device 510 transmits clock embedded data to the receiving device 530 through the transmission line 520. The transmitter 510 transmits a clock training signal through the transmission line 520 during the training period and transmits data to which a clock code is added through the transmission line 520 during the data period.

The receiving device 530 includes a sampling signal generator 300 and a sampler 550. The sampling signal generator 300 restores the clock signal CLK from the transmission signal RX transmitted through the transmission line 520, and transmits the data DATA delayed by the recovery delay of the clock signal CLK to the sampler 550. to provide. The sampling signal generator 300 includes a clock recovery circuit 100 for recovering the clock signal CLK from the transmission signal RX based on the clock window signal CLKWIN, and a clock window signal CLKWIN and data for clock recovery. It may include a delay locked loop circuit 400 for generating a sampling signal (SS) for sampling. The sampler 550 may sample and / or parallelize the data DATA provided from the clock recovery circuit 100 in response to the sampling signal SS provided from the delay locked loop circuit 400. The parallel data PD sampled by the sampler 550 and the clock signal CLK / delayed clock signal DCLK recovered by the sampling signal generator 300 are transferred to other components inside or outside the receiving device 530. It can be provided as a data and clock signal.

20 illustrates an example in which the transmitting device 510 and the receiving device 530 are connected through one transmission line 520, but the transmitting device 510 and the receiving device 530 may be connected through two or more transmission lines. In addition, the interface system 500 may be a system using a serial interface. The interface system 500 includes a Low Voltage Differential Signaling (LVDS) interface, a Transition Minimized Differential Signaling (TMDS) interface, a Reduced Swing Differential Signaling (RSDS) interface, a Point-to-Point Differential Signaling (PPDS) interface, serial advanced technology attachment) interface and the like can be employed.

As such, the clock recovery circuit and the sampling signal generator according to embodiments of the present invention can accurately recover the clock signal from the clock embedded data. In addition, the clock recovery circuit and the sampling signal generator according to the embodiments of the present invention can speed up signal transmission by using an adaptively generated clock window signal.

The present invention can be usefully used in any interface device and system. In addition, the present invention is a low voltage differential signaling (LVDS) interface system, a transition minimized differential signaling (TMDS) interface system, a reduced swing differential signaling (RSDS) interface system, a point-to-point differential signaling (PPDS) interface system, SATA (SATA) serial advanced technology attachment).

Although described above with reference to the embodiments of the present invention, those skilled in the art various modifications and changes to the present invention without departing from the spirit and scope of the invention described in the claims below I will understand.

1 is a block diagram illustrating a clock recovery circuit according to an exemplary embodiment of the present invention.

FIG. 2 is a timing diagram for describing an operation of the clock recovery circuit of FIG. 1.

3A is a timing diagram illustrating an example of operations of a clock code detector and a clock signal generator included in the clock recovery circuit of FIG. 1.

3B is a timing diagram illustrating another example of operations of the clock code detector and the clock signal generator included in the clock recovery circuit of FIG. 1.

3C is a timing diagram illustrating another example of operations of a clock code detector and a clock signal generator included in the clock recovery circuit of FIG. 1.

FIG. 3D is a timing diagram illustrating another example of operations of the clock code detector and the clock signal generator included in the clock recovery circuit of FIG. 1.

4 is a block diagram illustrating a clock code detector included in the clock recovery circuit of FIG. 1.

FIG. 5 is a timing diagram for describing an operation of the clock code detector of FIG. 4.

FIG. 6 is a diagram illustrating a clock signal generator included in the clock recovery circuit of FIG. 1.

FIG. 7 is a timing diagram for describing an operation of the clock signal generator of FIG. 6.

8 is a block diagram illustrating a delay circuit included in the clock recovery circuit of FIG. 1.

9 is a diagram illustrating an output unit included in the clock recovery circuit of FIG. 1.

FIG. 10 is a block diagram illustrating a sampling signal generator including the clock recovery circuit of FIG. 1.

FIG. 11 is a diagram illustrating a delay line included in the sampling signal generator of FIG. 10.

FIG. 12 is a diagram illustrating a clock window generator included in the sampling signal generator of FIG. 10.

FIG. 13 is a timing diagram for describing an operation of the delay line of FIG. 11 and the clock window generator of FIG. 12.

14 is a diagram illustrating a clock signal generator included in a clock recovery circuit according to another exemplary embodiment of the present invention.

15 illustrates a clock window generator included in a sampling signal generator according to another embodiment of the present invention.

FIG. 16 is a diagram illustrating a window signal generator included in the clock window generator of FIG. 15.

17 is a diagram illustrating a window signal selector included in the clock window generator of FIG. 15.

18A is a timing diagram illustrating an example of an operation of the window signal selector of FIG. 17.

18B is a timing diagram for describing another example of the operation of the window signal selector of FIG. 17.

19 is a diagram illustrating a window signal selection unit included in a sampling signal generator according to still another embodiment of the present invention.

20 is a block diagram illustrating an interface system including a sampling signal generator according to embodiments of the present invention.

<Description of the symbols for the main parts of the drawings>

100: clock recovery circuit 110: clock code detection unit

111: rising detector 113: falling detector

115: rising-falling determinant 117: selector

130: clock signal generation unit 150: delay circuit

170: output unit 171: clock output unit

173: data output unit 300: sampling signal generator

400: delay locked loop circuit 410: phase frequency detector

420: lock detector 430: control signal generator

441, 442, 443, 444, 445, 446, 447, 448: Delay cell

440: delay line 450: clock window generator

460: window signal generation unit 470: window signal selection unit

Claims (10)

A clock code detector for receiving a transmission signal including a clock code, detecting an edge of the clock code in the transmission signal in response to a clock window signal, and generating a clock transition signal based on the edge of the clock code; And And a clock signal generator configured to generate a restored clock signal in response to the clock transition signal. The method of claim 1, wherein the clock code detector, A rising detector for detecting a rising edge of the clock code in the transmission signal to generate a rising edge detection signal; A falling detector for detecting a falling edge of the clock code in the transmission signal to generate a falling edge detection signal; A rise-fall determiner that determines whether the clock code has a rising edge or a falling edge to generate a rising-falling decision signal; And And a selector for selectively outputting the rising edge detection signal or the falling edge detection signal as the clock transition signal in response to the rising-falling determination signal. The method of claim 2, The rising detector includes a first latch for outputting the clock window signal as the rising edge detection signal when the clock window signal has a logic high level and the transmission signal has a logic high level, The falling detector includes a second latch for outputting the clock window signal as the falling edge detection signal when the clock window signal has a logic high level and the transmission signal has a logic low level, The rising-falling determiner includes a flip-flop that outputs the transmission signal as the rising-falling determination signal in response to the rising edge of the clock window signal, The selector includes a multiplexer that receives the rising-falling determination signal as a selection signal and selectively outputs the rising edge detection signal or the falling edge detection signal as the clock transition signal in response to the rising-falling determination signal. Clock recovery circuit, characterized in that. The method of claim 1, wherein the clock generation unit, And generating the reconstructed clock signal that rises in response to the clock transition signal and falls in response to the delayed clock transition signal that delayed the clock transition signal. The method of claim 1, wherein the clock generation unit, And generating a recovery clock signal that rises in response to the clock transition signal and falls in response to a clock falling signal received from a delay locked loop circuit. The method of claim 1, And a delay unit configured to delay the transmission signal by a delay time of the clock code detector and the clock signal generator. The method of claim 6, A clock output unit for selectively outputting the recovery clock signal output from the clock signal generation unit or the transmission signal output from the delay unit in response to the lock detection signal; And And a data output unit for selectively outputting the transmission signal output from the delay circuit in response to the lock detection signal. A clock recovery circuit for receiving a transmission signal comprising a clock code, detecting an edge of the clock code in the transmission signal in response to a clock window signal, and generating a clock signal based on the edge of the clock code; And A sampling signal comprising a delay locked loop circuit for generating a multi-phase clock signal based on the clock signal, generating the clock window signal based on the multi-phase clock signal, and outputting the multi-phase clock signal as a sampling signal. Genitals. The method of claim 8, wherein the delay lock loop circuit, A delay line including a plurality of delay cells for sequentially delaying the clock signal to generate the multi-phase clock signal, and generating a delayed clock signal delayed by the clock signal; A phase frequency detector for generating an up signal and a down signal based on a phase difference between the clock signal and the delayed clock signal; A control signal generator configured to generate a delay control signal for adjusting a delay time of the delay line in response to the up signal and the down signal; A lock detector for generating a lock detection signal in response to the up signal and the down signal; And And a clock window generator for performing a logic operation on the multi-phase clock signal to generate the clock window signal. The method of claim 9, wherein the clock window generator, A first window signal is generated by performing a logic operation on two clock signals among the multi-phase clock signals, and a second window signal is generated by performing a logical operation on two clock signals adjacent to the two clock signals. A window signal generator configured to selectively generate the first window signal or the second window signal in response to a window selection signal; And And a window signal selector which detects an interval between the first window signal and an edge of the clock code and generates the window selection signal based on the detected interval.

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