KR101614109B1 - Semiconductor package and manufacturing method thereof - Google Patents

Semiconductor package and manufacturing method thereof Download PDF

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KR101614109B1
KR101614109B1 KR1020130124831A KR20130124831A KR101614109B1 KR 101614109 B1 KR101614109 B1 KR 101614109B1 KR 1020130124831 A KR1020130124831 A KR 1020130124831A KR 20130124831 A KR20130124831 A KR 20130124831A KR 101614109 B1 KR101614109 B1 KR 101614109B1
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semiconductor
interposer
substrate
terminals
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KR20150045562A (en
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도원철
박진희
이지훈
박은호
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앰코 테크놀로지 코리아 주식회사
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Abstract

본 발명의 반도체 패키지는, 기판과, 상기 기판 상에 형성되며, 서로 이격된 복수의 세그먼트를 포함하는 확장용 기판과, 상기 복수의 세그먼트 중 적어도 두 세그먼트 상에 걸쳐 형성되는 적어도 하나의 반체 다이를 포함할 수 있다.A semiconductor package of the present invention includes a substrate, an extension substrate formed on the substrate and including a plurality of segments spaced apart from each other, at least one half die formed over at least two segments of the plurality of segments, .

Description

반도체 패키지 및 그 제작 방법{SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF}TECHNICAL FIELD [0001] The present invention relates to a semiconductor package,

본 발명은 반도체 패키지에 관한 것으로, 더욱 상세하게는 인터포저 등과 같은 확장용 기판 상에 복수의 반도체 다이가 부착되는 적층 구조를 갖는 반도체 패키지 및 그 제작 방법에 관한 것이다.
The present invention relates to a semiconductor package, and more particularly, to a semiconductor package having a stacked structure in which a plurality of semiconductor dies are attached on an extension substrate such as an interposer and a method of manufacturing the same.

최근 들어, 스마트폰, 스마트 패드 등과 같은 휴대형 전자기기의 시장이 폭발적으로 성장해 가면서 경박단소 제품에 대응할 수 있는 반도체 패키지의 수요가 점진적으로 증가하고 있으며, 또한 고기능화로 인해 반도체 소자의 입출력 단자수가 점진적으로 증가하는 추세이다.Recently, as the market of portable electronic devices such as smart phones and smart pads has been exploding, demand for semiconductor packages capable of responding to light and small size products has been gradually increasing. In addition, due to high functionality, the number of input / .

따라서, 경박단소화 및 고기능화에 대응하기 위한 반도체 패키지의 하나로서 적층형 패키지(패키지 온 패키지 : PoP)가 활용되고 있는데, 이러한 적층형 패키지에서는 하부 기판과 반도체 소자 사이에 인터포저 등과 같은 확장용 기판이 삽입되어 사용되고 있으며, 이러한 인터포저 상에는 복수의 반도체 소자(예컨대, 로직 소자, 메모리 소자 등)가 동일 평면상에 부착(형성)될 수 있다.Accordingly, a stacked package (package on package: PoP) is used as one of the semiconductor packages to cope with thinning and high functionality. In such a stacked package, an expansion board such as an interposer is inserted between the lower substrate and the semiconductor element And a plurality of semiconductor elements (for example, logic elements, memory elements, etc.) can be attached (formed) on the same plane on the interposer.

여기에서, 하부 기판과 인터포저는 솔더볼 등과 같은 도전성 범프를 통해 물리적으로 부착되고, 인터포저와 반도체 소자는 솔더 페이스트 등과 같은 도전성 부재를 통해 물리적으로 부착될 수 있다.Here, the lower substrate and the interposer are physically attached through a conductive bump such as a solder ball, and the interposer and the semiconductor element can be physically attached through a conductive member such as a solder paste or the like.

한편, 인터포저 상에 복수의 반도체 소자를 부착한다는 것은 인터포저의 크기가 그만큼 증가하게 되는 문제로 귀결되며, 이러한 문제는 인터포저 칩을 제작할 때 핸들링을 어렵게 하는 문제와 웨이퍼의 손실률을 증가시키는 문제를 유발시킨다.On the other hand, attaching a plurality of semiconductor elements on the interposer results in a problem that the size of the interposer is increased correspondingly. Such a problem is a problem of making the interposer chip difficult to handle and a problem of increasing the loss rate of the wafer ≪ / RTI >

즉, 인터포저 칩의 크기가 커질수록 깨짐 등의 손상 가능성이 증가하게 되고, 결함에 대한 민감도도 증가, 예컨대 하나의 웨이퍼에서 제작한 인터포저 칩 중 2개가 결함이라고 가정할 때, 총 10개의 인터포저 칩을 제작 가능한 경우와 30개의 인터포저 칩을 제작 가능한 경우의 결함율은 현저한 차이를 갖게 되는데, 이러한 이유로 인해 인터포저 칩의 크기가 커질수록 결함 민감도가 증가하게 되는 문제가 있다.That is, as the size of the interposer chip increases, the possibility of damage such as breakage increases, and sensitivity to defects increases. For example, assuming that two of the interposer chips fabricated in one wafer are defective, There is a significant difference between the case where the through chip chip can be manufactured and the case where the 30 interposer chips can be manufactured. For this reason, there is a problem that the defect sensitivity increases as the size of the interposer chip becomes larger.

또한, 종래의 인터포저는 탑재되는 복수의 반도체 소자들 중 어느 하나의 반도체 소자가 상대적으로 많은 수의 I/O 단자를 필요로 하는 고기능성 소자인 경우, 인터포저 자체를 상대적으로 많은 수의 관통 실리콘 비아 및 I/O 단자를 갖는 고기능성 칩으로 제작해야만 하는 문제가 있다.
Also, in the conventional interposer, when one of the plurality of semiconductor elements to be mounted is a high-function element requiring a relatively large number of I / O terminals, the interposer itself can be penetrated through a relatively large number There is a problem that a high-performance chip having a silicon via and an I / O terminal must be manufactured.

대한민국 공개특허 제2012-0095157호(공개일 : 2012. 08. 28.)Korean Patent Publication No. 2012-0095157 (Published on Aug. 28, 2012)

본 발명은, 복수의 반도체 소자가 탑재되는 인터포저를 서로 이격된 복수의 세그먼트 형태로 제작함으로써, 인터포저 제작을 위한 핸들링이 용이하면서도 제작시의 결함 민감도를 저감시킬 수 있는 새로운 반도체 패키지 및 그 제법을 제안한다.The present invention relates to a new semiconductor package which can easily handle for manufacturing an interposer and can reduce defect sensitivity at the time of fabrication by manufacturing the interposer in which a plurality of semiconductor elements are mounted in the form of a plurality of segments spaced apart from each other, .

또한, 본 발명은 복수의 반도체 소자가 탑재되는 인터포저를 서로 이격된 복수의 세그먼트 형태로 제작하여 부분적인 고기능화를 실현함으로써, 인터포저의 제작 용이성 및 제작비용을 절감할 수 있는 새로운 반도체 패키지 및 그 제법을 제안한다.The present invention also provides a new semiconductor package and a method for fabricating the same, which can reduce the fabrication easiness and production cost of the interposer by realizing the partial functioning by manufacturing the interposer in which a plurality of semiconductor elements are mounted in the form of a plurality of segments spaced apart from each other, Suggest the recipe.

본 발명이 해결하고자 하는 과제는 상기에서 언급한 것으로 제한되지 않으며, 언급되지 않은 또 다른 해결하고자 하는 과제는 아래의 기재로부터 본 발명이 속하는 통상의 지식을 가진 자에 의해 명확하게 이해될 수 있을 것이다.
The problems to be solved by the present invention are not limited to those mentioned above, and another problem to be solved not mentioned can be clearly understood by those skilled in the art from the following description .

본 발명은, 일 관점에 따라, 기판과, 상기 기판 상에 형성되며, 서로 이격된 복수의 세그먼트를 포함하는 확장용 기판과, 상기 복수의 세그먼트 중 적어도 두 세그먼트 상에 걸쳐 형성되는 적어도 하나의 반도체 다이를 포함하는 반도체 패키지를 제공한다.According to an aspect of the present invention, there is provided a semiconductor device comprising a substrate, an extension substrate formed on the substrate and including a plurality of segments spaced apart from each other, and at least one semiconductor formed over at least two segments of the plurality of segments, A semiconductor package including a die is provided.

본 발명의 상기 확장용 기판은, 복수의 관통 실리콘 비아가 형성된 분리형 인터포저일 수 있다.The extension substrate of the present invention may be a removable interposer in which a plurality of through silicon vias are formed.

본 발명의 상기 분리형 인터포저는, 적어도 하나의 고기능성 세그먼트와 적어도 하나의 저기능성 세그먼트를 포함할 수 있다.The discrete interposer of the present invention may comprise at least one high functionality segment and at least one low functionality segment.

본 발명의 상기 분리형 인터포저는, 실리콘 재질, 글라스 재질, PCB 타입의 오거닉 재질 중 어느 하나일 수 있다.The separable interposer of the present invention may be any one of silicon material, glass material, and PCB type organic material.

본 발명의 상기 반도체 패키지는, 상기 확장용 기판과 반도체 다이를 매립하는 몰드 부재를 더 포함할 수 있다.The semiconductor package of the present invention may further include a mold member for burying the extension substrate and the semiconductor die.

본 발명은, 다른 관점에 따라, 기판을 준비하는 과정과, 서로 이격된 복수의 세그먼트를 포함하는 확장용 기판을 상기 기판 상에 부착하는 과정과, 상기 복수의 세그먼트 중 적어도 두 세그먼트 상에 걸쳐지는 형태로 적어도 하나의 반도체 다이를 부착하는 과정을 포함하는 반도체 패키지 제작 방법을 제공한다.According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of preparing a substrate, attaching an extension substrate including a plurality of segments spaced apart from each other on the substrate, And attaching at least one semiconductor die in the form of a semiconductor die.

본 발명의 상기 분리형 인터포저는, 도전성 범프를 통해 상기 기판 상에 부착될 수 있다.The detachable interposer of the present invention can be attached to the substrate through a conductive bump.

본 발명의 상기 도전성 범프는, 솔더 볼 또는 표면에 솔더가 코팅된 구리 볼일 수 있다.The conductive bump of the present invention may be a solder ball or a copper ball whose surface is coated with solder.

본 발명의 상기 제작 방법은, 상기 확장용 기판과 반도체 다이를 몰드 부재로 매립하는 과정을 더 포함할 수 있다.
The manufacturing method of the present invention may further include a step of embedding the extension substrate and the semiconductor die with a mold member.

본 발명은, 서로 이격된 복수의 세그먼트 형태로 인터포저를 제작함으로써, 인터포저 제작을 위한 핸들링이 용이하면서도 제작시의 결함 민감도를 저감시킬 수 있다.By manufacturing the interposer in the form of a plurality of segments spaced apart from each other, it is possible to easily handle for manufacturing the interposer, and to reduce the sensitivity of the defect at the time of manufacture.

또한, 본 발명은 서로 이격된 복수의 세그먼트 형태로 인터포저를 제작하여 부분적인 고기능화를 실현함으로써, 인터포저의 제작 용이성 및 제작비용을 절감할 수 있다.
Further, according to the present invention, the interposer is manufactured in the form of a plurality of segments spaced apart from each other to partially achieve high functionality, thereby making it possible to reduce fabrication easiness and manufacturing cost of the interposer.

도 1은 본 발명의 실시 예에 따른 반도체 패키지의 단면도이다.
도 2 내지 도 7은 본 발명의 다양한 실시 예에 따라 인터포저를 복수의 세그먼트 형태로 형성하는 예들을 각각 보여주는 각 평면 예시도이다.
도 8a 내지 8c는 본 발명의 실시 예에 따라 반도체 패키지를 제작하는 주요 과정을 도시한 공정 순서도이다.1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.
FIGS. 2-7 are plan-view illustrations, each showing an example of forming the interposer in a plurality of segments in accordance with various embodiments of the present invention.
8A to 8C are process flow diagrams illustrating a main process of fabricating a semiconductor package according to an embodiment of the present invention.

먼저, 본 발명의 장점 및 특징, 그리고 그것들을 달성하는 방법은 첨부되는 도면과 함께 상세하게 후술되는 실시 예들을 참조하면 명확해질 것이다. 여기에서, 본 발명은 이하에서 개시되는 실시 예들에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시 예들은 본 발명의 개시가 완전하도록 하고, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 발명의 범주를 명확하게 이해할 수 있도록 하기 위해 예시적으로 제공되는 것이므로, 본 발명의 기술적 범위는 청구항들에 의해 정의되어야 할 것이다.First, the advantages and features of the present invention, and how to accomplish them, will be clarified with reference to the embodiments to be described in detail with reference to the accompanying drawings. While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

아울러, 아래의 본 발명을 설명함에 있어서 공지 기능 또는 구성 등에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략할 것이다. 그리고, 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들인 것으로, 이는 사용자, 운용자 등의 의도 또는 관례 등에 따라 달라질 수 있음은 물론이다. 그러므로, 그 정의는 본 명세서의 전반에 걸쳐 기술되는 기술사상을 토대로 이루어져야 할 것이다.In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. It is to be understood that the following terms are defined in consideration of the functions of the present invention, and may be changed according to intentions or customs of a user, an operator, and the like. Therefore, the definition should be based on the technical idea described throughout this specification.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예에 대하여 상세하게 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명의 실시 예에 따른 반도체 패키지의 단면도로서, 본 발명의 반도체 패키지는 기판(102) 상에 복수의 세그먼트(106a, 106b)로 된 분리형 인터포저(106)가 부착(형성)되고, 분리형 인터포저(106)의 상부에 두 개의 반도체 다이(110, 112)가 부착(형성)되는 구조를 가질 수 있다. 여기에서, 분리형 인터포저(106)는 확장용 기판으로 통칭(정의)될 수 있다.1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. In the semiconductor package of the present invention, a detachable interposer 106 of a plurality of segments 106a and 106b is attached (formed) on a substrate 102 , And two semiconductor dies 110 and 112 are attached (formed) on the upper portion of the detachable interposer 106. Here, the detachable interposer 106 can be defined (defined) as a substrate for extension.

도 1을 참조하면, 분리형 인터포저(106)는 도전성 범프(104)를 통해 기판(102) 상에 부착(전기적인 접속)될 수 있는데, 이러한 도전성 범프(104)로서는, 예컨대 솔더 볼 또는 표면에 솔더가 코팅된 구리 볼 등이 사용될 수 있다. 여기에서, 각 도전성 범프는 대응하는 각 관통 실리콘 비아(TSV)(108)와 물리적으로 연결된다.1, a removable interposer 106 may be attached (electrically connected) to a substrate 102 via a conductive bump 104, such as a solder ball or surface A solder-coated copper ball, or the like may be used. Here, each conductive bump is physically connected to a respective respective through silicon via (TSV) 108.

또한, 분리형 인터포저(106)를 구성하는 세그먼트(106a)는 저기능성 세그먼트일 수 있고, 다른 하나의 세그먼트(106b)는 고기능성 세그먼트일 수 있는데, 고기능성 세그먼트라 함은 상대적으로 많은 수의 I/O 단자를 필요로 하는 고기능성 반도체 소자에 대응할 수 있도록 상대적으로 많은 수의 관통 실리콘 비아(TSV)와 I/O 단자가 형성되는 세그먼트를 의미하고, 저기능성 세그먼트라 함은 상대적으로 작은 수의 I/O 단자를 필요로 하는 저기능성 반도체 소자에 대응할 수 있도록 상대적으로 작은 수의 관통 실리콘 비아(TSV)와 I/O 단자가 형성되는 세그먼트를 의미할 수 있다.Further, the segment 106a constituting the detachable interposer 106 may be a low functionality segment and the other segment 106b may be a high functionality segment, which is a relatively large number of I Refers to a segment in which a relatively large number of through silicon vias (TSV) and I / O terminals are formed so as to correspond to a high functionality semiconductor device requiring a / O terminal, and a low functionality segment means a relatively small number A relatively small number of through silicon vias (TSV) and I / O terminals may be formed to correspond to a low-function semiconductor device requiring an I / O terminal.

즉, 반도체 다이(110)는 저기능성 반도체 소자일 수 있고, 다른 반도체 다이(112)는 고기능성 반도체 소자일 수 있다.That is, the semiconductor die 110 may be a low functionality semiconductor device and the other semiconductor die 112 may be a high functionality semiconductor device.

그리고, 분리형 인터포저(106)는, 예컨대 실리콘 재질, 글라스 재질, PCB 타입의 오거닉 재질 중 어느 하나일 수 있다.The separable interposer 106 may be any one of a silicon material, a glass material, and an organic material of a PCB type, for example.

한편, 도면에서의 도시는 생략되었으나, 본 발명의 반도체 패키지는 반도체 다이(110, 112), 분리형 인터포저(106) 및 도전성 범프(104)를 매립(몰딩)하는 몰드 부재를 더 포함할 수 있다.Although not shown in the drawings, the semiconductor package of the present invention may further include a mold member for embedding (molding) the semiconductor die 110, 112, the detachable interposer 106, and the conductive bump 104 .

도 2 내지 도 7은 본 발명의 다양한 실시 예에 따라 인터포저를 복수의 세그먼트 형태로 형성하는 예들을 각각 보여주는 각 평면 예시도이다.FIGS. 2-7 are plan-view illustrations, each showing an example of forming the interposer in a plurality of segments in accordance with various embodiments of the present invention.

도 2를 참조하면, 2개의 세그먼트(202a, 202b)로 형성되는 분리형 인터포저와 이 분리형 인터포저 상에 3개의 반도체 다이(204a, 204b, 204c)가 적층되는 예시를 보여주는데, 하나의 반도체 다이(204a)가 두 세그먼트(202a, 202b)에 걸쳐서 적층(부착)되고, 나머지 2개의 반도체 다이(204b, 204c)가 하나의 세그먼트(202b) 상에 적층(부착)되는 형태임을 보여준다.Referring to Figure 2, there is shown an example in which three semiconductor dies 204a, 204b, 204c are stacked on a separate interposer formed by two segments 202a, 202b and on a separate interposer, 204a are stacked (attached) over the two segments 202a, 202b and the remaining two semiconductor dies 204b, 204c are stacked (attached) on one segment 202b.

여기에서, 하나의 반도체 다이(204a)가 고기능성 반도체 소자이고, 두 반도체 다이(204b, 204c)가 저기능성 반도체 소자인 것으로 가정할 때, 하나의 세그먼트(202a)는 고기능성 세그먼트이고 다른 하나의 세그먼트(202b)는 저기능성 세그먼트일 수 있다.Herein, assuming that one semiconductor die 204a is a high functionality semiconductor element and two semiconductor dies 204b and 204c are low functionality semiconductor elements, one segment 202a is a high functionality segment and the other Segment 202b may be a low functionality segment.

도 3을 참조하면, 2개의 세그먼트(302a, 302b)로 형성되는 분리형 인터포저와 이 분리형 인터포저 상에 5개의 반도체 다이(304a, 304b, 304c, 304d, 304e)가 적층되는 예시를 보여주는데, 하나의 반도체 다이(304c)가 두 세그먼트(302a, 302b)에 걸쳐서 적층(부착)되고, 2개의 반도체 다이(304a, 304b)가 하나의 세그먼트(302a) 상에 적층(부착)되며, 다른 2개의 반도체 다이(304d, 304e)가 다른 세그먼트(302b) 상에 적층(부착)되는 형태임을 보여준다.Referring to Figure 3, there is shown an example in which five semiconductor die 304a, 304b, 304c, 304d, 304e are stacked on a separate interposer formed by two segments 302a, 302b and on a separate interposer, The semiconductor die 304c is stacked (attached) over the two segments 302a and 302b and the two semiconductor dies 304a and 304b are stacked (attached) on one segment 302a, And that the dies 304d and 304e are laminated (attached) on the other segment 302b.

여기에서, 두 반도체 다이(304a, 304b)가 고기능성 반도체 소자이고, 나머지 반도체 다이(304c, 304d, 304e)가 저기능성 반도체 소자인 것으로 가정할 때, 하나의 세그먼트(302a)는 고기능성 세그먼트이고 다른 하나의 세그먼트(302b)는 저기능성 세그먼트일 수 있다.Here, assuming that the two semiconductor dies 304a, 304b are high functionality semiconductor devices and the remaining semiconductor dies 304c, 304d, 304e are low functionality semiconductor devices, one segment 302a is a high functionality segment The other segment 302b may be a low functionality segment.

도 4를 참조하면, 2개의 세그먼트(402a, 402b)로 형성되는 분리형 인터포저와 이 분리형 인터포저 상에 5개의 반도체 다이(404a, 404b, 404c, 404d, 404e)가 적층되는 예시를 보여주는데, 하나의 반도체 다이(404c)가 두 세그먼트(402a, 402b)에 걸쳐서 적층(부착)되고, 2개의 반도체 다이(404a, 404b)가 하나의 세그먼트(402a) 상에 적층(부착)되며, 다른 2개의 반도체 다이(404d, 404e)가 다른 세그먼트(402b) 상에 적층(부착)되는 형태임을 보여준다.Referring to Figure 4, there is shown an example in which five separate semiconductor die 404a, 404b, 404c, 404d, 404e are stacked on a separate interposer formed by two segments 402a, 402b, Two semiconductor dies 404a and 404b are stacked (attached) on one segment 402a, and two semiconductor dies 404a and 404b are stacked (attached) on two segments 402a and 402b, And the dies 404d and 404e are stacked (attached) on the other segment 402b.

여기에서, 두 반도체 다이(404a, 404b)가 고기능성 반도체 소자이고, 나머지 반도체 다이(404c, 404d, 404e)가 저기능성 반도체 소자인 것으로 가정할 때, 하나의 세그먼트(402a)는 고기능성 세그먼트이고 다른 하나의 세그먼트(402b)는 저기능성 세그먼트일 수 있다.Here, assuming that the two semiconductor dies 404a and 404b are high functionality semiconductor elements and the remaining semiconductor dies 404c, 404d and 404e are low functionality semiconductor elements, one segment 402a is a high functionality segment The other segment 402b may be a low functionality segment.

도 5를 참조하면, 3개의 세그먼트(502a, 502b, 502c)로 형성되는 분리형 인터포저와 이 분리형 인터포저 상에 5개의 반도체 다이(504a, 504b, 504c, 504d, 504e)가 적층되는 예시를 보여주는데, 하나의 반도체 다이(504c)가 세 개의 세그먼트(502a, 502b, 502c)에 걸쳐서 적층(부착)되고, 2개의 반도체 다이(504a, 504b)가 하나의 세그먼트(502a) 상에 적층(부착)되며, 다른 2개의 반도체 다이(504d, 504e)가 다른 세그먼트(502c) 상에 적층(부착)되는 형태임을 보여준다.5, there is shown an example in which five separate semiconductor die 504a, 504b, 504c, 504d, 504e are stacked on a separate interposer formed by three segments 502a, 502b, 502c , One semiconductor die 504c is stacked (attached) over three segments 502a, 502b and 502c and two semiconductor dies 504a and 504b are stacked (attached) on one segment 502a , And the other two semiconductor dies 504d and 504e are stacked (attached) on the other segment 502c.

여기에서, 두 반도체 다이(504a, 504b)가 고기능성 반도체 소자이고, 나머지 반도체 다이(504c, 504d, 504e)가 저기능성 반도체 소자인 것으로 가정할 때, 하나의 세그먼트(502a)는 고기능성 세그먼트이고 나머지 2개의 세그먼트(502b, 502c)는 저기능성 세그먼트일 수 있다.Here, assuming that the two semiconductor dies 504a and 504b are high functionality semiconductor elements and the remaining semiconductor dies 504c, 504d and 504e are low functionality semiconductor elements, one segment 502a is a high functionality segment The remaining two segments 502b, 502c may be low functionality segments.

도 6을 참조하면, 3개의 세그먼트(602a, 602b, 602c)로 형성되는 분리형 인터포저와 이 분리형 인터포저 상에 4개의 반도체 다이(604a, 604b, 604c, 604d)가 적층되는 예시를 보여주는데, 반도체 다이(604b)가 두 세그먼트(602a, 602b)에 걸쳐서 적층(부착)되고, 반도체 다이(604c)가 두 세그먼트(602b, 602c)에 걸쳐서 적층(부착)되며, 반도체 다이(604a)가 세그먼트(602a) 상에 적층(부착)되고, 반도체 다이(604d)가 세그먼트(602c) 상에 적층(부착)되는 형태임을 보여준다.6, there is shown an example in which four semiconductor dies 604a, 604b, 604c, and 604d are stacked on a separate interposer formed by three segments 602a, 602b, and 602c and a separate interposer, The semiconductor die 604c is stacked over the two segments 602b and 602c and the semiconductor die 604a is stacked over the segments 602a and 602b, , And a semiconductor die 604d is stacked (attached) on the segment 602c.

여기에서, 두 반도체 다이(604a, 604d)가 고기능성 반도체 소자이고, 나머지 두 반도체 다이(604b, 604c)가 저기능성 반도체 소자인 것으로 가정할 때, 두 세그먼트(602a, 602c)는 고기능성 세그먼트이고 나머지 하나의 세그먼트(602b)는 저기능성 세그먼트일 수 있다.Here, assuming that the two semiconductor dies 604a and 604d are high functionality semiconductor devices and the remaining two semiconductor dies 604b and 604c are low functionality semiconductor devices, the two segments 602a and 602c are high functionality segments The remaining one segment 602b may be a low functionality segment.

도 7을 참조하면, 4개의 세그먼트(702a, 702b, 702c, 702d)로 형성되는 분리형 인터포저와 이 분리형 인터포저 상에 4개의 반도체 다이(704a, 704b, 704c, 704d)가 적층되는 예시를 보여주는데, 2개의 반도체 다이(704a, 704b)가 두 세그먼트(702a, 702b)에 걸쳐서 적층(부착)되고, 나머지 2개의 반도체 다이(704c, 704d)가 두 세그먼트(702c, 702d)에 걸쳐서 적층(부착)되는 형태임을 보여준다.Referring to FIG. 7, there is shown an example in which four semiconductor die 704a, 704b, 704c, 704d are stacked on a separate interposer formed by four segments 702a, 702b, 702c, 702d and a separate interposer The two semiconductor dies 704a and 704b are stacked over the two segments 702a and 702b and the remaining two semiconductor dies 704c and 704d are stacked over the two segments 702c and 702d, .

도 8a 내지 8c는 본 발명의 실시 예에 따라 반도체 패키지를 제작하는 주요 과정을 도시한 공정 순서도이다.8A to 8C are process flow diagrams illustrating a main process of fabricating a semiconductor package according to an embodiment of the present invention.

도 8a를 참조하면, 확장용 기판으로서 기능하는 분리형 인터포저와 반도체 다이들을 적층할 기판(102)을 준비한다.Referring to FIG. 8A, a substrate 102 to be stacked with a semiconductor die and a detachable interposer serving as an extension substrate is prepared.

이어서, 도전성 범프(104), 예컨대 솔더 볼 또는 표면에 솔더가 코팅되는 구리 볼 등과 같은 도전성 범프를 이용하는 적층 공정(부착 공정)을 진행함으로써, 일례로서 도 8b에 도시된 바와 같이, 기판(102) 상에 두 세그먼트(106a, 106b)로 된 분리형 인터포저(106)를 부착(형성)한다.Subsequently, by performing a lamination process (adhesion process) using conductive bumps 104, for example, conductive bumps such as solder balls or copper balls coated with solder on the surface thereof, as shown in Fig. 8B as an example, (Form) a separate interposer 106 of two segments 106a, 106b.

예컨대, 기판(102) 상의 목표 위치에 도전성 범프(104)들을 올리고, 각 세그먼트(106a, 106b)를 목표 위치에 정렬시킨 후 리플로우 공정 등을 진행함으로써, 기판(102) 상에 분리형 인터포저(106)를 부착한다. 여기에서, 세그먼트(106a)는 저기능성 세그먼트이고 다른 하나의 세그먼트(106b)는 고기능성 세그먼트일 수 있으며, 각 세그먼트(106a, 106b)에는 복수의 관통 실리콘 비아(TSV)와 I/O 단자들이 형성되어 있다.For example, by placing the conductive bumps 104 on a target position on the substrate 102, arranging the segments 106a and 106b at a target position, and performing a reflow process or the like, 106). Here, the segment 106a may be a low functionality segment and the other segment 106b may be a high functionality segment, with each of the segments 106a and 106b having a plurality of through silicon vias TSV and I / O terminals formed .

다시, 도전성 범프를 이용하는 적층 공정(부착 공정)을 진행함으로써, 일례로서 도 8c에 도시된 바와 같이, 분리형 인터포저(106) 상에 반도체 다이들(110, 112)을 부착(형성)시킨다. 여기에서, 반도체 다이(110)는 저기능성 반도체 소자이고 다른 하나의 반도체 다이(112)는 고기능성 반도체 소자일 수 있다.The semiconductor die 110 (or 112) is attached (formed) on the detachable interposer 106, as shown in Fig. 8C as an example, by performing a lamination process (attachment process) using conductive bumps. Here, the semiconductor die 110 may be a low functionality semiconductor device and the other semiconductor die 112 may be a high functionality semiconductor device.

한편, 도면에서의 도시는 생략되었으나, 몰딩 공정 등을 진행함으로써, 기판(120) 상에 적층된 분리형 인터포저(106)와 각 반도체 다이(110, 112)를 몰드 부재로 매립시킬 수 있다.Although not shown in the drawings, the separable interposer 106 and the semiconductor dies 110 and 112 stacked on the substrate 120 and the semiconductor dies 110 and 112 can be filled with a mold member by performing a molding process or the like.

이상의 설명은 본 발명의 기술사상을 예시적으로 설명한 것에 불과한 것으로서, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자라면 본 발명의 본질적인 특성에서 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경 등이 가능함을 쉽게 알 수 있을 것이다. 즉, 본 발명에 개시된 실시 예들은 본 발명의 기술 사상을 한정하기 위한 것이 아니라 설명하기 위한 것으로서, 이러한 실시 예에 의하여 본 발명의 기술 사상의 범위가 한정되는 것은 아니다.It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. It is easy to see that this is possible. That is, the embodiments disclosed in the present invention are not intended to limit the scope of the present invention but to limit the scope of the present invention.

따라서, 본 발명의 보호 범위는 후술되는 청구범위에 의하여 해석되어야 하며, 그와 동등한 범위 내에 있는 모든 기술사상은 본 발명의 권리범위에 포함되는 것으로 해석되어야 할 것이다.
Therefore, the scope of protection of the present invention should be construed in accordance with the following claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

102 : 기판 104 : 도전성 범프
106 : 분리형 인터포저 108 : 관통 실리콘 비아
110, 112 : 반도체 다이102: substrate 104: conductive bump
106: detachable interposer 108: penetrating silicon vias
110, 112: semiconductor die

Claims (11)

기판과,
도전성 범프를 통해 상기 기판상에 전기적 접속 형태로 형성되며, 서로 이격된 복수의 세그먼트를 포함하는 확장용 기판과,
상기 복수의 세그먼트 중 적어도 두 세그먼트 상에 걸쳐 전기적 접속으로 형성되는 적어도 하나의 반도체 다이와,
상기 두 세그먼트 중 어느 한 세그먼트에 전기적 접속으로 형성되는 적어도 하나의 다른 반도체 다이
를 포함하고,
상기 두 세그먼트 중 하나는,
상대적으로 많은 수의 I/O 단자를 필요로 하는 고기능성 반도체 소자에 대응할 수 있도록 상대적으로 많은 수의 관통 실리콘 비아(TSV)와 I/O 단자가 형성되는 고기능성 세그먼트이고,
상기 두 세그먼트 중 다른 하나는,
상대적으로 작은 수의 I/O 단자를 필요로 하는 저기능성 반도체 소자에 대응할 수 있도록 상대적으로 작은 수의 관통 실리콘 비아(TSV)와 I/O 단자가 형성되는 저기능성 세그먼트인
반도체 패키지.
A substrate;
An expansion board formed in electrical connection on the substrate through conductive bumps and including a plurality of segments spaced apart from each other;
At least one semiconductor die formed in electrical connection over at least two of the plurality of segments,
At least one other semiconductor die formed in electrical connection to any one of the two segments
Lt; / RTI >
Wherein one of the two segments comprises:
Functional segments in which a relatively large number of through silicon vias (TSV) and I / O terminals are formed to cope with a high-functional semiconductor device requiring a relatively large number of I / O terminals,
Wherein the other of the two segments comprises:
Functional segments in which a relatively small number of through silicon vias (TSV) and I / O terminals are formed so as to correspond to a low-function semiconductor device requiring a relatively small number of I / O terminals
Semiconductor package.
제 1 항에 있어서,
상기 확장용 기판은,
복수의 관통 실리콘 비아가 형성된 분리형 인터포저인
반도체 패키지.
The method according to claim 1,
Wherein the extension substrate comprises:
A separable interposer in which a plurality of through silicon vias are formed
Semiconductor package.
삭제delete 제 2 항에 있어서,
상기 분리형 인터포저는,
실리콘 재질, 글라스 재질, PCB 타입의 오거닉 재질 중 어느 하나인
반도체 패키지.
3. The method of claim 2,
Wherein the removable interposer comprises:
One of silicon material, glass material, PCB type of organic material
Semiconductor package.
제 1 항에 있어서,
상기 반도체 패키지는,
상기 확장용 기판과 반도체 다이를 매립하는 몰드 부재
를 더 포함하는 반도체 패키지.
The method according to claim 1,
The semiconductor package includes:
A mold member for embedding the extension substrate and the semiconductor die;
Further comprising:
기판을 준비하는 과정과,
서로 이격된 복수의 세그먼트를 포함하는 확장용 기판을 도전성 범프를 통해 상기 기판상에 전기적 접속 형태로 부착하는 과정과,
상기 복수의 세그먼트 중 적어도 두 세그먼트 상에 걸쳐져 전기적 접속 형태로 적어도 하나의 반도체 다이를 부착하는 과정과,
상기 두 세그먼트 중 어느 한 세그먼트에 전기적 접속 형태로 적어도 하나의 다른 반도체 다이를 부착하는 단계
을 포함하고,
상기 두 세그먼트 중 하나는,
상대적으로 많은 수의 I/O 단자를 필요로 하는 고기능성 반도체 소자에 대응할 수 있도록 상대적으로 많은 수의 관통 실리콘 비아(TSV)와 I/O 단자가 형성되는 고기능성 세그먼트이고,
상기 두 세그먼트 중 다른 하나는,
상대적으로 작은 수의 I/O 단자를 필요로 하는 저기능성 반도체 소자에 대응할 수 있도록 상대적으로 작은 수의 관통 실리콘 비아(TSV)와 I/O 단자가 형성되는 저기능성 세그먼트인
반도체 패키지 제작 방법.
Preparing a substrate;
Attaching an extension substrate including a plurality of segments spaced apart from each other in an electrically connected form to the substrate through a conductive bump;
Attaching at least one semiconductor die over at least two segments of the plurality of segments in an electrically connected form;
Attaching at least one other semiconductor die in electrical connection to any one of the two segments,
/ RTI >
Wherein one of the two segments comprises:
Functional segments in which a relatively large number of through silicon vias (TSV) and I / O terminals are formed to cope with a high-functional semiconductor device requiring a relatively large number of I / O terminals,
Wherein the other of the two segments comprises:
Functional segments in which a relatively small number of through silicon vias (TSV) and I / O terminals are formed so as to correspond to a low-function semiconductor device requiring a relatively small number of I / O terminals
A method of fabricating a semiconductor package.
제 6 항에 있어서,
상기 확장용 기판은,
복수의 관통 실리콘 비아가 형성된 분리형 인터포저인
반도체 패키지 제작 방법.
The method according to claim 6,
Wherein the extension substrate comprises:
A separable interposer in which a plurality of through silicon vias are formed
A method of fabricating a semiconductor package.
삭제delete 삭제delete 제 6 항에 있어서,
상기 도전성 범프는,
솔더 볼 또는 표면에 솔더가 코팅된 구리 볼인
반도체 패키지 제작 방법.
The method according to claim 6,
The conductive bump may include:
Solder balls or copper balls coated with solder on the surface
A method of fabricating a semiconductor package.
제 6 항에 있어서,
상기 제작 방법은,
상기 확장용 기판과 반도체 다이를 몰드 부재로 매립하는 과정
을 더 포함하는 반도체 패키지 제작 방법.The method according to claim 6,
In the manufacturing method,
A process of embedding the extension substrate and the semiconductor die in a mold member
Further comprising the steps of:
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