KR101604120B1 - Semiconductor package structure using ets and method thereof - Google Patents

Semiconductor package structure using ets and method thereof Download PDF

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KR101604120B1
KR101604120B1 KR1020140056413A KR20140056413A KR101604120B1 KR 101604120 B1 KR101604120 B1 KR 101604120B1 KR 1020140056413 A KR1020140056413 A KR 1020140056413A KR 20140056413 A KR20140056413 A KR 20140056413A KR 101604120 B1 KR101604120 B1 KR 101604120B1
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South Korea
Prior art keywords
metal interconnection
pad
interconnection pad
electronic device
insulating layer
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KR1020140056413A
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Korean (ko)
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KR20150129440A (en
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임호정
김병진
신민철
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앰코 테크놀로지 코리아 주식회사
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Priority to KR1020140056413A priority Critical patent/KR101604120B1/en
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

According to the present invention, in a semiconductor package using ETS, when an electronic element such as a semiconductor active element or a passive element is adhered to the upper part of the ETS, the peripheral area of the ETS pad embedded in the insulating layer such as the prepreg film is trench etched and connected to the ETS pad A relatively high molding clearance can be ensured by forming a trench having a certain depth in the lower portion of the electronic device, thereby making it possible to improve voids in the molding process.

Description

 [0001] DESCRIPTION [0002] SEMICONDUCTOR PACKAGE STRUCTURE USING ETS AND METHOD THEREOF [

The present invention relates to a semiconductor package manufacturing method, and more particularly, to a semiconductor package using an ETS, in which an electronic element such as a semiconductor active element or a passive element is adhered on an ETS (embeded trace substrate) A relatively high molding clearance can be ensured by forming a trench having a certain depth in the lower portion of the electronic device connected to the ETS pad by trench etching the peripheral region of the embedded ETS pad, The present invention relates to a method and a structure for manufacturing a semiconductor package using ETS, which can improve the void generation.

Generally, the ETS method is a technique for embedding a metal wiring pad for connection of an electronic device into an insulating layer such as a prepreg film.

1 shows a package structure in which a semiconductor electronic device is connected to an ETS pad. At this time, the semiconductor electronic element is referred to as an active element such as a transistor or a passive element such as a capacitor. In FIG. 1, a passive element such as a capacitor is connected to an ETS pad .

1, a soldermask 104 of an area to which a capacitor is to be connected is opened on a prepreg 100 in which an ETS pad 102 is embedded and a capacitor 106 And then a molding process is performed to cover the capacitor 106 using a mold compound such as an epoxy molding compound (EMC) to form a semiconductor package.

However, as shown in FIG. 1, in the conventional semiconductor package structure using ETS, since the ETS pad is formed in a form embedded in an insulating layer such as a prepreg, and passive elements such as a capacitor are connected to the ETS pad, The clearance 108 for molding between the prepreg film and the prepreg film is very low, and voids are generated in the lower region of the capacitor during the molding process.

(Patent Literature)

Korean Published Patent No. 10-2012-0112464 (Published on October 11, 2012)

Therefore, in the semiconductor package using ETS, when the electronic device such as a semiconductor active device or a passive device is adhered to the upper part of the ETS, the peripheral area of the ETS pad buried in the insulating layer such as the prepreg film is trench etched and connected to the ETS pad A method of fabricating a semiconductor package using ETS that can improve the void generation during the molding process because a relatively high molding clearance can be secured by forming a trench having a certain depth in an underlying electronic device. .

According to the present invention, there is provided a method of manufacturing a semiconductor package using ETS, comprising the steps of: applying a solder mask to an upper portion of an insulating layer in which a first metal interconnection pad is embedded; Etching a portion of the solder mask to open a portion of the entire region of the first metal interconnection pad except the region where the electronic device is connected and trenching an outer region of the first metal interconnection pad; Forming the first metal interconnection pad with an island type second metal interconnection pad isolated by the trench; connecting the electronic element on the second metal interconnection pad; And performing molding to cover the electronic device with respect to the upper surface of the electronic device.

In addition, in the step of performing the molding, a first step of filling a molding compound in the trench formed to isolate the second metal interconnection pad in a lower portion of the electronic device, And filling the remaining region with the molding compound.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor package using ETS, comprising the steps of: applying a solder mask to an upper portion of an insulating layer having a first metal interconnection pad embedded therein; Etching and etching a part of the solder mask to open a first region of a predetermined central portion of the entire region of the first metal wiring pad and a portion of the insulating layer adjacent to the first region; , Forming the first metal interconnection pad with a second metal interconnection pad of the type separated right and left on the insulating layer by the trench, connecting the electronic element on the second metal interconnection pad, And performing molding to cover the electronic device with respect to the upper surface of the substrate including the space.

In addition, in the step of performing the molding, a first step of filling a molding compound in the trench, which separates the second metal interconnection pad left and right, under the electronic device, And filling the remaining region with the molding compound.

Further, the insulating layer is formed of a prepreg film.

The first metal interconnection pad is formed on the insulating layer by an ETS method.

The first metal interconnection pad may be formed of a single pad having a width and a length corresponding to the width of the electronic device connected to the upper portion of the first metal interconnection pad.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor package using ETS, comprising the steps of: applying a solder mask to an upper portion of an insulating layer having a first metal interconnection pad embedded therein; Etching a part of the solder mask to open the second metal wiring pad; forming a second metal wiring pad on the first metal wiring pad to a predetermined first thickness; And performing molding to cover the electronic device with respect to an upper surface of the substrate including a space formed between the insulating layer and the electronic device by a height of the second metal interconnection.

The second metal interconnection pad is formed to be smaller than or equal to the area of the first metal interconnection pad.

The present invention also provides a semiconductor package structure using ETS, which is applied to an upper portion of an insulating layer in which a first metal interconnection pad is buried and an insulating layer in which the first metal interconnection pad is buried, A trench formed by etching an outer region of the first metal interconnection pad except an area where an electronic device is connected and an outer area of the first metal interconnection pad; And a second metal interconnection pad formed in an island type by being isolated by the first metal interconnection pad.

The present invention also provides a semiconductor package structure using ETS, which is applied to an upper portion of an insulating layer in which a first metal interconnection pad is buried and an insulating layer in which the first metal interconnection pad is buried, A trench formed by etching a first region of a predetermined central portion of the entire region of the first metal wiring pad and a portion of the insulating layer adjacent to the first region; And a second metal interconnection pad formed in a type separated laterally by the trench.

Further, the insulating layer is formed of a prepreg film.

The first metal interconnection pad is formed on the insulating layer by an ETS method.

The first metal interconnection pad may be formed of a single pad having a width and a length corresponding to the width of the electronic device connected to the upper portion of the first metal interconnection pad.

The present invention also provides a semiconductor package structure using ETS, which is applied to an upper portion of an insulating layer in which a first metal interconnection pad is buried and an insulating layer in which the first metal interconnection pad is buried, And a second metal wiring pad formed on the first metal wiring pad at a predetermined thickness.

The second metal interconnection pad is formed to be smaller than or equal to the area of the first metal interconnection pad.

According to the present invention, in the semiconductor package using ETS, when the electronic element such as the semiconductor active element or the passive element is adhered on the ETS, the peripheral region of the ETS pad embedded in the insulating layer such as the prepreg film is trench etched and connected to the ETS pad It is possible to secure a relatively high molding clearance by forming a trench having a certain depth in the lower part of the electronic device, thereby making it possible to improve the problem of void generation in the molding process.

1 is a sectional view of a semiconductor package structure using a conventional ETS,
FIGS. 2A to 2D are process cross-sectional views of a semiconductor package using an ETS according to an embodiment of the present invention,
3A to 3D are process sectional views of a semiconductor package using an ETS according to another embodiment of the present invention,
4A to 4D are process sectional views of a semiconductor package using ETS according to another embodiment of the present invention.

Hereinafter, the operation principle of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions of the present invention, and these may be changed according to the intention of the user, the operator, or the like. Therefore, the definition should be based on the contents throughout this specification.

FIGS. 2A to 2D are cross-sectional views illustrating an ETS package manufacturing process according to an embodiment of the present invention. Hereinafter, the ETS package manufacturing process of the present invention will be described in detail with reference to FIGS. 2A to 2D.

First, as shown in FIG. 2A, a prepreg 202, which is an insulating layer, is formed on the substrate 200 to a predetermined thickness. At this time, the prepreg film 202 may be embeded with a predetermined pattern of a first metal wiring pad 204 such as a trace through an ETS (Embedded Trace Substrate) method.

A solder mask 206 is applied to the upper portion of the prepreg film 202 and selectively etched so as to expose the first metal wiring pads 204 on the prepreg film 202, A solder mask 206 having a predetermined area including the metal wiring pads 204 is formed. At this time, the prepreg film 204 may be a composite of glass fiber or resin.

Next, as shown in FIG. 2B, a photoresist is applied to the top of the prepreg film 202 and patterned. Then, using a photoresist mask 208 formed through patterning, The first metal interconnection pad 204 embedded in the prepreg film 202 is etched to form a second metal interconnection pad 210 having a desired pattern as shown in FIG.

At this time, the photoresist mask 208 may be formed on the entire surface of the first metal interconnection pad 204 except for the area where the electronic element such as the active element or the passive element is connected, A part of the prepreg film 202 located at the outer periphery may be patterned to be opened.

Reference numeral 250 denotes a plan view of the package up to the process of FIG. 2C. As shown in the reference numeral 250, the photoresist mask 208 connects the electronic elements among the entire region of the first metal wiring pad 204 A portion of the prepreg film 202 located outside the first metal interconnection pad 204 is trench-etched and the first metal interconnection pad 204 is etched to form a trench Type second metal wiring pads 210 isolated by the first metal wiring pads 252.

2D, after the electronic device 214 is connected to the second metal interconnection pad 210, the upper surface of the substrate 200, including the trench 252 located below the electronic device 214, A molding process for filling a mold compound such as an epoxy molding compound (EMC) is performed to cover the electronic device 214 with respect to the surface.

Accordingly, in the embodiment of the present invention, a higher molding clearance 260 can be ensured due to the trench 252 formed in the periphery of the second metal wiring pad 210 on the prepreg film 202, It is possible to improve problems such as generation of voids in the process.

3A to 3D are cross-sectional views illustrating an ETS package manufacturing process according to another embodiment of the present invention. Hereinafter, the ETS package manufacturing process of the present invention will be described in detail with reference to FIGS. 3A to 3D.

First, as shown in FIG. 3A, a prepreg 302, which is an insulating layer, is formed on the substrate 300 to a predetermined thickness. At this time, the prepreg film 302 may be embeded with a predetermined pattern of a first metal wiring pad 304 such as a trace through an Embedded Trace Substrate (ETS) method.

Then, a solder mask 306 is applied to the upper portion of the prepreg film 302, and then the first metal wiring pads 304 are selectively etched to expose the first metal wiring pads 304 on the prepreg film 302, A solder mask 306 having a predetermined area including the metal wiring pads 304 is formed.

Next, as shown in FIG. 3B, a photoresist is applied to the top of the prepreg film 302 and patterned. Then, using a photoresist mask 308 formed through patterning, The first metal interconnection pads 304 buried in the prepreg film 302 are partially etched to form the second metal interconnection pads 310 having the desired pattern as shown in FIG. 3C.

The photoresist mask 308 may include a first region and a first region of a predetermined central portion except a region to which an electronic device such as an active device or a passive device is connected in the entire region of the first metal interconnection pad 304, A part of the adjacent prepreg film 302 may be patterned to be opened.

Reference numeral 350 denotes a plan view of the package up to the process of FIG. 3C. As shown in the reference numeral 350, the photoresist mask 308 connects the electronic elements of the entire region of the first metal interconnection pad 304 And the first metal wiring pad 304 is etched to form a trench 352 formed by etching. The trench 352 is formed by etching the first region of the prepreg film 302 and the first region of the prepreg film 302 adjacent to the first region, And the second metal wiring pads 310 are separated from each other by the right and left sides.

3D, the electronic device 314 is connected to the second metal interconnection pad 310, and then the upper part of the substrate 300 including the trench 352 located below the electronic device 314, A molding process for filling a mold compound such as EMC (epoxy molding compound) is performed so as to cover the electronic device 314 with respect to the surface.

Accordingly, in the embodiment of the present invention, a higher molding clearance 360 can be secured due to the trench 352 formed between the second metal wiring pads 310 on the prepreg film 302, It is possible to improve problems such as generation of voids in the process.

4A to 4C are cross-sectional views illustrating an ETS package manufacturing process according to another embodiment of the present invention. Hereinafter, the ETS package manufacturing process of the present invention will be described in detail with reference to FIGS. 4A to 4C.

First, as shown in FIG. 4A, a prepreg 402, which is an insulating layer, is formed on the substrate 400 to a predetermined thickness. At this time, the prepreg film 402 may be embeded with a predetermined pattern of a first metal wiring pad 404 such as a trace through an ETS (Embedded Trace Substrate) method.

A solder mask 406 is coated on the prepreg 402 so that the first metal wiring pads 404 on the prepreg film 402 are selectively etched to expose the first metal wiring pads 404, A solder mask 406 having a predetermined area including the metal wiring pads 404 is formed.

Next, as shown in FIG. 4B, a metal material such as copper (Cu) is deposited on the first metal interconnection pad 402 and patterned through a photolithography process to form a first metal interconnection pad 402, A second metal interconnection pad 408 is formed on the second metal interconnection pad 408. In this case, the area of the second metal interconnection pad 408 may be less than or equal to the area of the first metal interconnection pad 402, the height of the second metal interconnection pad 408 may be a predetermined thickness, For example, the height of the first metal interconnection pad 402.

Reference numeral 450 denotes a plan view of the package up to the process of FIG. 4B. As shown in reference numeral 450, a second metal wiring pad 408 is vertically stacked on the first metal wiring pad 304 .

4C, after the electronic device 414 is connected to the second metal interconnection pad 408, a space formed by the step of the second metal interconnection pad 408 is formed under the electronic device 414 A molding process is performed to fill a mold compound such as an EMC molding compound to cover the electronic device 414 with respect to the upper surface of the substrate 400. [

Accordingly, in the embodiment of the present invention, a higher molding clearance can be ensured due to the space formed by the step of the second metal wiring pads 408 on the prepreg film 402, ) Can be improved.

As described above, according to the present invention, in the semiconductor package using ETS, when the electronic element such as the semiconductor active element or the passive element is adhered on the ETS, the peripheral region of the ETS pad buried in the insulating layer such as the prepreg film is trench etched A relatively high molding clearance 460 can be ensured by forming a trench having a certain depth in the lower portion of the electronic device connected to the ETS pad, thereby improving voids in the molding process .

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention should not be limited by the described embodiments but should be defined by the appended claims.

202: prepreg film 204: first metal wiring pad
206: solder mask 210: second metal wiring pad
214: electronic device 252: trench

Claims (16)

Applying a solder mask to an upper portion of the insulating layer on which the first metal wiring pads are embedded on the substrate,
Etching a portion of the solder mask above the insulating layer to open the first metal interconnection pad;
Trenching the remaining region of the first metal wiring pad except the region where the electronic element is connected and the outer region of the first metal wiring pad,
Forming the first metal interconnection pad into an island-type second metal interconnection pad isolated by the trench;
Connecting the electronic device on the second metal interconnection pad,
Performing molding to cover the electronic device against an upper surface of the substrate including the trench space
Method of fabricating semiconductor package using ETS.
The method according to claim 1,
In performing the molding,
A first step of filling a molding compound in the trench formed in the lower part of the electronic device to isolate the second metal wiring pad;
After the first step, a second step of filling the remaining area of the electronic device revealed with the molding compound
Wherein the semiconductor package is formed of a conductive material.
Applying a solder mask to an upper portion of the insulating layer on which the first metal wiring pads are embedded on the substrate,
Etching a portion of the solder mask above the insulating layer to open the first metal interconnection pad;
Trenching a first region of a predetermined central portion of the entire region of the first metal interconnection pad and a portion of the insulating layer adjacent to the first region;
Forming the first metal interconnection pad with a second metal interconnection pad of a separated type on the insulating layer by the trench;
Connecting an electronic device on the second metal interconnection pad,
Performing molding to cover the electronic device against an upper surface of the substrate including the trench space
Wherein the ETS is a semiconductor package.
The method of claim 3,
In performing the molding,
A first step of filling a molding compound in the trench, which separates the second metal interconnection pad left and right, under the electronic device;
After the first step, a second step of filling the remaining area of the electronic device revealed with the molding compound
Wherein the semiconductor package is formed of a conductive material.
The method according to claim 1 or 3,
Wherein the insulating layer
Wherein the semiconductor substrate is formed of a prepreg film.
The method according to claim 1 or 3,
The first metal interconnection pad may include:
Wherein the insulating layer is formed on the insulating layer by an ETS method.
The method according to claim 1 or 3,
The first metal interconnection pad may include:
Wherein the first metal interconnection pad is formed of one pad that is not separated and has a width and a length corresponding to the width of the electronic device connected to the upper portion of the first metal interconnection pad.
Applying a solder mask to an upper portion of the insulating layer on which the first metal wiring pads are embedded on the substrate,
Etching a portion of the solder mask above the insulating layer to open the first metal interconnection pad;
Forming a second metal interconnection pad on the first metal interconnection pad to a predetermined first thickness;
Connecting an electronic device on the second metal interconnection pad,
Performing molding to cover the electronic device with respect to an upper surface of the substrate including a space formed between the insulating layer and the electronic device by a height of the second metal interconnection
Wherein the ETS is a semiconductor package.
9. The method of claim 8,
Wherein the second metal interconnection pad comprises:
Wherein the area of the first metal wiring pad is smaller than or equal to the area of the first metal interconnection pad.
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KR1020160014955A Division KR101688081B1 (en) 2016-02-05 2016-02-05 Ets structure

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009135444A (en) 2007-10-15 2009-06-18 Power Integrations Inc Package for power semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009135444A (en) 2007-10-15 2009-06-18 Power Integrations Inc Package for power semiconductor device

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