KR101590480B1 - Pipeline Analog to Digital Converter - Google Patents

Abstract

The present invention relates to a pipelined ADC using a SAR ADC based MDAC. In particular, the residual voltage amplifier of MDAC is replaced with a preamplifier in the comparator of the SAR ADC converter, and the residual voltage gain error generated at this time is compensated in the digital domain. The linear voltage approximation is used to compensate the residual voltage gain error Line ADC.
The pipelined ADC according to the present invention amplifies the residual voltage by using a preamplifier PA (already provided in the comparator) used in a comparator of the SAR ADC without using a separate amplifier, It is advantageous to reduce the area of the antenna.
In addition, the distortion of the amplified residual voltage caused by the nonlinear characteristic of the gain of the preamplifier is corrected in the digital domain, and in performing the linear approximation accompanied with the correction, the accuracy of the correction can be improved by refining the reference voltage Therefore, it has the advantage of securing the performance of the pipelined ADC.

Description

A pipeline ADC {Pipeline Analog to Digital Converter}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipelined analog to digital converter (ADC), and more particularly to a pipelined ADC based on a Successive Approximation Register ADC (SAR ADC).

Recent advances in CMOS process technology enable the realization of digital circuits capable of small area, low power and high speed operation, as well as enabling various complex signal processing in the digital domain. However, due to low supply voltages and degraded characteristics of the scaled device, analog circuits are becoming more difficult to design and require a relatively large area and power consumption compared to digital circuits.

Therefore, in order to maximize the advantages of process technology, all signals are converted into digital signals in the system, and the role of ADC that converts external analog input signal to digital signal becomes very important. In particular, the development of display technologies such as communication technology and high-definition (HD) and ultra high-definition (UHD) accelerates the development of high-performance multimedia video systems. Possible pipeline ADC design technology is becoming an important issue.

Korean Registered Patent No. 10-1287097, Registered on Mar. 10, 2013.

A problem to be solved by the present invention is to amplify the residual voltage output from the MDAC of the pipelined ADC using MDAC based on the SAR ADC to a preamplifier provided in the comparator of the SAR ADC converter, This paper proposes a SAR ADC based pipeline ADC that compensates residual voltage gain error in the digital domain, but compensates (compensates) the residual voltage gain error using linear approximation.

In order to solve the above problems, a pipelined ADC

A signal obtained by amplifying an input signal of each stage of a pipelined ADC based on a successive approximation register ADC (SAR ADC) and a difference signal (residual voltage) of a signal obtained by quantizing the input signal, And an MDAC (Multiplying Digital to Analog Converter) for transmitting to the next stage. The residual voltage is amplified by using a preamplifier provided in the comparator of the SAR ADC, thereby solving the above problem.

The pipelined ADC according to the present invention amplifies the residual voltage by using a preamplifier PA (already provided in the comparator) used in a comparator of the SAR ADC without using a separate amplifier, It is advantageous to reduce the area of the antenna.

In addition, the error (distortion) of the amplified residual voltage caused by the nonlinear characteristic of the preamplifier gain is corrected in the digital domain, and in performing the linear approximation accompanied with the correction, the reference voltage for error measurement is subdivided Therefore, it is possible to improve the accuracy of the correction, and as a result, it is possible to secure the performance of the pipelined ADC.

FIG. 1A is a diagram schematically showing a configuration of a conventional general pipeline ADC.
1B is a view showing the configuration of the MDAC of FIG. 1A.
FIG. 1C is a diagram illustrating a residual voltage transfer characteristic when there is an offset and a residual voltage gain error in the MDAC of FIGS. 1A to 1B. FIG.
FIG. 2A is a diagram illustrating a configuration of a pipelined ADC according to the present invention.
FIG. 2B is a diagram illustrating the configuration of the MDAC of each stage of the pipelined ADC according to the present invention.
FIG. 2C is a graph showing an example of the residual voltage transfer characteristic of the MDAC when only the non-linear gain characteristic is considered.
FIG. 2D is a graph enlarging a portion corresponding to the input voltage V _IN from 0 to V _REF / 32 in the graph shown in FIG. 2C.
FIG. 2E is a graph illustrating a process of calculating the error of the MDAC output voltage of each stage using the linear approximation of FIG. 2D.
FIG. 2F is a diagram showing reference voltages (VDAC _REF ) for measuring the nonlinear error of the preamplifier gain in the error measurement mode.
Figures 2G-2I illustrate the process of measuring preamplifier output error by applying (7/256) V _REF , one of the various reference voltages shown in Figure 2F, to the MDAC preamplifier of the second stage (STAGE 2) Fig.
2J is a diagram showing an interval information detecting circuit for error correction of a digital output.
FIG. 3A is a timing diagram in an error measurement mode, and FIG. 3B is a diagram showing a timing diagram in a normal mode.
4A to 4C are diagrams illustrating simulation results of operation of a pipelined ADC according to the present invention.

Prior to the description of the concrete contents for the implementation of the present invention, for the sake of understanding, the configuration and operation of the existing pipeline ADC and the outline of the solution of the problem to be solved by the present invention will be given first. In the drawings, the same reference numerals are used to designate like elements in different drawings, and the same reference numerals (if any) It is possible to quote the element beforehand.

FIG. 1A is a diagram schematically showing a configuration of a conventional general pipeline ADC.

Each stage consists of a sample and hold amplifier (SHA), a sub-ADC (n-bit A / D), a sub-DAC (n-bit D / A), a subtractor, And a voltage amplifier (G is a residual voltage gain), and each stage is cascade connected to implement a pipelined ADC. The part consisting of the sub-DAC, the subtractor, and the residual voltage amplifier is called MDAC (Multiplying Digital to Analog Converter). The MDAC is amplifying the residual voltage (Residue) caused by the input signal (V ₁₎ and the quantized output signal (D _O2) of each stage signal (V ₂ = G · Residue) to the next stage input signal, and the overall performance of the pipeline ADC is determined according to the accuracy of the output signal V ₂ of each stage.

1B is a view showing the configuration of the MDAC of FIG. 1A.

D _n (n is a natural number) is generated as a binary code output of the sub-ADC using the unit capacitor row (C ₁ , C ₂ , ..., C _n ) -1. ≪ / RTI > The MDAC generates an output signal V _{RES obtained} by amplifying a residual voltage Residue obtained by subtracting an analog value (output value of sub-DAC) corresponding to the output value D _n of the sub-ADC from an input signal V _IN (output signal of SHA) do. V _RES is given by the following equation (1), and the residual voltage gain G is determined by the capacitor value C _n , C _F and the voltage gain A of the amplifier as shown in the following equation (2). Thus, the matching of the capacitors and the voltage gain A of the amplifier are important factors that determine the overall performance of the MDAC.

--- 식(1).

--- Expression (1).

--- 식(2).

- (2).

FIG. 1C is a diagram illustrating a residual voltage transfer characteristic when there is an offset and a residual voltage gain error in the MDAC of FIGS. 1A to 1B. FIG.

It can be seen from the characteristics shown in FIG. 1C that the linearity of the digital output of the residual voltage amplifier is degraded by the offset and the error of the residual voltage gain. In order to ensure linearity, one of the important performances of the ADC, a residual voltage amplifier having a correct voltage gain is required. This means that the digital correction technique proposed by the present invention requires the correction of the inaccurate and nonlinear voltage gain of the amplifier .

1C shows a case in which a missing code is generated in the digital output voltage because the gain A of the residual voltage amplifier is smaller than the ideal case, and FIG. 1B shows the gain A of the residual voltage amplifier It is non-monotonic if an output code that is larger than the ideal case and overlaps occurs in the digital output voltage.

The error of the residual voltage gain is due to the mismatch of the capacitor, the finite voltage gain of the amplifier, etc., and compared with the output value in the ideal case in the vicinity of the amplified residual voltage segments determined by the sub- So that a larger or smaller output (V _RES ) is generated. As a result, the resulting output of the pipelined ADC results in missing or redundant code, resulting in distortion of the signal and degrading the overall performance of the pipelined ADC.

The pipelined ADC uses an op-amp circuit using feedback, as shown in FIG. 1B, in order to ensure the linearity of the MDAC output and the accurate residual voltage gain. Since the residual voltage gain of the MDAC is determined by the voltage gain A of the op-amp with reference to Equation (2), assuming that the matching of the capacitors is sufficiently good, a high gain op-amp is required for a high resolution pipelined ADC implementation need. However, due to the miniaturization of the CMOS process, the gain that can be realized in a single amplifier stage is reduced, so that a multi-stage op-amp (multi-stage amplifier) can be used to realize the high residual voltage gain required for MDAC.

However, the use of multi-stage amplifiers involves problems that lead to an increase in area and power consumption, and additional techniques such as frequency compensation should be used as multi-stage op-amps can cause stability problems when using feedback.

Because consuming the highest power among the components of the pipelined ADC is the op amp used in MDAC, it is most important to reduce the power consumption of the op amp in order to reduce the overall power consumption of the pipelined ADC. For this purpose, techniques such as op-amp sharing and op-amp static current minimization have been proposed. In addition, research has been actively carried out on a correction technique which uses an analog circuit which does not satisfy the performance such as gain and linearity, and which solves the problem of the signal distortion by using a predetermined signal processing .

The correction technique can be largely divided into analog-domain correction and digital-domain correction. The calibration technique in the analog domain is a way to improve the performance of the pipelined ADC through additional analog circuitry, and its performance is determined by the accuracy of the analog circuitry used for calibration. Therefore, the area and the power consumption are increased by addition of elements and circuit blocks for accurate correction. However, since the correction technique in the digital domain improves the performance only through the digital signal processing without using the additional analog circuit, it is less influenced by the accuracy of the circuit or the device as compared with the correction technique in the analog domain. Particularly, due to the recent miniaturization of the process, the area and power consumption required for the digital circuit are rapidly reduced, and the importance is emphasized as a key technology for implementing a low power, high speed and high resolution ADC converter.

For this reason, various digital calibration techniques have been used to realize a 12-bit or higher-resolution pipelined ADC with low power consumption. However, as the calibration accuracy increases, the digital calibration circuit for error signal processing in the digital domain becomes complicated and the cost increases there is a problem.

Therefore, in order to reduce the power consumption of the pipelined ADC, the solution of the problem to be solved by the present invention is to integrate the residual voltage amplification function of the existing MDAC into a preamplifier (already provided in the comparator) (preamp), and to correct the residual voltage gain error (distortion) in the digital domain in order to improve the complexity of the correction circuit. This approach can improve the performance of calibration by refining the reference voltage for calibration without additional circuitry (without additional amplifiers), and there is a limit to the size of the residual voltage amplifier of existing pipelined ADCs The preamplifier can be fabricated in a relatively small area so that it can be used in microprocessing.

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. Detailed description of known functions and configurations associated with the present invention, The detailed description thereof will be omitted.

FIG. 2A is a diagram illustrating a configuration of a pipelined ADC according to the present invention.

The pipelined ADC according to the present invention has a pipeline structure composed of three stages (STAGE 1, STAGE 2, Back-end ADC) similar to the conventional general pipelined ADC, and each sub-ADC has the same And a 6-bit SAR ADC (6b SAR ADC). Each stage also has a MDAC. The first and second encodings are implemented as mid-treads. The reason for using the 6-bit SAR ADC for the first stage (STAGE 1) and the second stage (STAGE 2) is to generate the reference voltage for error measurement and correction of the preamplifier output from these two stages in order to realize the residual voltage transfer characteristic of the mid-tread method.

On the other hand, in order to prevent the deviation of the residual voltage amplified by the offset of the signal path from the full scale of the reference voltage V _REF , A 5-bit MDAC with offset error correction range is implemented using an overlap region. Accordingly, the maximum residual voltage of each stage of the pipelined ADC according to the present invention is 1/32 of the entire area, and the maximum output of the MDAC amplified by 16 times is half of the entire area. The raw data of the pipelined ADC according to the present invention is 14 bits (5-5-6 structure) and is corrected in the digital domain by the first correction unit to truncate LSB 2 bits, Obtain the final 12-bit output (D _OUT ) for the analog input (V _IN ) of the ADC.

FIG. 2B is a diagram illustrating the configuration of the MDAC of each stage of the pipelined ADC according to the present invention.

As mentioned above, the conventional MDAC of a pipelined A / D converter uses an op-amp application circuit (amplifier) of feedback structure to ensure the accuracy of the residual voltage amplification gain and the high linearity of this gain. However, in order to satisfy the performance required for high-speed, high-resolution operation, a large number of op-amps having a feedback structure with a high gain and a wide bandwidth are required, thereby increasing the area of the circuit (chip) and power consumption.

To solve this problem, the pipelined ADC according to the present invention amplifies the residual voltage using a preamplifier (PA) used in a comparator of a SAR ADC without using a separate amplifier, thereby reducing power consumption and chip area .

Referring to FIG. 2B, the MDAC of each stage of the pipelined ADC according to the present invention includes 64 unit capacitors (in FIG. 2B, the number before the C of each capacitor means the number of capacitors) It is implemented as a 6-bit DAC based on a capacitor row. The comparator consists of a preamplifier (PA) and a latched comparator, and the open circuit gain PAG of the preamplifier (PA) in the comparator is 16. A preamplifier (PA) is placed at the front of the latch comparator to apply a larger input signal to the latch comparator in order to avoid metastability problems by reducing the time it takes to output the digital output after the input signal is applied to the latch comparator .

The MDAC of each stage of the pipelined ADC according to the present invention transfers the value (V _RES ) amplifying the residual voltage applied to the input of the comparator to the next stage after the last bit of the SAR ADC is determined. The switching method of the switches is performed by the switching control unit.

V _IN : Input voltage of the sub-SAR ADC.

V _REF : External reference voltage corresponds to the full scale of the external input signal.

V _RES : Residual voltage amplified through the preamplifier.

V _CM : common-mode voltage.

Meanwhile, the switching method in the normal mode (details of which will be described later) is the same as that of the conventional common-mode based SAR ADC. In the first phase, the common mode voltage (V _CM ) and the input signal (V _IN ) to be converted are applied to the top and bottom plates of the capacitor to sample the input signal, respectively. In the second phase, when the top plate of the capacitor is disconnected and the bottom plate is connected to the common mode voltage (V _CM ), when the comparator is driven, the most significant bit (MSB) is outputted by comparing the sampled signal with 0, The reference voltage V _REF applied to the capacitor row is changed according to the bit value and the LSB (least significant bit) is sequentially output from the MSB.

After the LSB is output, the amount of charge corresponding to the residual voltage is stored in the capacitor row. Therefore, the residual voltage is applied to the differential input terminal (V _PA , the top plate of the capacitor row) of the preamplifier in the comparator, and the output obtained by amplifying the residual voltage by the voltage gain PAG of the preamplifier is V _RES . The amplified residual voltage (V _RES ) is sampled at the input of the next stage, and is converted to digital through the same process.

The MDAC of the SAR ADC-based pipelined ADC according to the present invention amplifies the residual voltage through the comparator preamplifier. The amplified residual voltage V _RES is curved out of the ideal waveform (straight line) due to the nonlinearity of the preamplifier gain (See FIG. 2C, so that the voltage gain V _RES / V _IN also exhibits a nonlinear characteristic). This nonlinearity has the problem of limited resolution because it degrades the linearity of the pipelined ADC (because it deviates much from ideal operating characteristics). Therefore, in order to realize a high resolution of 12 bits or more, the nonlinear characteristic of the voltage gain caused by the nonlinearity of the preamplifier gain PAG must be corrected. That is, the linearity of the voltage gain (preamplifier gain) must be ensured to ensure the manifestation of the ideal operating characteristics of the pipelined ADC.

FIG. 2D is an enlarged graph of the input voltage V _{PA corresponding} to 0 to V _REF / 32 in the graph shown in FIG. 2C. In FIG. 2D, the portion corresponding to 0 to V _REF / 32 is divided into several sections, Approximate waveform in which the curve of the MDAC output voltage (V _RES ) of each divided section is linearly approximated (linear function) so as to have linearity (piecewise linear). Using this linearly approximated waveform of the MDAC output voltage, it is possible to measure the error (distortion) of the MDAC output voltage (amplified residual voltage) versus the ideal case through a simple operation and to improve the accuracy of the correction have.

FIG. 2E is a graph illustrating a process of calculating the error of the MDAC output voltage of each stage using the linear approximation of FIG. 2D.

The reference voltages VDAC _REF (n) and VDAC _REF (n + 1) are applied to the input signal V _PA of the preamplifier PA in the error measurement mode (details of the error measurement mode will be described later) The quantized value D _{N, E, O} (n) and D _{N, E, O} (n + 1) of the output signal amplified by the reference voltage are obtained by the preamplifier. In this case, the ADC for quantizing the preamplifier output signal uses a pipeline structure connected to the rear end of the MDAC for measuring the error, and it is assumed that the correction sequence is applied from the rear to have ideal quantization characteristics. Obtained by the error measurement mode _{D N, E, O (n} ), D N, E, O (n + 1) and the ideal output value for each of the reference voltage input _{D OUT, idl (n),} D OUT, idl (n The error of the output D (j) of the quantized MDAC in the range of D _{N , E, O} (n) ≤ D (j) ≤ D _{N , E, O} (n + 1) j) can be calculated as Equation (3).

--- (3).

The D _{N, E} (n) is a reference voltage input, VDAC _REF (n) measured values D _{N, E, O} in an ideal case free non-quantized value D _{OUT, idl} (n) and the ideal amplifier's output (n) of the Of cars.

D _{N, E} (n) = D _{OUT, idl} (n) - D _{N, E, O} (n)

However _, when D _{N, E and O} (n) are calculated using D _{N, E and O} (n) values actually measured _, the quantization noise contained in D _{N, E and O} (n) accumulates, . To solve this problem, an analog value corresponding to D _{N , E} (n) is generated and quantized to minimize the performance degradation occurring in the correction value calculation process. A concrete implementation method will be described later.

The output D (j) of the quantized MDAC and the corresponding error α (j) are calculated by the above procedure, and the sum of the two values is calculated to obtain the D _CAL (j) approximate to the ideal output.

D _CAL (j) = D (j) +? (J) - (5).

It is noted above that the fundamental cause of the error of the MDAC output voltage (amplified residual voltage) is due to the nonlinearity of the gain PAG of the preamplifier. Therefore, it is necessary to calibrate the PAG by linearly approximating the nonlinearity of the PAG.

First, the nonlinear error of the PAG should be measured, and a reference voltage is required for error measurement. The accuracy of the correction is determined according to the interval between the reference voltages, and the more the intervals defined by the two neighboring reference voltages are, the less the error due to the linear approximation is, .

FIG. 2F shows a reference voltage (VDAC _REF ) for nonlinear error measurement of the PAG in the error measurement mode. In the present invention, the nonlinear error of the PAG is measured for several reference voltages for each stage of the pipelined ADC.

In FIG. 2F, (-12 / 256) V _REF , (-11/256) V _REF , , (11/256) V _REF , and (12/256) V _REF . In this case, the number of intervals defined by the two adjacent reference voltages is 24, (1/256) V _REF . The greater the number of intervals (the narrower the interval between each interval), the less the error due to the linear approximation, and the more accurate the correction can be.

At this time, if the residual voltage amplified by the preamplifier exceeds the ideal output range of ± 0.5V _REF (when the amplified residual voltage deviates from the full range of reference voltage (-V _REF / 2 to V _REF / 2) (Reference voltages in the Extra reference area) against the additional eight reference voltages.

In order to generate a reference voltage for measuring the error of the amplified residual voltage, the pipelined ADC according to the present invention uses a capacitor row DAC already included in the SAR ADC to generate a residual voltage (Refer to FIG. 2B). Since each stage of the pipelined ADC according to the present invention uses a 6-bit SAR ADC, the minimum unit of the reference voltage for measuring the error of the amplified residual voltage that can be generated through the capacitor array is (1/32) V _REF . On the other hand, to increase the accuracy of the correction, a reference voltage spacing smaller than (1/32) V _REF can be created and a resistor ladder can be used for this purpose. For example, a capacitor row By applying a scaled external reference voltage (1/16) V _REF to the DAC using a resistor row, a reference voltage of (1/256) V _REF interval required for the error measurement mode can be generated.

Hereinafter, the operation of the pipelined ADC according to the operation mode of the pipelined ADC according to the present invention will be described.

The operation mode of the pipelined ADC according to the present invention includes two modes, i.e., an error measurement mode and a normal mode. The operation mode of the pipelined ADC according to the present invention will be described with reference to FIG.

First, the operation in the error measurement mode will be described as follows.

The error measurement mode is a mode in which reference voltages (VDAC _REF ) are sequentially applied to the MDAC comparator preamplifier in each stage, and the output signal is quantized by the rear SAR ADC to measure the preamplifier output error.

In other words, the second error measuring unit uses the digital output (a) of the back-end ADC that converts the input signal (V _IN ) to digital to output the preamplifier output error of the second stage (STAGE 2) 2 error, b) is measured in 6 bits. The measurement of the second error (b) is specifically performed by the above-described equation (3). The second compensation unit compensates the preamplifier output (c) of the second stage (STAGE 2) MDAC by reflecting the second error (b) to the preamplifier output (c) of the second stage (STAGE 2) In a normal mode to be described later with reference to equation (5)).

The first stage (STAGE 1) MDAC preamplifier output error (first error, e) is the second stage corrected by the second correction (this correction is done in normal mode, STAGE 2) Measured in 10 bits by the first error measuring unit using the preamplifier output (d) of the MDAC and the digital output (a) of the back-end ADC. The first error can be measured by the equation (3) as in the case of the second error measurement. The first correction unit corrects the first error e to the preamplifier output f of the first stage STAGE 1, (This correction is also made in the normal mode to be described later with reference to equation (5)), so that the input signal (V _IN ) is the final output digitized ( D _OUT ) is generated. On the other hand, it is assumed that the SAR ADC of the last stage (back-end ADC) has a 6-bit Effective Number Of Bit (ENOB) characteristic.

The measurement procedure of the MDAC preamplifier output error (second error) of the second stage (STAGE 2) will be described in more detail as follows.

1) Apply the desired reference voltage VDAC _REF (n) to the input of the comparator preamplifier using the MDAC capacitor row of the second stage (STAGE 2).

2) The second stage (STAGE 2) comparator preamplifier samples the amplified reference voltage to the capacitor column of the SAR ADC of the third stage (Back-end ADC). In this case, PA ₂ and ε ₂ represent the ideal voltage gain of the second stage preamplifier and the voltage gain error of the actually applied preamplifier, respectively.

3) Using the capacitor DAC of the SAR ADC of the third stage (back-end ADC), the output value of VDAC _REF (n) · PA _{2 in the} case where the gain of the preamplifier of the second stage (STAGE 2) The difference between the output signal VDAC _REF (n) · (PA ₂ -ε ₂ ) of the second stage (STAGE 2) including the sampled error, ie, the difference between the output of the MDAC preamplifier output error VDAC _REF n) · ε ₂ .

4) The VDAC _REF (n) · ε ₂ generated in step 3) is quantized to a 6-bit digital value using the SAR ADC of the third stage (back-end ADC).

Figures 2G-2I illustrate the process of measuring the MDAC output error by applying (7/256) V _REF , one of the various reference voltages shown in Figure 2F, to the preamplifier of the second stage (STAGE 2) Fig.

First, as shown in FIG. 2G, the differential capacitor thermal load of the MDAC of the second stage (STAGE 2) is reset. Then, in the next phase, as shown in FIG. 2H, 7C (= 4C + 2C + C) of each of the differential capacitor columns is connected to + V _REF / 16 and -V _REF / 16 to perform charge redistribution in the second stage 2) so that the MDAC of the pre-amplifier differential input V _{iN _ PA2} a reference voltage (7/256) of V _REF. V _{IN_PA2} is amplified by the preamplifier and sampled to the SAR ADC input of the third stage, where the amplified reference voltage includes the nonlinear error of the preamplifier of the second stage (STAGE 2). Finally, by switching the capacitor DAC arrangement of the SAR ADC of the third stage (back-end ADC) as shown in FIG. 2i, only the signal component generated by the gain error of the preamplifier of the second stage (STAGE 2) -end < / RTI > ADC). The SAR ADC of the last stage (back-end ADC) converts the sampled error to a 6-bit digital value. Measure the preamplifier error of the second stage (STAGE 2) for the remaining reference voltages in the same way.

When the error measurement of the MDAC preamplifier output of the second stage (STAGE 2) is completed, the error measurement of the MDAC preamplifier output of the first stage (STAGE 1) is performed by the first error measuring unit. The error measurement procedure of the MDAC preamplifier output of the first stage (STAGE 1) is almost the same as the measurement of the output error of the MDAC preamplifier of the second stage (STAGE 2). However, the output error of the MDAC preamplifier in the first stage (STAGE 1) is measured as a 10-bit digital value using the second (STAGE 2) and the last stage (back-end ADC) The use of the corrected output (d) of the output is different from the case of measuring the error of the second stage (STAGE 2). When the error (error) measurement for all the reference voltages is completed, the output of the MDAC preamplifier is corrected using the measured error in the normal mode to be mentioned immediately.

Next, the operation in the normal mode will be described as follows.

The normal mode uses the output error of the preamplifier measured in the error measurement mode to correct the digital output (the output of the MDAC preamplifier) and adjusts the input signal (V _IN ) (To generate D _OUT ).

In this case, the clock period required for the MDAC of each stage to output the residual voltage for the input is determined by the resolution of the sub-ADC. Using a SAR ADC instead of a typical flash-structured ADC reduces the number of comparators but increases the time required for quantization. The pipelined ADC according to the present invention uses a 6-bit SAR ADC for each stage and obtains a 6-bit output using a half clock cycle. The total of 4 clocks (using a full clock cycle In total, 8 clocks).

The correction value? (J) for the digital outputs (f, c) of the first stage (STAGE 1) and the second stage (STAGE 2) in the normal mode is calculated using the equation (3) Is obtained by a second error measuring unit. At this time, using the contains the above D (j) period information piecewise linear four values required to approximate _{D N, E, O (n} ), D N, E, O (n + 1), D N, E (n), D _{N, E} (n + 1). The section information including D (j) has an n value satisfying the following equation (6) and can be obtained by using a digital comparator of the flash structure shown in FIG. 2J (an interval information detecting circuit for error correction of the digital output) .

_{D N, E, O (n} ) ≤ D (j) ≤ D N, E, O (n + 1), n = -12, -11, ... , +11, +12 - (6).

The interval information detection circuit shown in FIG. 2J compares D (j) with D _{N, E, O} (k) (k = -12 to +12) measured in the error measurement mode and stores the corresponding interval information in a thermometer Code). The following table shows the interval information n for the thermometer code output of the interval information detection circuit.

3A is a diagram showing a timing diagram in an error measurement mode.

For the first stage (STAGE 1), a total latency time of 9 clocks is required to generate the final 10-bit digital output by generating the reference voltage VDAC _REF for the error measurement of the MDAC output. The second (STAGE 2) and third (Back-end ADC) require 5 clocks to output 6 bits of digital output, respectively. Therefore, a total of 79 (= 4 + 5 * 25) clocks are required to measure the error of the first stage (STAGE 1) for 25 digital reference voltages.

In the second stage (STAGE 2), a total of 6 clocks of delay time is required to generate the final 6-bit digital output by generating the reference voltage VDAC _REF for the error measurement of the MDAC output. The third stage (back-end ADC) requires 5 clocks to output a 6-bit digital output. Therefore, in order to measure the error of the second stage (STAGE 2) with respect to 25 digital reference voltages, a total of 76 (= 1 + 5 * 25) clocks are required. A clock is needed.

3B is a diagram showing a timing diagram in a normal mode.

Each stage of MDAC requires 4 clocks to sample the input to produce a digital output and an amplified residual voltage, where each stage of the SAR ADC outputs a digital output every 1/2 clock. Therefore, for 100 [MS / s] operation, each stage SAR ADC should operate at 800 [MHz].

4A to 4C are diagrams illustrating simulation results of operation of a pipelined ADC according to the present invention.

The pipelined ADC according to the present invention performs a motion model simulation assuming a 12-bit 100 [MS / s] operation. It also reflects the non-ideal characteristics of circuits and devices that can occur in actual design. A relative mismatch with an even distribution of 0.1 [%] is applied to the resistor ladder used to generate the scaled external reference voltage ± V _REF / 16, and the capacitor assumes a 12-bit match Relative mismatch with an even distribution of 0.025 [%] was applied. The preamplifier to which the output value is to be calibrated is applied a mismatch with an even distribution of ± 10 [%] in the case of an absolute linear gain. The non-linear gain is obtained by multiplying the absolute output by 10 And [%], respectively. The offset of the preamplifier is set to ± 5 [mV].

4A is a result of performing an operation simulation on a pipelined ADC according to the present invention, reflecting non-ideal characteristics of a circuit and a device.

The output FFT spectrum before correction shows a signal-to-noise and distortion ratio (SNDR) of 47.8 [dB] and a spurious free dynamic range (SFDR) of 60.5 [dB]. After applying the correction technique according to the present invention, [dB] and the SFDR is improved to 88.8 [dB].

4B is a diagram illustrating a simulation result for checking the influence of the accuracy of the scaled external reference voltage ± V _REF / 16 on the performance of the correction technique according to the present invention.

The SNDR for the calibrated output signal was measured with 10 arbitrary conditions for each case while varying the relative mismatch of the resistor string used to scale the external reference voltage from 0.1 [%] to 1 [%]. In this case, the condition of the capacitor mismatch is 0.025 [%] and 0.05 [%], and the other conditions are the same as those of the operation model simulation in FIG. 4A. As can be seen from the measurement results, even when the mismatching condition of the resistance column is 1 [%], the SNDR performance after the correction of the ADC according to the present invention is maintained at 69 [dB] or more.

4C is a diagram showing measurement results of DNL (Differential Nonlinearity) and INL (Integral NonLinearity) of an operation simulation.

When the correction is applied under the same conditions, DNL is 1 [LSB] and INL is 11.22 [LSB]. However, when the correction method according to the present invention is applied, DNL is 0.5 [LSB] and INL is 1.22 [ LSB], the linearity is improved.

The present invention has been described above with reference to preferred embodiments thereof. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The disclosed embodiments should, therefore, be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

Claims (7)

For a pipelined ADC based on a Successive Approximation Register ADC (ADC):
(MDAC) that transfers a signal obtained by amplifying a difference signal (residual voltage) between a signal input to each stage of the pipelined ADC and a signal obtained by quantizing the input signal to the next stage of the pipelined ADC, to Analog Converter)
The amplification of the residual voltage is performed using a preamplifier provided in the comparator of the SAR ADC,
(Error) of the amplified residual voltage caused by the nonlinear (non-ideal) characteristic of the preamplifier gain is measured, and the amplified residual voltage is converted into a linear (ideal) characteristic using the error And an error measurement / correction unit that corrects the error to approximate the error. delete The method according to claim 1,
Wherein the pipelined ADC is a three-stage configuration. 4. The method of claim 3,
The output of the SAR ADC of the back-end ADC of the pipeline ADC is used to obtain the MDAC preamplifier output error of the second stage (STAGE 2) of the pipelined ADC, (First error) of the MDAC preamplifier output error (STAGE 1) of the first stage (STAGE 1) is obtained by using the output of the SAR ADC of the second stage (STAGE 2) and the output of the SAR ADC of the last stage Features a pipelined ADC. 5. The method of claim 4,
A characteristic curve of the amplified residual voltage according to a reference signal (for measurement of the error) for generating the amplified residual voltage is subdivided into a plurality of subdivisions into a plurality of subdivisions, Characterized in that the characteristic curve is linearized by piecewise linearization. 6. The method of claim 5,
Wherein the pipeline ADC comprises a plurality of divisional sections. 7. The method of claim 6,
And directly generated from the MDAC and applied as an input to the preamplifier.

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