KR101570928B1 - Electrostatic Discharge Device of using Lateral Insulated Gate Bipolar Transistor having lower Trigger Voltage - Google Patents

Electrostatic Discharge Device of using Lateral Insulated Gate Bipolar Transistor having lower Trigger Voltage Download PDF

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KR101570928B1
KR101570928B1 KR1020140039461A KR20140039461A KR101570928B1 KR 101570928 B1 KR101570928 B1 KR 101570928B1 KR 1020140039461 A KR1020140039461 A KR 1020140039461A KR 20140039461 A KR20140039461 A KR 20140039461A KR 101570928 B1 KR101570928 B1 KR 101570928B1
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region
well
active region
well active
deep
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KR1020140039461A
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KR20150115091A (en
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구용서
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단국대학교 산학협력단
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Abstract

An electrostatic discharge protection device capable of entering a holding area at a low trigger voltage to perform a stable operation is disclosed. A first P-well active region, an N-well active region and a second P-well active region are formed on the deep N-well region. The first P-well active region is electrically connected to the second P-well active region through the wiring. In addition, the spacing distance between the first P-well active region and the N-well active region is greater than the separation distance between the N-well active region and the second P-well active region. Thus, a punch-through phenomenon occurs between the N-well active region and the second P-well active region, and an equivalent circuit of the diode is formed. This allows the electrostatic discharge protectors to enter the holding area quickly even at low trigger voltages.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a lateral insulated gate bipolar transistor-based electrostatic discharge protection device having a low trigger voltage,

The present invention relates to electrostatic discharge protection, and more particularly, to an electrostatic discharge protection device having a low trigger voltage based on a lateral insulated gate bipolar transistor having a forward diode region.

An electrostatic discharge protection device is an element that protects a semiconductor circuit in a situation where an undesired high voltage such as static electricity is applied among semiconductor elements. The electrostatic discharge protection device is connected to an input terminal of a semiconductor circuit performing a specific function, and maintains the off state when a voltage or a signal having a normal level is applied. In addition, when a surge voltage is applied, the electrostatic discharge protection device turns on and flows a current corresponding to a voltage applied to the ground or the like. This function performs the function of protecting the semiconductor circuit.

The voltage level at which the electrostatic discharge protection device is turned on and starts operation is referred to as a trigger point. Also, a region where a constant voltage state is maintained in a turned-on state is referred to as a holding region. Therefore, when a high level voltage is applied to the semiconductor element by static electricity or the like, the electrostatic discharge protection element operates in the holding area, and the large current flows to the ground through the electrostatic discharge protection element. Therefore, the internal circuit of the chip in which the semiconductor circuit is implemented is protected from impact by static electricity or the like.

1 is a cross-sectional view illustrating an electrostatic discharge protection device using a lateral insulated gate bipolar transistor (LIGBT) according to a related art.

Referring to FIG. 1, a deep N-well region 20 is formed on a p-type substrate 10. On the deep N-well region 20 is provided an insulating layer 50 disposed between the P-well active region, the N-well active region and the P-well active region and the N-well active region.

The P-well active region has a P-well region 40, a first P + region 41 and an N + region 42 formed on the P-well region 40. The dopant concentration in the first P + region 41 is greater than the dopant concentration in the P-well region 40. Also, the N + region 42 is above the dopant concentration of the deep N-well region 20. A first P-type electrode 43 is formed on the first P + region 41 and an N-type electrode 44 is provided on the N + The first P-type electrode 43 and the N-type electrode 44 are electrically connected.

The N-well active region has an N-well region 30 and a second P + region 31 formed on the N-well region 30. In addition, a second P-type electrode 32 is formed on the second P + region 31. The dopant concentration of the N-well region 30 is preferably higher than that of the deep N-well region 20. [

Further, the insulating layer 50 is disposed between the P-well region 40 and the N-well region 30, and is buried with an insulator by a shallow isolation film process. A gate structure 51 is formed on a portion of the insulating layer 50 and on the P-well region 40. The gate structure 51 is composed of a dielectric film and a gate electrode, and is electrically connected to the first P-type electrode 43 and the N-type electrode 44.

The first P-type electrode 43, the N-type electrode 44, and the gate structure 51, which are connected in common, are used as a cathode terminal, and the second P-type electrode 32 is used as an anode terminal in order to function as an electrostatic discharge do. The cathode terminal is connected to the ground.

If the voltage applied through the anode terminal is below the trigger level, the electrostatic discharge protection device does not start operation. This is because the N + region 42, the P-well region 40 and the deep N-well region 20 form an NPN transistor and the voltage of the applied anode terminal acts as a reverse bias to the formed NPN transistor.

When the voltage at the anode terminal rises, the depletion region expands between the P-well region 40 and the deep N-well region 20 due to the reverse bias of the formed NPN transistor. For example, if the dopant concentration of the deep N-well region 20 is lower than the dopant concentration of the P-well region 40, the depletion region encapsulates and expands the deep N-well region 20. Further, due to the ground level applied to the gate structure 50, a phenomenon that holes accumulate in the lower portion of the insulating layer 50 occurs. When the voltage applied to the anode terminal reaches the trigger level, the depletion region expands to the N-well region 30. Further, in the region below the insulating layer, a channel formed by holes is formed. Thus, a current path through the second P + region 31, the N-well region 30 and the P-well active region is formed. The electrostatic discharge protection device has a constant voltage characteristic due to the pinch-off phenomenon in which a shallow channel of holes is formed in the lower portion of the insulating layer 50 in addition to the punch-through phenomenon caused by the expansion of the depletion region. Therefore, even if a high surge voltage is applied, a current is caused to flow to the ground through the anode terminal and the cathode terminal, and a holding region where the anode terminal is set to the trigger level is formed.

The electrostatic discharge protector of FIG. 1 described above serves as an important element of the depletion region expansion operation for the deep N-well region 20. [ Further, in order to secure a stable and constant trigger level, the concentration of the dopant in the deep N-well region 20 and the P-well region 40 must be constantly controlled for each chip formed on the wafer. However, since the concentration of the dopant in the semiconductor manufacturing process has a certain variation range, it is difficult to fix the dopant at a specific trigger level.

In addition, the deep N-well region 20 is encroached in the operation mechanism, and the depletion region is expanded, so that the trigger voltage is set high. If the trigger voltage is high, an unwanted high level voltage is applied to the semiconductor circuit that should normally operate, causing damage to the semiconductor circuit.

Therefore, an electrostatic discharge protection device capable of ensuring a stable holding area with a low trigger level will be required.

SUMMARY OF THE INVENTION The present invention provides an electrostatic discharge protection device capable of performing stable operation even at a low trigger voltage.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a deep N-well region formed on a P-type substrate; A first P-well active region formed on the deep N-well region and interrupting the flow of current when a voltage with a negative trigger voltage is applied to the anode terminal; An N-well active region formed on the deep N-well region and formed at a distance L1 on a side of the first P-well region, the N-well active region being connected to the anode terminal and modeled with a forward diode for a voltage applied; Well region and formed on the side of the N-well region with a spacing distance L2 that is smaller than the spacing distance L1, wherein the pinch-and-well region of the deep N- And a second P-well active region for inducing an OFF phenomenon.

According to the present invention described above, a pinch-off phenomenon occurs between the N-well active region and the second P-well active region. Thus, it is possible to quickly enter the holding region before the pinch-off phenomenon occurs between the first P-well active region and the N-well active region. This means that at low trigger voltages, the electrostatic discharge protectors enter the holding area.

Thus, the semiconductor device can be protected by entering the holding region at a relatively low surge voltage, and stable operation can be ensured.

1 is a cross-sectional view illustrating an electrostatic discharge protection device using a lateral insulated gate bipolar transistor (LIGBT) according to a related art.
2 is a cross-sectional view illustrating an electrostatic discharge protection device according to a preferred embodiment of the present invention.
FIG. 3 is a circuit diagram modeling the electrostatic discharge protection device shown in FIG. 2 according to a preferred embodiment of the present invention.
4 is another circuit diagram modeling the electrostatic discharge protection device shown in FIG. 2 according to a preferred embodiment of the present invention.
5 is a graph for explaining the effects of the electrostatic discharge protection device of FIGS. 2 to 4 according to a preferred embodiment of the present invention.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example

2 is a cross-sectional view illustrating an electrostatic discharge protection device according to a preferred embodiment of the present invention.

Referring to FIG. 2, a deep N-well region 110 is provided on a P-type substrate 100. Well active region 120, an N-well active region 130, and a second P-well active region 140 are provided on the deep N-well region 110. The first P- In addition, an insulating layer 150 is formed between the first P-well active region 120 and the N-well active region 130.

The first P-well active region 120 blocks current flow when a voltage below the trigger voltage is applied to the anode terminal. Further, when the voltage between the anode terminal and the cathode terminal is equal to or higher than the trigger voltage, a current path toward the ground is formed to flow the current to the ground. The first P-well active region 120 includes a first P-well region 121 and a first P + region 122 formed on the first P-well region 121. The first P- An N + region 123 and a second P + region 124, respectively. A first P-type electrode 125 is formed on the first P + region 122, a first N-type electrode 126 is formed on the first N + region 123, and a second P- A P-type electrode 127 is formed. The first P-type electrode 125 and the first N-type electrode 126 are connected in common to form a cathode terminal.

An N-well active region 130 is formed across the insulating layer 150 formed on the side of the first P-well active region 120. [ The N-well active region 130 has an N-well region 131 and a third P + region 132 formed on the N-well region 131. A third P-type electrode 133 is formed on the third P + region 132, and an anode terminal is formed on the third P-type electrode 133. When the voltage is applied through the anode terminal, the third P + region 132 and the N-well region 131 are modeled as a forward diode. Accordingly, the voltage applied to the anode terminal can be applied to the deep N-well region 110 after a predetermined voltage drop.

A second P-well active region 140 is formed on a side surface of the N-well active region 130. The second P-well active region 140 has a second P-well region 141 and a second N + region 142 formed on the second P-well region 141. A second N-type electrode 143 is formed on the second N + region 142 and a second P-type electrode 143 formed on the first P-well active region 120 127, respectively. For example, when a bias is applied through the deep N-well region 110, the second P-well region 141 forms a reverse diode connection structure for the deep N-well region 110. In the second P-well active region 140, a forward diode is formed between the second P-well region 141 and the second N + region 142.

An insulating layer 150 is formed between the first P-well active region 120 and the N-well active region 130. The insulating layer 150 may be buried with an insulating material according to a shallow isolation layer process. A gate structure 151 is formed on a part of the first P-well region 121 and a part of the insulating layer 150. The gate structure 151 may comprise a gate dielectric and a gate electrode. The gate structure 151 is electrically connected to the cathode terminal.

In addition, the insulating layer 150 may be formed between the N-well active region 130 and the second P-well active region 140. When an insulating layer 150 is formed between the two regions, a gate structure is formed over a portion of the formed insulating layer and a portion of the second P-well region 141. The structure of the gate structure is the same as described above.

In addition, when a bias is not applied to the anode terminal, the distance L1 between the first P-well region 121 and the N-well region 131 is larger than the distance between the N-well region 131 and the second P- 141).

Well region 110 due to the forward diode configuration between the third P + region 132 and the N-well region 131 in the N-well active region 130 when a voltage is applied through the anode terminal, A constant bias is applied. A reverse diode appears between the deep N-well region 110 and the first P-well region 121 and a reverse diode appears between the deep N-well region 110 and the second P-well region 141. [ Therefore, the current flowing from the anode terminal to the cathode terminal is cut off. However, there may be a minute amount of current due to the leakage current in the reverse diode as the voltage increases. In addition, as the voltage of the anode terminal increases, the depletion region expands at the interface between the deep N-well region 110 and the first P-well region 121 forming the reverse diode. For example, if the doping concentration of the first P-well region 121 is higher than the doping concentration of the deep N-well region 110, the depletion region is enlarged in the direction of sinking the deep N-well region 110. Also, the depletion region is enlarged at the interface between the deep N-well region 110 and the second P-well region 141 as well. The enlarged depletion region encapsulates the deep N-well region 110.

When the anode voltage continues to increase, a phenomenon that only the depletion region appears between the N-well region 131 and the second P-well region 141 occurs first because the separation distance L2 is smaller than the separation distance L1. Therefore, a punch-through phenomenon may occur across the depletion region formed between the N-well region 131 and the second P-well region 141. [ When an insulating layer and a gate structure are formed between the N-well region 131 and the second P-well region 141, a hole channel is formed below the insulating layer. Thus, a current path from the N-well active region 130 to the second P-well active region 140 at the trigger voltage is formed. On the other hand, no punch-through phenomenon occurs between the first P-well region 121 and the N-well region 131 due to the separation distance L2. Thus, no current path is directed from the N-well active region 130 to the first P-well active region 120 directly.

When the current path is formed between the N-well active region 130 and the second P-well active region 140, the second N-type electrode 143 and the second P-type electrode 127 are electrically connected Current also flows in the first P-well active region 120. [ This forms a current flowing through the second P + region 124 to the first P + region 122. [ Therefore, the trigger voltage applied between the anode terminal and the cathode terminal sharply decreases to the holding voltage. In addition, a resistance component due to the first P-well region 121 exists between the second P + region 127 and the first P + region 122. Therefore, when the amount of current increases with the trigger voltage applied, the voltage drop due to the resistance component of the first P-well region 121 may increase. The increased voltage drop may be set to a certain level due to the forward diode formed by the first P-well region 121 and the first N + region 123. [ Therefore, even if the current increases in the holding state, the increase in the voltage between the anode terminal and the cathode terminal becomes a negligible level, and the voltage difference between the anode terminal and the cathode terminal is kept constant.

 FIG. 3 is a circuit diagram modeling the electrostatic discharge protection device shown in FIG. 2 according to a preferred embodiment of the present invention.

Referring to FIG. 3, it is assumed that a voltage difference less than the trigger voltage is applied between the anode terminal and the cathode terminal. Therefore, the punch-through phenomenon does not occur.

The electrostatic discharge protection capacitor is modeled as three transistors Q1, Q2 and Q3 and one diode D.

The emitter terminal of the first transistor Q1 is connected to the cathode terminal, the collector terminal is connected to the second node N2, and the base terminal is connected to the first node N1. The emitter terminal is modeled as a first N + region 123. The first node N1 is a model of the first P well region 121. The second node N2 is a model of the deep N well region 110 will be. The resistance R1 between the first node N1 and the cathode terminal is modeled by the resistance between the first P-well region 121 and the first P + region 122. [

The collector terminal of the second transistor Q2 is connected to the first node N1, the base terminal is connected to the second node N2, and the emitter terminal is connected to the third node N3 via the resistor R2. And the third node N3 is a model of the third P + region 132. [ The resistance R2 is modeled by the resistance between the N-well region 131 and the deep N-well region 110. [

The emitter terminal of the third transistor Q3 is connected to the third node N3 through the resistor R3, the base terminal is connected to the second node N2, and the collector terminal is connected to the fourth node N4. The fourth node N4 is a model of the second P-well region 141 and the resistor R3 is a model of the resistance between the N-well region 131 and the deep N-well region 110. [

Further, the diode D is connected between the fourth node N4 and the first node N1 via the resistor R4. The resistor R 4 is a model of resistance between the second P + region 127 and the first P-well region 121.

In the above circuit diagram, the cathode terminal is connected to the ground and the voltage is applied to the anode terminal. The applied voltage is set to be less than the trigger voltage. A positive bias is applied between the third node N3 and the second node N2. However, a reverse bias is applied between the second node N2, which is the base terminal of the second transistor Q2, and the first node N1, which is the collector terminal. A reverse bias is also applied between the second node N2, which is the base terminal of the third transistor Q3, and the fourth node N4, which is the collector terminal. Therefore, the second transistor Q2 and the third transistor Q3 maintain the OFF state. Also, even if a bias is applied through the second node N2, the voltage applied to the anode terminal by the first transistor Q1 which is in the reverse bias state is not transmitted to the cathode terminal.

4 is another circuit diagram modeling the electrostatic discharge protection device shown in FIG. 2 according to a preferred embodiment of the present invention.

Referring to FIG. 4, a circuit diagram modeling the operation of FIG. 2 when the voltage applied to the anode terminal is equal to or greater than the trigger voltage is disclosed.

4, the connection relationship between the first transistor Q1 and the second transistor Q2 is the same as that described in FIG. However, the third transistor Q3 is omitted, and the voltage drop means is shown. That is, between the third P + region 132 modeled as the third node N3 and the second P-well region 141 shown as the fourth node N4, the voltage due to the punch-through of the deep N-well region 110 The descending means 200 is disposed. The voltage drop means 200 may be modeled as a specific constant voltage source. However, when an insulating film is formed between the N-well active region 130 and the second P-well active region 140 and a gate structure is formed thereon as described in FIG. 2, Due to this formation, the voltage drop means 200 can be modeled as a resistor with a low value. That is, the voltage drop means 200 may be modeled as a constant voltage source or a resistor.

When a voltage equal to or higher than the trigger voltage is applied to the anode terminal, a punch-through phenomenon occurs between the N-well active region 130 and the second P-well active region 140. That is, in the deep N-well region 110 between the N-well region 131 and the second P-well region 141, only a depletion region in which electrons or holes are not present appears and a channel May be formed under the insulating film. When only the depletion region appears, a tunneling phenomenon due to a predetermined voltage occurs, which can be modeled as a constant voltage source. Further, when a channel is formed under the insulating film, it can be modeled as a resistance element having a relatively low resistance value.

Therefore, when a voltage equal to or higher than the trigger voltage is applied through the anode terminal, the current path through the third node N3, the voltage drop means 200, the diode D, the resistor R4, the first node N1, . Therefore, the applied voltage drops to the holding voltage and the constant voltage state is maintained.

5 is a graph for explaining the effects of the electrostatic discharge protection device of FIGS. 2 to 4 according to a preferred embodiment of the present invention.

5, dotted lines indicate characteristics of the electrostatic discharge protection element having the configuration of FIG. 1, and solid lines show characteristics of the electrostatic discharge protection element having the configuration of FIG. 2 of the present invention.

First, in the configuration of FIG. 1, the punch-through operation occurs in the deep N-well region 20, which is a space between the P-well region 40 and the N- That is, the punch-through operation occurs due to the voltage difference across the depletion region formed by the reverse bias applied to the deep N-well region. Therefore, the trigger voltage Vt1 for generating the punch-through has a relatively high value.

However, in FIG. 2 of the present invention, punch-through occurs between the N-well active region 130 and the second P-well active region 140. Well active region 130 and the second P-well active region 140 before a punch-through phenomenon occurs between the first P-well active region 120 and the N- A punch-through occurs. Therefore, the trigger voltage in Fig. 2 is set to Vt2 lower than the trigger voltage in Fig. This means that even when the applied voltage is relatively low, the electrostatic discharge protection device operates by entering the holding state.

Therefore, when the electrostatic discharge protection device enters the holding state, the holding voltage Vh is set, and the holding current Ih is maintained to be increased or decreased according to the applied anode voltage.

Therefore, the electrostatic discharge protection device of the present invention can perform stable operation for a high voltage to which a high surge voltage is applied or a semiconductor device is damaged.

110: deep N-well region 120: first P-well active region
130: N-well active region 140: Second P-well active region

Claims (5)

A deep N-well region formed on the P-type substrate;
A first P-well active region formed on the deep N-well region and connected to the cathode terminal to block the flow of current when a voltage of a negative trigger voltage is applied to the anode terminal;
An N-well active region formed on the deep N-well region and formed with a distance L1 on a side of the first P-well active region, the N-well active region being connected to the anode terminal and modeled with a forward diode for a voltage applied; And
Well active region and is formed on the deep N-well region and is opposed to the first P-well active region about the N-well active region, And a second P-well active region electrically coupled to the first P-well active region, the second P-well active region being formed in the second P-well active region and inducing a punch-through phenomenon in the deep N- Discharge protection device. 2. The device of claim 1, wherein the first P-
A first P-well region formed on the deep N-well region and forming a reverse diode with the deep N-well region for a voltage applied to the anode terminal;
A first P + region formed on the first P-well region and connected to the cathode terminal;
A first N + region formed on the first P-well region and connected to the cathode terminal;
And a second P + well region formed on the first P-well region and electrically connected to the second P-well active region to supply a current to the cathode terminal when a level equal to or higher than a trigger voltage is applied to the anode terminal, Wherein the first and second electrodes are electrically connected to each other. 2. The method of claim 1, wherein the N-
An N-well region formed on the deep N-well region and communicating a voltage coupled to the anode terminal to the deep N-well region; And
And a third P + region formed on the N-well region and forming a forward diode with the N-well region for a voltage applied through the anode terminal. 4. The device of claim 3, wherein the second P-
A second P-well region formed on the deep N-well region and forming a deep N-well region and a reverse diode; And
And a second N + region formed on the second P-well region and electrically connected to the first P-well active region. The electrostatic discharge protection device according to claim 4, wherein when the voltage of the anode terminal is equal to or greater than the trigger voltage, the deep N-well region is punched-through.
KR1020140039461A 2014-04-02 2014-04-02 Electrostatic Discharge Device of using Lateral Insulated Gate Bipolar Transistor having lower Trigger Voltage KR101570928B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101031799B1 (en) * 2009-05-28 2011-04-29 주식회사 바우압텍 Electro-Static Discharge Protection Device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101031799B1 (en) * 2009-05-28 2011-04-29 주식회사 바우압텍 Electro-Static Discharge Protection Device

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