KR101562108B1 - A method of preventing pattern collapse - Google Patents

Abstract

A device comprises a substrate and at least three conductive characteristic parts embedded inside the substrate. Each conductive characteristic part includes upper width of x and lower width of y, while upper width and lower width (x1, y1) of a first conductive characteristic part has a dimension of x1<y1, upper width and lower width (x2, y2) of a first conductive characteristic part has a dimension of x2<y2, x2=y2 or x2>y2, and upper width and lower width (x3, y3) of a first conductive characteristic part has a dimension of x3>y3. The device also includes a gap structure separating the first conductive characteristic part and the second conductive characteristic part. The gap structure may include things such as air or a dielectric substance.

Description

{METHOD OF PREVENTING PATTERN COLLAPSE}

The present invention relates to the field of semiconductors.

This patent claims priority to U.S. Serial No. 61 / 776,651, filed March 11, 2013, the disclosure of which is incorporated herein by reference.

The semiconductor integrated circuit (IC) industry has undergone rapid growth. Technology advances in IC materials and design have created IC generations, each with smaller and more complex circuits than previous generations. During IC development, the geometric size (i.e., the smallest component (or line) that can be made using the fabrication process) has decreased, while the functional density (i.e., the number of devices interconnected per chip area) has increased overall . This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and fabrication, and similar developments in IC processing and fabrication are required for these developments to be realized.

For example, as the critical dimension (CD) of a feature scales down, the feature may have a high aspect ratio (ratio of height to width of the feature). When the high duty ratio reaches the threshold, the feature may actually collapse or fall down during the manufacturing process. Therefore, a way to prevent this from happening is necessary.

The device includes a substrate and at least three conductive features embedded in the substrate. Each conductive feature comprising a top width x and a bottom width y wherein the top width and bottom width (x1, y1) of the first conductive feature have a dimension of (x1 < y1), the top width of the second conductive feature and The lower width x2 and y2 have dimensions of (x2 <y2; x2 = y2; or x2> y2), and the upper and lower widths x3 and y3 of the third conductive feature have dimensions of (x3> y3) . The device also includes a gap structure that isolates the first conductive feature and the second conductive feature. The gap structure may include air or a dielectric.

The present disclosure is best understood from the following detailed description when taken in conjunction with the accompanying drawings. It is emphasized that in accordance with standard practice in the industry, various features are not drawn to scale but are used for illustrative purposes only. Indeed, the dimensions of the various features may be increased or decreased arbitrarily to clarify the description.
1 is a cross-sectional view of a device according to one or more embodiments.
2 is a flow diagram of a method of manufacturing a device for implementing one or more embodiments.
Figures 3-8, 9A-9C, and 10A-10C are cross-sectional views of forming a device to implement one or more embodiments.
11A-11C are cross-sectional views of structures according to one or more embodiments.
Figures 12-14 are examples of structures that benefit from one or more embodiments.
15A and 15B are a top view and a cross-sectional view of a metal island that will benefit from one or more embodiments.
16 is a cross-sectional view of a metal island that benefits from one or more embodiments.

It is to be understood that the following disclosure is intended to provide many different embodiments or examples for implementing various features of the invention. The components and configurations of the specific examples are described below to simplify the present disclosure. These are, of course, merely examples and not intended to be limiting. For example, in the following description, forming the first feature on or on the second feature may include an embodiment in which the first and second features are formed in direct contact, and the first and second features An embodiment in which additional features may be formed between the first feature and the second feature to prevent additional direct contact may also be included. The present disclosure may also repeat reference numerals and / or letters in various examples. This repetition is for the sake of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations described.

Referring now to FIG. 1, structure 100 is part of a device fabricated in accordance with one or more embodiments of the present disclosure. The structure 100 includes a substrate 102, a substrate pattern 104 formed on the substrate, and a trench 106 embedded into the substrate. In one embodiment, the trench 106 may be filled with a different insulator and / or dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, to form an isolation structure in the substrate 102. In another embodiment, the trench 106 is formed of Al, Cu, Ni, W, or a combination of these to form a connection line (e. G., A trench metal line) Lt; RTI ID = 0.0 &gt; a &lt; / RTI &gt; If the substrate pattern 104 collapses during fabrication, filling the trenches 106 may not be performed.

The pattern 104 includes a pattern height h and a pattern width w. In the case of a pattern having irregular or non-rectangular sides as shown in FIG. 1, the pattern width w may be defined at a midpoint (or average) of the pattern, such as at half the height. The ratio of h / w defines the aspect ratio of the pattern. The higher the aspect ratio, the more likely the pattern will collapse or fall off. The critical aspect ratio of the pattern is the aspect ratio of the pattern where the pattern begins to collapse or fall off. In other words, when the aspect ratio of the pattern is equal to or greater than the critical aspect ratio of the pattern, the pattern will collapse or fall. The critical aspect ratio of the pattern depends on various factors, one of which is the material that constitutes the pattern. In one embodiment, a pattern composed of a relatively soft material, such as a very low k dielectric material, will have a relatively low aspect ratio, compared to a pattern made of a relatively hard material such as metal.

Referring now to FIG. 2, a flow diagram of a method 200 for manufacturing a device in accordance with one or more embodiments of the present disclosure is illustrated. Additional steps may be provided during method 200, and after method 200, before and after method 200, and with respect to a further embodiment of method 200, some of the steps described may be replaced, . The method 200 will be further described below and more specific embodiments for manufacturing the device 300 using the method 200 will be described concurrently with reference to FIGS.

The method 200 begins at step 202 by receiving or providing a substrate. In this embodiment, the substrate is also referred to as a wafer substrate. Referring to Figure 3, a substrate 302 is provided. In this embodiment, the substrate 302 comprises a silicon wafer. Alternatively or additionally, the substrate 302 may comprise another elemental semiconductor, such as germanium; Compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; Or an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. In yet another alternative, the substrate 302 may comprise a dielectric layer, a conductive layer, or a combination thereof.

The method 200 proceeds to step 204 by depositing a first hardmask layer over the substrate and depositing a second hardmask layer over the first hardmask layer. Referring again to FIG. 3, a first hardmask layer 304 is deposited on the substrate 302 and a second hardmask layer 306 is deposited on the first hardmask layer 304. In one or more embodiments, the first hardmask layer 304 may comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable material. In some embodiments, the second hard mask layer 306 comprises a metal nitride compound, such as TiN. The first hardmask layer 304 and / or the second hardmask layer 306 may be deposited using a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process.

The method 200 proceeds to step 206 by forming a trench that is filled into the substrate. The trenches may be formed using a number of steps as shown and are described below with reference to Figures 4 and 5. Referring to FIG. 4, a resist pattern is formed on the second hard mask layer 306, and then etched to form a patterned second hard mask layer 306. Referring to FIG. 5, a patterned second hard mask layer 306 is used to etch the trenches 310 buried in the substrate 302.

The method 200 proceeds to step 208 by forming a first barrier layer in the trench next to the substrate and filling the trench with a conductive layer. The first barrier layer 312 is disposed on the sidewalls and the bottom of the trench 310 buried in the substrate 302 and the conductive layer 314 is disposed over the first barrier layer 312 to fill the trenches. . The first barrier layer 312 prevents conductive material from the conductive layer 314, such as metal, from migrating into the substrate 302. In this embodiment, the first barrier layer is also considered to be part of the conductive layer. In one or more embodiments, the first barrier layer 312 has a thickness in the range of approximately 20 to 500 Angstroms and comprises a metal and / or metal compound such as TaN / Ta. In some embodiments, the conductive layer 314 comprises a metal or metal alloy such as Al, Cu, W, an Al alloy, a Cu alloy, or a W alloy. One way to fill the trenches involves using deposition processes such as CVD, PVD, sputtering, or electroplating processes. In this embodiment, filling the trench further includes using a chemical mechanical polishing (CMP) process and a cleaning process. As shown in FIG. 6, the first hardmask layer 304 and the second hardmask layer 306 are also removed.

The method 200 proceeds to step 210 by forming a patterned third hardmask layer disposed over the buried conductive layer into the substrate. Referring to FIG. 7, a patterned mask layer 316 is formed over the conductive layer 314 and the substrate 302. In some embodiments, the patterned mask layer 316 comprises an organic material such as a photoresist. In some embodiments, the patterned mask layer 316 comprises a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. One manner of forming the patterned third mask layer 316 includes using a deposition process, such as a CVD or PVD process, a lithographic process, an etch process, and / or a cleaning process.

The method 200 proceeds to step 212 by etching the conductive layer and the first barrier layer using a patterned third hardmask layer to form a patterned conductive layer. 8, conducting features 318a-d are formed on first barrier layer 312 and air gap structures 320a-c are formed on conductive feature 318a -d). Note that in this embodiment, as shown in Figure 8, the air gap structure 320a-c also extends below the first barrier 312 to form a recess. In one embodiment, the conductive features 318a-d comprise Cu. Since Cu has a strong mechanical strength, the corresponding pattern or feature will have a relatively large critical aspect ratio. Thus, the conductive features 318a-d can be further scaled down to a dimension as low as 10 nm without the pattern or feature becoming collapsed. In this embodiment, by filling the air gap structures 320a-c with a dielectric material such as a low-k dielectric material, the pattern or features associated with the low k dielectric material pattern, Without the problem of collapse, conductive lines or wire lines with small dimensions, such as 10 nm, are embedded into the low k dielectric material. One way to form the conductive features includes using an etching process, a CMP process, and a cleaning process.

FIG. 2 shows two alternative processes to be performed after step 212. In a first alternative embodiment, the method 200 proceeds to step 222 along path A by depositing a second barrier over the substrate and the conductive features buried in the substrate. Referring to FIG. 9A, a second barrier layer 322 is formed over the conductive features 318a-d and the substrate 302. The second barrier layer 322 covers all open surfaces such as the open surfaces of the substrate 302 and the sidewalls and top surfaces of the conductive features 318a-d. In one embodiment, the second barrier layer 322 comprises a silicon carbon (SiC), silicon nitride (SiN), silicon carbon nitride (SiCN), or silicon oxide (SiO _2). In this embodiment, the thickness of the second barrier layer 322 is in the range of approximately 20 to 100 angstroms. One way to deposit the second barrier layer 322 is to use an atomic layer deposition (ALD) process.

Following the process of path A, the method 200 proceeds to step 224 by forming a second dielectric layer on the second barrier layer disposed over the buried conductive features into the substrate. In one embodiment, forming the second dielectric layer 324a, as shown in FIG. 9B, comprises filling the air gap structures 320a-c between the conductive features 318a-d, respectively. In another embodiment, forming the second dielectric layer 324b, as shown in FIG. 9C, includes holding the air gap structures 320a-c. That is, the second dielectric layer 324b does not fill the air gap structure below. In some embodiments, the second dielectric layer (324a and 324b) comprises a dielectric material such as silicon oxide (SiO _2), silicon nitride (SiN), or silicon oxynitride (SiON). In a further embodiment, the second dielectric layers 324a and 324b may be formed of a material such as fluorine doped silicon oxide, carbon doped silicon oxide, porous silicon oxide, porous carbon doped silicon oxide, organic polymer, k dielectric material. The second dielectric layer 324a and / or 324b may be formed using a CVD or PVD process.

Referring again to FIG. 2, in another process, the method 200 proceeds from step 212 to step 232 along path B by depositing a second barrier layer over the conductive features. Referring to FIG. 10A, second barrier layers 326a-d are formed over the conductive features 318a-d, respectively. In this embodiment, the second barrier layer 326a-d covers only the sidewalls and top portions of the conductive features 318a-d. In this embodiment, the second barrier layer 326a-d has a thickness in the range of approximately 10 to 50 angstroms and includes a metal such as cobalt (Co). The second barrier layer 326a-d may be formed using a CVD or PVD process.

Following the process of path B, the method 200 proceeds to step 234 by forming a second dielectric layer over the second barrier layer disposed on the buried conductive features into the substrate. In one embodiment, as shown in FIG. 10B, forming the second dielectric layer 324c includes filling the air gap structures 320a-c between the conductive features 318a-d. In another embodiment, as shown in FIG. 10C, depositing the second dielectric layer 324d may be accomplished by filling the air gap structure 320a-c without filling the second dielectric layer 324d, 0.0 &gt; 320a-c. &Lt; / RTI &gt; In an alternate embodiment, the second dielectric layer (324c or 324d) comprises a dielectric material such as silicon oxide (SiO _2), silicon nitride (SiN), or silicon oxynitride (SiON). In yet another alternative embodiment, the second dielectric layer 324c or 324d may also include a layer of fluorine doped silicon oxide, carbon doped silicon oxide, porous silicon oxide, porous carbon doped silicon oxide, organic polymer, Lt; RTI ID = 0.0 &gt; k dielectric &lt; / RTI &gt;

Referring now to FIG. 11A, a cross-sectional view of a conductive feature 318 fabricated by using the method 200 in accordance with one or more embodiments is illustrated. As shown in Fig. 11A, the conductive feature designated by reference numeral 318a is a trapezoidal structure. The trapezoidal structure includes a lower width ya and an upper width xa. In this embodiment, the lower portion of the trapezoidal structure is closer to the substrate on which the trapezoidal structure is formed than the upper portion of the trapezoidal structure. In this embodiment, the lower width ya on the trapezoidal structure is larger than the upper width xa.

The device 300 may include additional conductive features. As shown in FIG. 11B, the conductive feature designated by reference numeral 318b is a parallelogram. The parallelogram structure includes a lower width yb and an upper width xb. In this embodiment, the lower width yb on the parallelogram structure is approximately equal to the upper width xb. As shown in Fig. 11C, the conductive feature designated by reference numeral 318c is a trapezoidal structure. The trapezoidal structure includes a lower width yc and an upper width xc. In this embodiment, the lower width yc on the parallelogram structure is smaller than the upper width xc.

FIGS. 12-14 illustrate an example of a structure 400 fabricated using the method 200 in accordance with one or more embodiments. The structure 400 includes a substrate 402, conductive features 404a-j buried in the substrate 402, and air gap structures 406a-h that separate the conductive features 404a-j, respectively . It is to be understood that other configurations of the device 400 and various items may be included or omitted. The device 400 is an exemplary embodiment and is not intended to be limited to the invention other than those explicitly recited in the claims.

In some embodiments, the substrate 402 includes a dielectric material such as silicon oxide (SiO _2), silicon nitride (SiN), or silicon oxynitride (SiON). In another embodiment, the substrate 402 comprises a low k dielectric material such as fluorine doped silicon oxide, carbon doped silicon oxide, porous silicon oxide, porous carbon doped silicon oxide, organic polymer, or silicon based polymer . In some embodiments, the conductive features 404a-j comprise a metal or metal alloy such as W, W alloy, Al, Al alloy, Cu or Cu alloy. In at least one embodiment, the air gap structure (406a-h) is a silicon oxide (SiO _2), silicon nitride (SiN), or silicon oxynitride nitride (SiON) with a dielectric material, or a fluorine-doped silicon oxide, carbon-doped such May be filled by a low k dielectric material such as silicon oxide, porous silicon oxide, porous carbon doped silicon oxide, organic polymer, or silicon based polymer.

As shown in Fig. 12, structure 400a includes a substrate 402, conductive features 404a-d embedded in the substrate 402, and air (not shown) isolating each of the conductive features 404a- Gap structures 406a-c. The conductive features 404a-d are formed by forming a trench in the substrate 402, filling the trench with a conductive material, and performing an etching process. In one embodiment, the conductive features 404a-d may include a Cu line having a pitch as low as approximately 10 nm without Cu line collapse or falling problems.

As shown in Fig. 13, structure 400b includes a substrate 402, conductive features 404e-g, and air gap structures 406d and 406e. The conductive features 404e-g are embedded in the substrate 402 and the air gap structure 406d divides the conductive features 404e and the air gap structure 406e divides the conductive features 404g.

As shown in Fig. 14, structure 400c includes a substrate 402, conductive features 404h-j, and air gap structures 406f-g. The conductive features 404h-j are formed in the substrate 402 and the air gap structure 406f intercepts the conductive features 404h and the air gap structure 406g cuts the conductive features 404i , The air gap structure 406h breaks off both of the conductive features 404i and 404j. In some embodiments, air gap structures 406a-h may be further filled with a dielectric material.

Referring now to FIGS. 15A and 15B, a top view and a cross-sectional view of a device 450 according to one or more embodiments are illustrated. The device 450 includes a substrate 402 and conductive features 452a, 452b, and 452c. The conductive features 452a-c are embedded into the substrate 402. In one embodiment, the conductive features 452a include small dimensions such as 10 nm. Also, the conductive features 452a and 452b have dimensions x and y (see FIGS. 11A-11C) with x <y, x = y, or x> y. Conductive feature 452c has dimensions x and y that are x > y. Also, in one embodiment, there is a gap structure 454 filled with air or dielectric material between the conductive features 452a and 452b. In this embodiment, the small conductive feature is also referred to as a small metal island. In one embodiment, the small metal island forms a large metal feature, etches the large metal feature to form a small metal feature that is isolated by the air gap structure, and the air gap feature is filled with a dielectric material, Is formed by using the method 200 as shown in Fig. 2, such as forming a small metal island.

Referring now to FIG. 16, a device 500 includes a substrate 402 and conductive (e.g., Cu) features 552a, 552b, 552c, 552d, and 552e. The conductive features 552a-e are embedded into the substrate 402. In one embodiment, one of the conductive features, e.g., 552c, has dimensions x and y of x < y (see Figures 11a-11c), one of the conductive features, e.g., 552d, One of the conductive features, e.g., 552e, has dimensions x and y of x > y. Also, in one embodiment, there is a gap structure 554 filled between conductive features 552a and 552b, between 552b and 552c, and between 552c and 552d, filled with air or a dielectric material.

In this embodiment, two trenches are formed using a damascene process. Conductive features 552a through 552d are formed in the first trench and conductive features 552e are formed in the second trench. Similar to the way trenches 310 are filled with conductive layer 314, both trenches are filled with a conductive material at the same time, as described above with respect to FIG. The process continues in a first trench similar to the process described above with respect to Figures 7 to 10C, and the conductive layer will be etched to form the conductive features 552a-d. The conductive layer will not be etched in the second trench and will thus form the conductive feature 552e.

In the above description, various processes such as a film deposition process, a lithography process, an etching process, an ion implantation process, a CMP process, and a cleaning process are performed by manufacturing a device. In this embodiment, the film deposition process includes a PVD process such as evaporation and DC magnetron sputtering, a plating process such as electroless plating or electrolytic plating, atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD) , Or CVD processes such as high density plasma CVD (HDP CVD), ion beam deposition, spin-on coating, metal-organic decomposition (MOD), ALD processes and / or other suitable methods.

In some embodiments, the lithography process includes coating a resist film on a wafer substrate, exposing the resist film deposited on the wafer substrate with an optical lithography tool or electron beam writer, developing the exposed resist film, Forming a resist pattern for the process or etching process. Coating the resist film on the wafer substrate involves performing a dehydration process before applying the resist film on the wafer substrate, which can enhance the adhesion of the resist film to the wafer substrate. The dewatering process may include baking the substrate at a high temperature for a predetermined duration or applying a chemical such as hexamethyldisilizane (HMDS) to the substrate. The coating of the resist film on the wafer substrate may include a soft bake (SB). Exposing a resist film deposited on a wafer substrate involves using a light exposure tool or a charged particle exposure tool. The photolithographic tool may include I-line, deep ultraviolet (DUV), or extreme ultraviolet (EUV) tools. The charged particle exposure tool includes an electron beam or ion beam tool. Using a light exposure tool involves using a mask. The mask may be a binary mask (BIM), a super binary mask (SBIM), or a phase shift mask (PSM), and the PSM may be an alternate phase shift mask phase shift mask or attenuated phase shift mask (att.). Developing the exposed resist film may include post exposure bake (PEB), post-develop bake (PDB) processes, or a combination thereof.

The etching process may include dry (plasma) etching, wet etching, and / or other etching methods. For example, the dry etching process may be carried out using an oxygen containing gas, a fluorine containing gas (e.g., CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ , and / or C ₂ F ₆ ), a chlorine containing gas , Cl _2, CHCl _3, CCl _4, and / or BCl _3), a bromine-containing gas (e.g., HBr and / or CHBr _3), containing gas, or other suitable gas and / or plasma, and / or a iodide Combinations can be implemented.

Accordingly, this disclosure describes devices and methods. In one embodiment, the device comprises a substrate and at least three conductive features embedded in the substrate. Each conductive feature comprising a top width x and a bottom width y wherein the top width and bottom width x1, y1 of the first conductive feature have a dimension of (x1 < y1), the top width of the second conductive feature and The lower width x2 and y2 have dimensions of (x2 <y2; x2 = y2; or x2> y2) and the upper and lower widths x3 and y3 of the third conductive feature have dimensions of (x3> y3) . The device also includes a gap structure that isolates the first conductive feature and the second conductive feature. The gap structure may include air or a dielectric.

In another embodiment, the device comprises a substrate, at least two conductive features embedded in the substrate, wherein the conductive features include a trapezoidal shape having a lower width greater than the top width, and an air gap structure . The device further comprises a first barrier layer separating the substrate and the conductive feature. The first barrier layer comprises TaN / Ta. The device further includes a second barrier layer disposed over the two conductive features separated by an air gap structure. The second barrier layer may extend over the substrate. The second barrier layer comprises Co, SiC, SiN, SiCN, or SiO _2. The device further comprises a dielectric layer disposed over the air gap structure, wherein the air gap structure is embedded below the dielectric layer without filling the air gap structure. The device further comprises an air gap structure filled by a dielectric layer. Conductive features include Cu, Cu alloys, Al, Al alloys, W, or W alloys.

In another embodiment, the present disclosure describes a device comprising a substrate and at least three conductive features embedded in the substrate. Each conductive feature includes a top width x and a bottom width y. The top and bottom widths (x2, y2) of the second conductive feature have a dimension of (x2 <y2; x2 = y2) Or x2 &gt; y2, and the upper and lower widths (x3, y3) of the third conductive feature have dimensions of (x3 > y3). The device further comprises a gap structure isolating the first conductive feature and the second conductive feature. The gap structure may be an air gap, a dielectric, or a combination thereof.

In another embodiment, the present disclosure describes a device comprising a substrate and three conductive features embedded in the substrate. The first conductive feature includes a top width x1 and a bottom width y1, wherein (x1 <y1; x1 = y1; or x1 > y1). The second conductive feature includes a top width x2 and a bottom width y2, wherein (x2 <y2; x2 = y2; or x2> y2). The third conductive feature includes a top width x3 and a bottom width y3, wherein x3 > y3. The device further comprises a gap structure, such as air or dielectric, that isolates the first and second conductive features.

The present disclosure also describes a method of manufacturing a device. In one embodiment, the method comprises: receiving a substrate; forming a trench in the substrate; filling the trench with a conductive material; filling the trench; placing a first barrier layer on the bottom and sidewalls of the trench and over the first barrier layer And performing an etching process on the conductive layer using a hard mask to form at least two conductive features that are isolated by the air gap structure. The method further includes depositing a second barrier layer over the two conductive features separated by the air gap structure. The method further includes extending the second barrier layer over the substrate. The method further includes depositing a dielectric layer over the second barrier layer disposed over the two conductive features separated by the air gap structure. Deposition of the dielectric layer includes embedding an air gap structure underneath. Depositing the dielectric layer further includes filling the air gap structure.

In another embodiment, a method includes receiving a substrate, forming a trench in the substrate, filling the trench with a conductive material-filling the trench comprises depositing a first barrier layer on the bottom and sidewalls of the trench and a second barrier layer on the first barrier layer, - performing an etching process using a hard mask to form at least two conductive features separated by an air gap structure in the conductive layer, to deposit a second barrier layer over the two conductive features, And depositing a dielectric layer over the second barrier layer. The method further includes using a lithographic process. Depositing the second barrier includes depositing a second barrier layer over the substrate. Deposition of the dielectric layer includes embedding an air gap structure underneath. Depositing the dielectric layer further includes filling the air gap structure.

In another embodiment, the method includes forming a first trench in the substrate and filling the first trench with a conductive material. Filling the first trench includes forming a first barrier layer on the bottom and sidewalls of the first trench and forming a conductive layer disposed over the first barrier layer. The method further includes performing an etching process on the conductive layer using a hard mask to form first and second conductive features that are isolated by the gap structure. The first conductive feature includes a top width smaller than the bottom width.

The foregoing is a description of features of various embodiments to enable those skilled in the art to more fully understand the aspects of the disclosure. Those skilled in the art will readily appreciate that the present disclosure can readily be used as a basis for designing or modifying other processes and structures to accomplish the same purposes and / or to achieve the same advantages as the embodiments disclosed herein You should know. It should be understood by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of this disclosure and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the disclosure.

102: substrate 104: substrate pattern
106: Trench 300: Device
302: substrate 304: first hard mask layer
306: second hard mask layer 310: trench
312: first barrier layer 314: conductive layer
316: patterned mask layer 318a-d: conductive feature
320a-c: air gap structure 322, 326a-d: second barrier layer

Claims (10)

Board;
At least three conductive features embedded in the substrate, each conductive feature comprising a top width x and a bottom width y, wherein the top width and bottom width (x1, y1) of the first conductive feature (X2 &lt;y2; or x2 &gt; y2) of the second conductive feature, The top width and bottom width of the part (x3, y3) have dimensions of (x3 &gt;y3); And
And a gap structure isolating the first conductive feature and the second conductive feature,
Wherein the top surface of the at least three conductive features is flush with the top surface of the substrate. The device of claim 1, further comprising a first barrier layer separating the substrate from one of the at least three conductive features. The device of claim 1, further comprising a second barrier layer disposed over the at least three conductive features. Board;
A first conducting feature embedded in the substrate, wherein the conducting feature comprises a top width x1 and a bottom width y1, wherein (x1 <y1; x1 = y1; or x1>y1);
A second conductive feature buried in the substrate, wherein the second conductive feature includes a top width x2 and a bottom width y2, wherein (x2 &lt;y2; x2 = y2; or x2 &gt;y2);
A third conductive feature embedded in the substrate, the top width x3 and the bottom width y3, wherein (x3 &gt;y3); And
And a gap structure isolating the first conductive feature and the second conductive feature,
Wherein the top surface of the first conductive feature, the second conductive feature, and the third conductive feature are flush with the top surface of the substrate. A method of forming a device,
Providing a substrate;
Forming a first trench in the substrate;
Filling the first trench with a conductive material, wherein filling the first trench includes forming a first barrier layer on the lower and sidewalls of the first trench and forming a conductive layer disposed over the first barrier layer -; And
Performing an etching process on the conductive layer using a hard mask to form a first conductive feature and a second conductive feature that are isolated by a gap structure,
Wherein the first conductive feature comprises a top width smaller than the bottom width. 6. The method of claim 5, further comprising depositing a second barrier layer over the two conductive features separated by the gap structure. 6. The method of claim 5, further comprising extending a second barrier layer over the substrate. 6. The method of claim 5, further comprising depositing a dielectric layer over a second barrier layer disposed over the two conductive features separated by the gap structure. 6. The method of claim 5, further comprising filling the gap structure with a dielectric. The method of claim 5,
Forming a second trench in the substrate; And
Filling the second trench with the conductive material-filling the second trench comprises forming the first barrier layer on the lower and sidewalls of the second trench and forming a conductive layer disposed over the first barrier layer - &lt; / RTI &gt;
Wherein the filled second trench forms a third conductive feature,
Wherein the third conductive feature comprises a top width that is greater than the bottom width.

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